Semiconductor structure

Abstract

The disclosure provides a semiconductor structure with a low resistance via contact. An example semiconductor structure includes a substrate, a dielectric layer disposed over the substrate, a resistor disposed in the dielectric layer, and a resistive via contact disposed in the dielectric layer of the resistor. The resistive via contact also includes a first layer disposed on and in contact with the resistor, a second layer disposed on the first layer, and a third layer disposed on the second layer. The first layer has a first thickness and a first resistivity, the second layer has a second thickness, and the third layer has a third thickness and a second resistivity. The first thickness is greater than the third thickness, and the first resistivity is less than the second resistivity.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to semiconductor devices, and more particularly to via contacts for interconnecting conductive features between different layers of a semiconductor structure. Background Art

[0002] Due to the continuous increase in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.), the semiconductor industry has experienced rapid growth. In most cases, the iterative reduction of the minimum feature size enables an increase in the integration density, allowing more components to be integrated into a given area. There is always a need to improve the performance of semiconductor devices. Summary of the Utility Model

[0003] One aspect of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a substrate, a dielectric layer, a resistor, and a resistive via contact. The dielectric layer is disposed above the substrate. The resistor is disposed within the dielectric layer, and the resistor extends from a first sidewall to a second sidewall along a first horizontal direction. The resistive via contact is disposed within the dielectric layer, wherein the resistive via contact continuously extends from a first side to a second side along the first horizontal direction. The resistive via contact further includes a first layer, a second layer, and a third layer. The first layer is disposed on and in contact with the resistor, wherein the first layer has a first thickness and a first resistivity. The second layer is disposed on and in contact with the first layer, wherein the second layer has a second thickness. The third layer is disposed on and in contact with the second layer, wherein the third layer has a third thickness and a second resistivity. Wherein the first thickness is greater than the third thickness, and the first resistivity is less than the second resistivity.

[0004] One aspect of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a substrate, a dielectric layer, a resistor, and a resistive contact structure. The dielectric layer is disposed above the substrate. The resistor is disposed within the dielectric layer, and the resistor extends from a first sidewall to a second sidewall along a first horizontal direction. The resistive contact structure includes a plurality of resistive via contacts disposed in the dielectric layer, wherein each resistive via contact continuously extends from a first side to a second side along the first horizontal direction. Each resistive via contact further includes a first layer, a second layer, and a third layer. The first layer, disposed on and in contact with the resistor, wherein the first layer has a first thickness and a first resistivity. The second layer is disposed on and in contact with the first layer, wherein the second layer has a second thickness. The third layer is disposed on and in contact with the second layer, wherein the third layer has a third thickness and a second resistivity. Wherein the first thickness is greater than the third thickness, and the first resistivity is less than the second resistivity.

[0005] One aspect of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a substrate, a dielectric layer, a resistor, and a resistor contact structure. The dielectric layer is disposed over the substrate. The resistor is disposed within the dielectric layer and extends from a first sidewall to a second sidewall along a first horizontal direction. The resistor contact structure includes a plurality of resistor vias contacts arranged in columns along a second horizontal direction substantially perpendicular to the first horizontal direction, and each resistor via contact extends continuously from a first side to a second side along the first horizontal direction. Each resistor via contact further includes a first layer, a second layer, and a third layer. The first layer is disposed on and in contact with the resistor, wherein the first layer has a first thickness and a first resistivity. The second layer is disposed on and in contact with the first layer, wherein the second layer has a second thickness. The third layer is disposed on and in contact with the second layer, wherein the third layer has a third thickness and a second resistivity. Wherein the first thickness is greater than the third thickness, the third thickness is greater than the second thickness, and the first resistivity is at least 10% less than the second resistivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with industry standard practice, various features may not be drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0007] Figure 1A A layout cross-sectional schematic diagram of a semiconductor structure is shown in accordance with some embodiments;

[0008] Figure 1B Shown in accordance with some embodiments Figure 1A A top-down schematic diagram of a region of the semiconductor structure;

[0009] Figure 1C Shown in accordance with some embodiments Figure 1A A cross-sectional schematic diagram of a region of the semiconductor structure;

[0010] Figure 1D A top-down schematic diagram of a semiconductor structure of another example is shown in accordance with some embodiments;

[0011] Figure 2 A cross-sectional schematic diagram of a semiconductor structure of another example is shown in accordance with some embodiments;

[0012] Figure 3 A cross-sectional schematic diagram of a semiconductor structure of another example is shown in accordance with some embodiments;

[0013] Figure 4A A layout cross-sectional schematic diagram of a semiconductor structure is shown in accordance with some embodiments;

[0014] Figure 4BSchematic top view of a region of a semiconductor structure shown in accordance with some embodiments Figure 1A ;

[0015] Figure 4C Schematic cross-sectional view of a region of a semiconductor structure shown in accordance with some embodiments Figure 1A ;

[0016] Figure 4D Schematic top view of a semiconductor structure of another example shown in accordance with some embodiments

[0017] Figure 5 Schematic cross-sectional view of a semiconductor structure of another example shown in accordance with some embodiments

[0018] Figure 6 Schematic cross-sectional view of a semiconductor structure of another example shown in accordance with some embodiments

[0019] Figure 7A Schematic top view of a semiconductor structure of another example shown in accordance with some embodiments

[0020] Figure 7B Schematic top view of a semiconductor structure of another example shown in accordance with some embodiments

[0021] Figure 8 Flowchart of an example method for manufacturing a semiconductor structure shown in accordance with some embodiments

[0022]

Symbol Description

[0023] 100A: Semiconductor structure

[0024] 100B: Semiconductor structure

[0025] 101: Substrate

[0026] 102: Dielectric layer / ILD layer

[0027] 103: Dielectric layer / ILD layer

[0028] 104: CESL

[0029] 105: CESL

[0030] 107: STI layer

[0031] 110: Workpiece

[0032] 111: Metal gate

[0033] 112: Conductive feature

[0034] 113: Conductive feature

[0035] 114: Barrier layer

[0036] 115: Plug

[0037] 116: Barrier layer

[0038] 117: Plug

[0039] 130: Region

[0040] 131: Resistor

[0041] 140: Resistive contact structure

[0042] 150: Resistive via contact

[0043] 150-1,150-2,150-3: Resistive via contact

[0044] 151: First layer

[0045] 151a,151c: First layer

[0046] 152: Second layer

[0047] 153: Third layer

[0048] 154: Main part

[0049] 155: Side part

[0050] 156: Side part

[0051] 157: Side part

[0052] 158: Side part

[0053] 159: Top surface

[0054] 160: Main part

[0055] 161: Top surface

[0056] 162: Bottom surface

[0057] 163: First end

[0058] 164: Second end

[0059] 165: Via contact

[0060] 166: First interface / Interface

[0061] 167: First side

[0062] 168: Second side

[0063] 169: Second interface

[0064] 171: Top surface

[0065] 172: First end

[0066] 173: Second end

[0067] 181: First side

[0068] 182: Second side

[0069] 183: First side

[0070] 184: Second side

[0071] 200: Semiconductor structure

[0072] 300: Semiconductor structure

[0073] 400A: Semiconductor structure

[0074] 400B: Semiconductor structure

[0075] 430: Region

[0076] 440: Resistive contact structure

[0077] 450: Resistive viacon contact

[0078] 450a, 450b, 450c: Resistive viacon contact

[0079] 451, 451a, 451b, 451c: First layer

[0080] 452, 452a, 452b, 452c: Second layer

[0081] 453, 453a, 453b, 453c: Third layer

[0082] 455, 456: Bottom part

[0083] 457, 457a, 457b, 457c: Side part

[0084] 458, 458a, 458b, 458c: Side part

[0085] 467, 467a, 467b, 467c: First side

[0086] 468, 468a, 468b, 468c: Second side

[0087] 472, 472a, 472b, 472c: First end

[0088] 473, 473a, 473b, 473c: Second end

[0089] 500: Semiconductor structure

[0090] 600: Semiconductor structure

[0091] 700A: Semiconductor structure

[0092] 700B: Semiconductor structure

[0093] 800: Method

[0094] 802, 804, 806, 808, 810: Steps

[0095] A - A’: Line

[0096] D: Distance

[0097] FEOL: Front - end of line

[0098] L CS : Total length

[0099] L R : Length

[0100] L VC : Length

[0101] T R : Thickness

[0102] T 1 , T 2 , T 3 : Thickness

[0103] W R : Width

[0104] W VC : Width

[0105] X: Direction

[0106] Y: Direction

[0107] Z: Direction Detailed implementation manners

[0108] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. The following describes specific examples of components and arrangements to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature hereinafter may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate the relationship between the various embodiments and / or configurations discussed.

[0109] In addition, for descriptive purposes, the present disclosure may use spatial relative terms, such as "below", "beneath", "lower", "above", "upper", etc., to describe the relationship of one element or feature to one or more other elements or features, as shown in the accompanying drawings. Spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0110] In addition, the source / drain region(s) may refer to the source or drain individually or collectively depending on the context. For example, a device may include a first source / drain region and a second source / drain region and other components. The first source / drain region may be the source region, and the second source / drain region may be the drain region, or vice versa. Those of ordinary skill in the art can understand various variations, modifications, and substitutions.

[0111] Some embodiments of the present disclosure are described below. Additional operations may be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the described stages may be replaced or removed. Some of the features described below may be replaced or removed, and additional features may be added for different embodiments. Although some embodiments perform operations in a specific order when discussed, these operations may be performed in another logical order.

[0112] Summary.

[0113] In semiconductor devices, particularly radio frequency (RF) devices, resistors (sometimes also referred to as "high-resistance areas" or "HiR areas") are important passive components. Resistors can be used for biasing, impedance matching, filtering, gain control, transmission line termination, improving noise reduction signal integrity, frequency response applications, etc. A resistor disposed in a layer of a semiconductor device is typically electrically connected to another active or passive component in the same or a different layer of the semiconductor device through in-layer or inter-layer via contacts coupled to the resistor. Via contacts (also referred to as "resistive via contacts") that can be used to connect to a resistor are typically formed in a process separate from the formation of other via contacts used to connect to non-resistive elements (e.g., transistors) in the resistor. The same semiconductor structure. Via contacts (also referred to as "resistive via contacts") that can be used to connect to a resistor and other via contacts used to connect to non-resistive elements in the same semiconductor structure are typically formed in different processes. Additionally, resistive via contacts are typically composed of a conductive material with good acid resistance or etch resistance to protect the resistive via contacts and the resistor thereunder from acid corrosion and metal loss during subsequent manufacturing processes. Compared with conventional materials used for non-resistive via contacts, the acid-resistant material of resistive via contacts typically has a relatively high resistivity. Therefore, the resistance of the resistive via contacts cannot be ignored and may sometimes be quite high.

[0114] In addition, the size of the resistors used in RF devices may be relatively large. For example, the resistors according to the present disclosure can be thin-film type resistors having a relatively large two-dimensional area, and the resistive via contacts connected to the resistors also have a relatively large size in order to provide sufficient physical contact area and electrical connectivity for the resistors. However, this may cause problems. Due to the relatively large size and / or relatively high resistivity of the resistive via contacts, the resistive via contacts can be regarded as additional resistors connected in series with the underlying resistor, and may cause an adverse increase in the overall resistance in the circuit and have a significant impact on the functional performance of the underlying resistor. In particular, the high resistance of the resistive via contacts may cause serious problems in RF devices where the resistors are required to strictly meet the specifications (i.e., the designed resistance). The high resistance of the resistive via contacts may further lead to instability of the device and a low yield rate during the wafer acceptance testing (WAT) process.

[0115] One aspect provided in this disclosure relates to a novel heterogeneous resistor via contact having a multi-layer structure. According to some embodiments, the resistor via contact may have a first layer disposed on a lower resistor, a second layer disposed on the first layer, and a third layer disposed on the second layer. The first layer may constitute the main part of the resistor contact structure and include a conductive material having a low resistivity; the second layer serves as an adhesive layer between the first layer and the third layer to improve the bonding strength between the first layer and the third layer; the third layer serves as a protective layer and includes an acid-resistant material for protecting the resistor contact structure and the lower resistor from corrosion during subsequent manufacturing processes. The heterogeneous resistor contact structure according to this disclosure has a significantly lower resistivity compared to conventional resistor via contacts without sacrificing acid resistance.

[0116] One aspect provided in this disclosure relates to a heterogeneous resistor contact structure having a pattern of a plurality of resistor via contacts with relatively small sizes. Compared to a single large via contact, the plurality of smaller via contacts can further reduce the resistance and capacitance of the resistor contact structure and provide better electrical connectivity to the lower resistor. In addition, the pattern of the plurality of smaller via contacts allows for a higher device density on the semiconductor structure, provides better thermal conductivity compared to a single large via contact, and the plurality of smaller via contacts can better dissipate heat from the semiconductor structure, reducing the risk of overheating, improving the overall thermal performance, and potentially reducing the manufacturing cost.

[0117] An exemplary semiconductor structure with low-resistance via contacts.

[0118] Figures 1A to 1C Some embodiments according to this disclosure illustrate an example semiconductor structure 100A including a contact structure 140 (also referred to as a "resistor contact structure", "contact assembly", "resistor contact assembly", or the like) disposed on a resistor 131. Figure 1A A cross-sectional view of the semiconductor structure 100A is shown. Figure 1B A top view showing the layout of a selected region 130 of the semiconductor structure 100A and the position of the resistor contact structure 140 relative to the resistor 131 is shown. Figure 1C Showing the semiconductor structure 100A in region 130 along Figure 1B a cross-sectional view taken along line A-A'.

[0119] In the illustrated example, semiconductor structure 100A includes, among other components, a workpiece 110. The workpiece 110 may include a substrate 101, at least one dielectric layer (e.g., dielectric layer 102), one or more metal gates 111, and a plurality of conductive features 112 and 113. In some embodiments, semiconductor structure 100A also includes at least one contact etch stop layer (CESL), such as CESL 104 and CESL 105, disposed on the workpiece 110. Semiconductor structure 100A further includes a dielectric layer 103 disposed on CESL 105 and at least one via contact 165 disposed within the dielectric layer 103. In some embodiments, a resistor 131 is disposed on CESL 105 and above the workpiece 110. A resistor contact structure 140 is disposed on the resistor 131 and within the dielectric layer 103. The resistor contact structure 140 is electrically coupled to the resistor and is configured to electrically connect the resistor to another active or passive element in the semiconductor structure 100A. The resistor contact structure 140 may include one or more resistor via contacts 150, and each resistor via contact 150 may also include a first layer 151, a second layer 152, a third layer 153, etc., sequentially stacked on the resistor 131. More examples of the resistor contact structure 140 and the resistor via contact 150 will be described in detail with reference to Figures 1B to 1C more examples of the resistor contact structure 140 and the resistor via contact 150.

[0120] In some embodiments, the substrate 101 may be a silicon substrate (e.g., a silicon wafer). Alternatively, the substrate 101 may include another elemental semiconductor, such as germanium; compound semiconductors, including silicon carbide, gallium nitride, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium phosphide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium arsenide phosphide indium; or combinations thereof. In an embodiment, the substrate 101 may include indium tin oxide (ITO) glass, include a silicon-on-insulator (SOI) substrate, be strained and / or stressed to enhance performance, include epitaxial regions, doped regions, and / or include other suitable features and layers.

[0121] Dielectric layers 102 and 103 are formed over substrate 101 and are also referred to as interlayer dielectric (ILD) layers. Each ILD layer 102 and 103 may include oxides derived from tetraethyl orthosilicate (TEOS) (e.g., an oxide layer formed using TEOS as a precursor), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. Each ILD layer may be formed by plasma enhanced chemical vapor deposition (PECVD), flowable CVD (FCVD), or other suitable methods. ILD layers 102 and 103 have the same or different materials.

[0122] One or more metal gates 111 may be connected to one or more active / passive elements (not shown) constructed within or above the active regions. The active and / or passive elements may include one or more transistors, such as p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), multi-gate FETs such as FinFETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, gate-all-around FETs (GAAFETs), bipolar transistors, high-voltage transistors, high-frequency transistors, static random access memory (SRAM) cells, other storage cells, resistors, capacitors, and inductors.

[0123] The conductive features 112 and 113 are electrically coupled to the metal gate 111 and / or other features in the workpiece 110. The conductive features 112 and 113 are configured to connect the metal gate 111 to other devices or functional components in different dielectric layers of the semiconductor structure 100A to provide a circuit path. In some embodiments, the metal gate 111 may be part of a transistor (not shown). The transistor may also include source / drain (S / D) features and other transistor gate features. In some embodiments, the metal gate 111 is in the form of a gate structure or a gate stack and also includes gate spacers. In some embodiments, the conductive feature 112 is electrically connected to the metal gate 111 of the transistor, and the conductive feature 113 is electrically coupled to the S / D features of the same transistor or a different transistor.

[0124] The conductive feature 112 may include a plug 115 and a barrier layer 114 disposed on the sidewall of the plug 115. Similarly, the conductive feature 113 may include a plug 117 and a barrier layer 116 disposed on the sidewall of the plug 117. The plugs 115 and 117 may each include a conductive material of a metal, a metal compound, or a metal alloy. Examples of the conductive material include, but are not limited to, aluminum (Al), nickel (Ni), gold (Au), silver (Ag), and copper-tin (Cu-Sn) alloy. The barrier layers 114 and 116 are configured to prevent interdiffusion between the plugs 115 and 117 and the dielectric layer 102, respectively. Examples of the barrier layers 114 and 116 include, but are not limited to, titanium / tungsten (Ti / W), titanium nitride (TiN), tantalum / tantalum nitride (Ta / TaN), cobalt / chromium (Co / Cr), cobalt silicide (CoSi x , such as CoSi, CoSi 2 and / or Co 2 Si). In some embodiments, the plug 117 is electrically connected to the S / D contact of the S / D feature of a transistor (not shown) in the 5 active region.

[0125] The vias 165 extend through the dielectric layer 103 and are respectively coupled to the conductive features 112 and 113. The vias 165 are configured to electrically connect the conductive features 112 and 113 in the dielectric layer 102 to other functional elements in or above the dielectric layer 103. The vias 165 may include a conductive portion and a barrier layer disposed on the sidewalls of the conductive portion. The formation of the vias 165 can be achieved by performing a patterning and etching process to form openings in the dielectric layer 103 that are vertically aligned with the conductive features 112 and 113. Next, using appropriate techniques such as sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), a barrier layer is deposited on the bottom and sidewalls of the openings. A conductive layer including a conductive material such as a metal is deposited into the openings and above the barrier layer, and a planarization process (e.g., a chemical-mechanical polishing (CMP) process) is performed to remove the excess conductive layer, establishing a smooth and substantially flat surface for subsequent processing steps.

[0126] During the etching process for forming the functional elements of the semiconductor structure 100A, the CESLs 104 and 105 are used as stop layers. Each of the CESLs 104 and 105 is configured to prevent the etching from going too deep and penetrating into the underlying layers of the device, and typically each of the CESLs 104 and 105 is designed to have an etching rate different from that of the underlying layer, such that the etching stops when it reaches the CESL. The CESL can include silicon nitride, silicon oxynitride, silicon nitride with oxygen (O) or carbon (C) elements, and / or other materials; and the CESL can be formed by CVD, PVD, ALD, or other suitable methods. In some embodiments, the CESLs 104 and 105 include different materials.

[0127] The resistor 131 is disposed above the workpiece 110. The resistor 131 can be in the form of a layer, a film, or a two-dimensional area in the horizontal direction (i.e., Figure 1A and Figure 1B the X-Y direction as shown). The resistor 131 includes a conductive material having a relatively high resistivity, such as a metal, a metal compound, or a metal alloy. In the illustrated example, the resistor 131 extends from a first end 163 (also referred to as the "first sidewall" 163) to a second end 164 (also referred to as the "second sidewall" 164) in a first horizontal direction (i.e., Figure 1C the X direction). The resistor 131 extends from a first side 181 to a second side 182 in a second horizontal direction (i.e., Figure 1B the Y direction). The resistor 131 is in the vertical direction (i.e.,Figure 1C extends from the top surface 161 to the bottom surface 162 in the Z direction. In some embodiments, the bottom surface 162 is substantially aligned with the top surface 159 of the CESL 104. In some embodiments, the resistor 131 is formed in the dielectric layer 103 that does not have a CESL, and the bottom surface 162 is substantially aligned with the bottom surface of the dielectric layer 103.

[0128] The resistor 131 has a length (L R , also referred to as the "first horizontal critical dimension" or "first horizontal CD") measured by the horizontal distance between the first end 163 and the second end 164 in the X direction. The resistor 131 has a width (W R , also referred to as the "second horizontal critical dimension" or "second horizontal CD") measured by the horizontal distance between the first side 181 and the second side 182 in the Y direction. The resistor 131 also has a thickness (T R ) measured by the vertical distance between the top surface 161 and the bottom surface 162. In some embodiments, the top surface 161 is aligned with or below the top surface of the CESL 105. In other words, the T R of the resistor 131 is equal to or less than the thickness of the CESL 105. Alternatively, the T R of the resistor 131 can be greater than the thickness of the CESL 105. L R , W R , and T R may vary. In some embodiments, the value of L R is about 3 nanometers to about 2000 nanometers. In some embodiments, the value of W R is about 3 nanometers to about 2000 nanometers. In some embodiments, the value of L R is at least about 1 nanometer.

[0129] Figure 1AOnly one resistor 131 is shown; however, depending on the application of the semiconductor structure 100A, multiple resistors 131 may be formed on the surface of the workpiece 110. In some embodiments, the resistor 131 may be formed close to the metal gate 111. The resistor 131 may include a conductive material, where the resistance of the conductive material is comparable to that of a polysilicon resistor, and the resistor 131 may be used to replace the polysilicon resistor used in radio frequency applications. In some embodiments, the resistor 131 has a sheet resistance of, for example, about 200 to 1,000 ohms per square (Ω / sq). Alternatively, the resistor 131 may include other sheet resistance values, depending on factors such as the material type, size, and / or thickness of the conductive material. In some embodiments, the resistor 131 is formed in a Front-End-Of-Line (FEOL) process. Alternatively, the resistor 131 may be formed in a Middle-End-Of-Line (MEOL) or Back-End-Of-Line (BEOL) process instead of in the FEOL process. In some embodiments, the resistor 131 includes at least one of Ti, Ta, Ni, Co, W, Mn, Cu, Ag, Si or any combination thereof. In some embodiments, the resistor 131 includes polysilicon.

[0130] In some embodiments, the resistor 131 is directly formed above or within the shallow trench isolation (STI) layer 107, where the STI layer 107 is disposed on or formed within the substrate 101. The STI layer 107 may be formed by etching shallow trenches in the substrate 101 and filling the shallow trenches with an insulating material such as an oxide. The STI layer 107 is typically used to isolate active semiconductor devices (such as transistors) from each other to prevent interference and current leakage between adjacent devices. According to the present disclosure, the resistor 131 may be directly formed above or within the STI layer 107 by deposition, ion implantation, or other processes. The STI layer 107 may also isolate the resistor 131 from other active or passive components from each other. In some embodiments, no CESL is formed between the resistor 131 and the STI layer 107. The resistor contact structure 140 is also formed in the same dielectric layer as the resistor 131 is formed. The resistor contact structure 140 may electrically connect the resistor 131 to another device of a functional element in another dielectric layer above the dielectric layer of the resistor 131.

[0131] In the illustrated example, the resistive contact structure 140 includes a resistive viacon contact 150 disposed above and in physical contact with the resistor 131. The resistive viacon contact 150 extends continuously from a first side 167 to a second side 168 along the X direction, and has a length (L VC ) that is the distance measured between the first side 167 and the second side 168. The resistive viacon contact 150 extends horizontally from a first side 183 to a second side 184 along the Y direction, and has a width (W VC ) that is the distance measured between the first side 183 and the second side 184 in the Y direction. The first side 167 is adjacent to the first end 163 of the resistor 131, and the second side 168 is adjacent to the second end 164 of the resistor 131. The resistive viacon contact 150 extends vertically from a top surface 171 to a bottom surface that is aligned with the bottom surface 162 of the resistor 131.

[0132] In some embodiments, each resistive viacon contact 150 of the resistive contact structure 140 includes at least three layers (e.g., a first layer 151, a second layer 152, and a third layer 153) and other components that are sequentially stacked in a vertical direction (i.e., Figure 1C the Z direction). The first layer 151 is disposed above the resistor 131, the second layer 152 is disposed on the first layer 151, and the third layer is disposed on the second layer 152. The first layer 151 and the second layer 152 share a first interface 166, and the second layer 152 and the third layer 153 share a second interface 169 above the first interface 166.

[0133] The first layer 151 may extend horizontally from the first side 167 to the second side 168, and the first layer 151 has the same length as L VC . In some embodiments, the L VC of the resistive viacon contact 150 is greater than the L R of the resistor 131. In some embodiments, the ratio of L VC to L R (L VC / L R) is at least 1.1, at least 1.2, at least 1.5, or at least 2. In some embodiments, the first layer 151 has a main portion 154 and two side portions (i.e., the first side portion 155 and the second side portion 156). The main portion 154 is located between the interface 166 and the top surface 161 of the resistor 131. The two side portions 155, 156 are respectively disposed at the first end 163 and the second end 164 of the resistor 131. The first side portion 155 vertically extends from the top surface 161 to the bottom surface 162 along the X direction and horizontally extends from the first side 167 to the first end 163. Similarly, the second side portion 156 vertically extends from the top surface 161 to the bottom surface 162 along the X direction and horizontally extends from the second side 168 to the second end 164. The side portions 155 and 156 may have a horizontal dimension (D), which is the distance measured between the first side 167 and the first end 163 or between the second side 168 and the second end 164. In some embodiments, D is from about 0 nanometers to about 1000 nanometers. The first layer 151 has a first thickness (T1) which is the distance measured between the interface 166 and the top surface 161 of the resistor 131. In some embodiments, T1 is from about 0.3 nanometers to about 100 nanometers.

[0134] Similar to the first layer, the second layer 152 horizontally extends from the first side 167 to the second side 168 and vertically extends from the top surface 171 to the first interface 166. The third layer 153 horizontally extends from the first end 172 to the second end 173 and vertically extends from the top surface 171 to the second interface 169. The second layer 152 includes a main portion 160 located between the second interface 169 and the first interface 166 and two side portions 157 and 158 respectively disposed on the first end 172 and the second end 173 of the third layer 153. In other words, the length of the third layer 153 along the X direction is less than L of the resistive via contact 150 VC , and the second layer 152 partially surrounds the third layer 153. In some embodiments, the side portions 157 and 158 of the second layer 152 have a horizontal dimension of from about 0 nanometers to about 30 nanometers (e.g., the distance measured from the first side 167 to the first end 172 or the distance measured from the second side 168 to the second end 173).

[0135] The second layer 152 has a second thickness (T2) measured as a vertical distance between the second interface 169 and the first interface 166. In some embodiments, T2 is significantly less than T1, and the value of T2 is about 0 nanometers (e.g., one or a few layers of atoms) to about 20 nanometers. The third layer 153 has a third thickness (T3) measured as a vertical distance between the top surface 171 and the second interface 169. In some embodiments, T3 is about 0 nanometers (e.g., one or a few layers of atoms) to about 50 nanometers. In some embodiments, the resistive through-hole contact 150 may have a total thickness (T3) of about 0.3 nanometers to about 170 nanometers. VC ), total thickness (T VC ) is measured by the sum of T1, T2, and T3 (i.e., T1+T2+T3). In some embodiments, the first layer 151 can constitute a majority of the resistive via contact 150. In some embodiments, the first layer 151 can constitute at least 50%, at least 60%, at least 70%, at least 80%, or at least 90% of the total volume of the resistive via contact 150.

[0136] In some embodiments, the first layer 151 includes a first material, the second layer 152 includes a second material, and the third layer 153 includes a third material. The first material, the second material, and the third material may be conductive materials of metals, metal compounds, or metal alloys. In some embodiments, the first material is different from the third material. In some embodiments, the first material and the second material have the same elemental composition (i.e., the same chemical element), but different crystal structures. In some embodiments, the first material has a first resistivity, the third material has a second resistivity, and the first resistivity is at least 3% less than the second resistivity. In some embodiments, the first resistivity is at least 5%, at least 10%, at least 15%, at least 20%, at least 25%, at least 30%, at least 40%, at least 50%, at least 75%, at least 90%, or at least 95% less than the second resistivity. In some embodiments, the first layer 151 has a first resistance value, the third layer 153 has a second resistance value, and the first resistance value is at least 3%, at least 5%, at least 10%, at least 15%, at least 20%, at least 25%, at least 30%, at least 40%, at least 50%, at least 75%, at least 90% or at least 95% less than the second resistance value.

[0137] In some embodiments, the first material includes at least one of W, Mn, Cu, Ag, Co, Ni, Ti, Ta or any combination thereof. In some embodiments, the third material includes at least one of W, Mn, Cu, Ag, Co, Ni, Ti, Ta or any combination thereof. In some embodiments, both the first layer 151 and the third layer 153 include metals. The metals have two different crystal structures from each other (i.e., the first crystal structure and the second crystal structure). For example, the first crystal structure is characterized by a body-centered cubic (BCC) lattice, and all three interaxial angles (i.e., α, β, γ) are 90 degrees. The second crystal structure is characterized by a face-centered cubic (FCC) lattice, and all three interaxial angles (i.e., α, β, γ) are 90 degrees. It should be noted that other crystal structures are also possible, such as a simple cubic (SC) lattice, a tetragonal lattice, an orthorhombic lattice, a rhombohedral lattice, a hexagonal lattice, a monoclinic lattice, and a triclinic lattice. In some embodiments, the first layer 151 has a first mass ratio of the first crystal structure to the second crystal structure, the third layer 153 has a second mass ratio of the first crystal structure to the second crystal structure, and the first mass ratio is different from the second mass ratio. In some embodiments, the first mass ratio is less than 1, and the second mass ratio is greater than 1. In some embodiments, the first mass ratio is less than 0.5. In some embodiments, the second mass ratio is greater than 2. In some embodiments, the total resistance of the resistive viacon contact 150 is significantly less than the resistance of the resistor 131. In some embodiments, the total resistance of the resistive viacon contact 150 is less than the resistance of the resistor 131 by at least 50%, at least 75%, at least 95%, or at least 99%.

[0138] In some embodiments, the third layer 153 can be used as a protective layer, and the third material of the third layer 153 can include an acid-resistant or etch-resistant metal. The acid-resistant or etch-resistant property of the third layer can enable protection of the resistive viacon contact from metal loss during subsequent BEOL acid / etch processes.

[0139] As described above, the second layer 152 can be used as an adhesive layer (also referred to as a "connection layer", "bonding layer", or "adhesive layer") to improve the bonding between the first layer 151 and the third layer 153. In some embodiments, the second material is different from the first material and / or the third material. In some embodiments, the second material includes both the first material and the third material, so the second layer 152 serves as a transition layer between the first layer 151 and the third layer 153. In some embodiments, the second material includes at least one of Ti, Ta, Ni, Co, W, Mn, Cu, Ag, Si or any combination thereof.

[0140] Differences in the metal and / or crystal structure between the first layer 151 and the third layer 153 may result in the heterogeneous nature of the resistive vias contact 150 and the resistive contact structure 140. Since the resistance of the first layer 151 is quite low and the first layer 151 constitutes most of the resistive vias contact 150, the total resistance of the resistive vias contact 150 can be significantly reduced compared to conventional resistive vias contacts made of materials with relatively high resistivity. Therefore, the heterogeneous resistive vias contacts according to the present disclosure can improve the resistance stability, durability, and functional performance, increase the overall yield of wafer acceptance testing (WAT), and improve the consistency of semiconductor manufacturing processes.

[0141] Figure 1D A top view showing the layout of another exemplary semiconductor structure 100B according to some embodiments. The semiconductor structure 100B is Figures 1A to 1C a close variant of the semiconductor structure 100A shown in and may include any one or more components of the above semiconductor structure 100A. In the exemplary illustration, the semiconductor structure 100B includes, among other components, a resistor 131 and a resistive contact structure 140 disposed above the resistor 131. The resistive contact structure 140 includes a plurality of resistive vias contacts 150 (i.e., resistive vias contacts 150-1, 150-2, and 150-3) arranged in columns along the Y direction and aligned. The resistive vias contacts 150 extend parallel in the X direction. The details of the resistive vias contacts 150 were described above with reference to Figures 1B to 1C and will not be repeated here. The total number of resistive vias contacts 150 can vary, for example, from 2 to 20.

[0142] Figure 2 A cross-sectional view showing another exemplary semiconductor structure 200 according to some embodiments. The semiconductor structure 200 is Figures 1A to 1D a variant of the semiconductor structures 100A and 100B shown and may include any one or more components of the above semiconductor structures 100A and 100B. Unless otherwise specified, the details of the components of the semiconductor structure 200 will not be repeated. In the exemplary illustration, the resistive vias contact 150 has a length (L R substantially the same as that of the resistor 131 (L VC)。In other words, the first side 167 and the second side 168 of the resistive viacon contact 150 are aligned with the first end 163 and the second end 164 of the resistor 131, respectively. The first layer 151 does not have side portions covering the first end 163 or the second end 164 of the resistor 131. Similar to the semiconductor structure 100B, the resistive contact structure 140 may include a plurality of resistive viacon contacts 150 arranged and aligned in columns along the Y direction.

[0143] Figure 3 A cross-sectional view of another exemplary semiconductor structure 300 is shown in accordance with some embodiments. The semiconductor structure 300 is Figure 2 a variant of the semiconductor structure 200 shown, and may include any one or more components of the semiconductor structure 200 described above. Details of the components of the semiconductor structure 300 will not be repeated herein unless otherwise specified. In the exemplary embodiment shown, the length (L VC ) of the resistive viacon contact 150 is less than the L R of the resistor 131. In some embodiments, the ratio of L VC to L R (L VC / L R ) is at least 0.5, at least 0.6, at least 0.7, at least 0.8, or at least 0.9. Similar to the semiconductor structure 200, the resistive contact structure 140 may include a plurality of resistive viacon contacts 150, where the resistive viacon contacts 150 are configured and aligned in columns along the Y direction. The distance between the first side 167 and the first end 163 or the distance between the second side 168 and the second end 164 (D) may be from about 0 nanometers to about 1000 nanometers.

[0144] Figures 4A - 4C An example of a semiconductor structure 400A is shown in accordance with some embodiments of the present disclosure, where the semiconductor structure 400A includes a resistive contact structure 440 (also referred to as a "contact structure", "contact assembly", or the like) disposed on the resistor 131. Figure 4A A cross-sectional view of the semiconductor structure 400A is shown. Figure 4B A top view showing the layout of the region 430 of the semiconductor structure 400A and the position of the resistive contact structure 440 relative to the resistor 131 is shown. Figure 4C A cross-sectional view of the region 430 of the semiconductor structure 400A along Figure 4B the line A - A' is shown. The semiconductor structure 400A is Figures 1A to 1C a close variant of the semiconductor structure 100A shown in, and may include any one or more components thereof. Details of the components of the semiconductor structure 400A will not be repeated herein unless otherwise specified.

[0145] In the illustrated example, the resistive contact structure 440 includes a plurality of resistive vias 450 (e.g., resistive vias 450a, 450b, and 450c), and the plurality of resistive vias 450 are configured in a row and aligned in the X direction. Generally, each resistive via 450 is similar to Figures 1A to 1C resistive via 150, and has a relatively small length (L VC ). Specifically, each resistive via 450 (i.e., 450a, 450b, and 450c) extends in the X direction from a first side 467 (i.e., 467a, 467b, and 467c) to a second side 468 (i.e., 468a, 468b, and 468c). Each resistive via 450 (i.e., 450a, 450b, and 450c) includes a first layer 451 (i.e., 451a, 451b, and 451c), a second layer 452 (i.e., 452a, 452b, and 452c), and a third layer 453 (i.e., 453a, 453b, and 453c). The first layers 451a and 451c respectively cover a portion of the first end 163 and a portion of the second end 164 of the resistor 131. The first layer 451a of the resistive via 450a has a bottom portion 455 disposed on the first end 163 of the resistor 131, and the first layer 451c of the resistive via 450c has a bottom portion 456 disposed on the second end 164 of the resistor 131. In some embodiments, the L VC of each resistive via 450 is about 3 nanometers to about 600 nanometers, about 3 nanometers to about 400 nanometers, about 3 nanometers to about 200 nanometers, about 3 nanometers to about 100 nanometers, about 3 nanometers to about 50 nanometers, or about 3 nanometers to about 20 nanometers. In some embodiments, the total length (L CS ) of the resistive contact structure 440 is about 3 nanometers to about 2000 nanometers, and the total length (L CS ) is the distance measured from the first side 467a of the resistive via 450a to the second side 468c of the resistive via 450c. In some embodiments, the ratio of L VC to L CS (L VC / L CS ) is 0.3 or less, 0.2 or less, 0.1 or less, 0.05 or less. The number of resistive vias 450 included in the resistive contact structure 440 can vary from 2 to 100.

[0146] Figure 4D A top view showing the layout of a semiconductor structure 400B according to another example is shown according to some embodiments. The semiconductor structure 400B is Figures 4A to 4CA similar variant of the semiconductor structure 400A shown in the figure, and may include any one or more components of the semiconductor structure 400A described above. In the example shown, the semiconductor structure 400B includes, among other components, a resistor 131 and a resistor contact structure 440 disposed above the resistor 131. The resistor contact structure 440 includes an array of resistor viacon contacts 450 configured in columns and rows in the X-Y plane. The array of resistor viacon contacts 450 may form a regular or irregular pattern. The details of the resistor viacon contacts 150 were described above with reference to Figures 1B to 1C and will not be repeated here. The number of resistor viacon contacts 150 may vary, for example, from 2 to 100.

[0147] Figure 5 A cross-sectional view of another exemplary semiconductor structure 500 is shown according to some embodiments. The semiconductor structure 500 is Figures 4A to 4D a variant of the semiconductor structures 400A and 400B shown in the figure, and may include any one or more components of the semiconductor structures 400A and 400B described above. Unless otherwise specified, the details of the components of the semiconductor structure 500 will not be repeated. In the example shown, the total length (L CS ) of the resistor contact structure 440 is substantially the same as the L R of the resistor 131. In other words, the first side 467a of the resistor viacon contact 450a and the second side 468c of the resistor viacon contact 450c are aligned with the first end 163 and the second end 164 of the resistor 131, respectively. Neither the first layer 151a nor the first layer 151c has a side portion covering the first end 163 or the second end 164 of the resistor 131.

[0148] Figure 6 A cross-sectional view of another exemplary semiconductor structure 300 is shown according to some embodiments. The semiconductor structure 600 is Figure 5 a variant of the semiconductor structure 500 shown in the figure, and may include any one or more components of the semiconductor structure 500 described above. Unless otherwise specified, the details of the components of the semiconductor structure 600 will not be repeated. In the example shown, the length (L CS ) of the resistor contact structure 440 is less than the L R of the resistor 131. In some embodiments, the ratio of L CS to L R (L CS / L R ) is at least 0.5, at least 0.6, at least 0.7, at least 0.8, or at least 0.9.

[0149] Figures 7A to 7B Additional examples of semiconductor structures 700A and 700B are shown, respectively. Figure 7AA top view showing the layout of an exemplary semiconductor structure 700A, which is a close variant of the semiconductor structure 100A. In the exemplary illustration, the semiconductor structure 700A includes a resistor 131 and a resistor contact structure 140 disposed on the resistor 131. The resistor contact structure 140 includes a plurality of resistor vias contacts 150 (e.g., resistor vias contacts 150-1, 150-2, and 150-3) arranged in rows parallel to the X direction. Each resistor via contact 150 continuously extends from a first side 181 of the resistor 131 to a second side 182 in the Y direction. The length (L VC ) of each resistor via contact 150 is substantially less than the L R of the resistor 131, and the width (W VC ) of each resistor via contact 150 is substantially the same as the W R of the resistor 131. The total number of resistor via contacts 150 included in the resistor contact structure 140 can vary from 2 to 100.

[0150] Figure 7B is a top view showing the layout of an exemplary semiconductor structure 700B, which is a close variant of the semiconductor structure 400A. In the exemplary illustration, the semiconductor structure 700B includes a resistor 131 and a resistor contact structure 440 disposed on the resistor 131. The resistor contact structure 440 includes a plurality of resistor vias contacts 450 (e.g., resistor vias contacts 450a, 450b, and 450c) arranged in columns parallel to the Y direction. The length (L VC ) of each resistor via contact 450 is significantly less than the L R , and the width (W VC ) of each resistor via contact 450 is significantly less than the W R . The total number of resistor via contacts 450 included in the resistor contact structure 440 can vary from 2 to 100.

[0151] Figure 8 A flowchart showing a method 800 for forming a semiconductor structure having a resistor contact structure according to some embodiments is presented. In Figure 8 the exemplary illustration, the method 800 includes steps 802, 804, 806, 808, and 810. Additional operations may be performed.

[0152] In step 802, an opening is formed. The opening may be formed in a resistor (e.g., Figure 1Aabove resistor 131) to expose the top surface of the resistor. In some embodiments, a plurality of openings (e.g., a row or column or array or pattern of a plurality of openings) are formed above the resistor. The openings can be formed using patterning and etching processes.

[0153] In step 804, a first layer is formed in the openings. The first layer (e.g., Figure 1A first layer 151) is formed in the openings using a suitable deposition technique (e.g., CVD, PVD, and ALD). In some embodiments, the first layer (e.g., Figure 4A first layer 451) is formed in each of the plurality of openings. In some embodiments, the first layer can be formed during the same deposition process as other conductive features (e.g., Figure 1A and Figure 4A conductive feature 112).

[0154] In step 806, a second layer is formed on the first layer. The second layer (e.g., Figure 1A second layer 152) can be formed on the first layer in the openings using a suitable deposition technique. In some embodiments, the second layer (e.g., Figure 4A second layer 452) is formed on the first layer in each of the plurality of openings.

[0155] In step 808, a third layer is formed on the second layer. The third layer (e.g., Figure 1A third layer 153) can be formed on the second layer in the openings using a suitable deposition technique. In some embodiments, the third layer (e.g., Figure 4A third layer 453) is formed on the second layer in each of the plurality of openings.

[0156] In step 810, a planarization process (e.g., CMP process) is performed to remove excess material of the third layer and produce a smooth and substantially flat surface of the third layer. Thereby, a resistor contact structure (e.g., Figure 1A resistor contact structure 140 or Figure 4A resistor contact structure 440) is formed.

[0157] It should be noted that the via contacts and contact structures according to the examples of the present disclosure are not only intended to provide connectivity for resistors. The via contacts and contact structures can generally be used as improved conductive interconnect features for other types of active and passive components.

[0158] According to some aspects of the present disclosure, a semiconductor structure is provided. In one example, the semiconductor structure includes a substrate, a dielectric layer disposed over the substrate, a resistor disposed in the dielectric layer and extending from a first sidewall to a second sidewall in a first horizontal direction, and a resistor viacon contact disposed in the dielectric layer of the resistor. The resistor viacon contact further includes a first layer disposed on and in contact with the resistor, a second layer disposed on and in contact with the first layer, and a third layer disposed on and in contact with the second layer. The first layer has a first thickness and includes a first material having a first resistivity, the second layer has a second thickness and includes a second material, and the third layer has a third thickness and includes a third material having a second resistivity. The first thickness is greater than the third thickness, and the first resistivity is less than the second resistivity.

[0159] In some embodiments, the resistor viacon contact has a length (L VC ) measured by the distance between a first side and a second side, and the length (L VC ) of the resistor viacon contact is from 3 nanometers to 2000 nanometers. In some embodiments, the resistor has a length (L R ) of the distance measured between a first sidewall and a second sidewall, and the length (L R ) of the resistor is less than the length (L VC ) of the resistor viacon contact. In some embodiments, the first layer of the resistor viacon contact further includes a main portion disposed on the top surface of the resistor, and side portions disposed on the first sidewall and the second sidewall, respectively. In some embodiments, the resistor has a thickness (T R ) of at least 1 nanometer. In some embodiments, the first thickness is from 0.3 nanometers to 100 nanometers, the second thickness is from 0 nanometers to 20 nanometers, and the third thickness is from 0 nanometers to 50 nanometers. In some embodiments, the first material and the third material each independently include at least one of or a combination of W, Mn, Cu, Ag, Co, Ni, Ti, Ta, and the second material includes at least one of or any combination of Ti, Ta, Ni, Co, W, Mn, Cu, Ag, Si. In some embodiments, the first material and the third material both include metals, the first material has a first crystal structure of the metal, the third material has a second crystal structure of the metal, and the first crystal structure is different from the second crystal structure. In some embodiments, the first material and the third material both include metals, the metal has a first crystal structure and a second crystal structure, the first material has a first mass ratio of the first crystal structure and the second crystal structure, the third material has a second mass ratio of the first crystal structure and the second crystal structure, the first mass ratio is greater than 1, and the second mass ratio is less than 1. In some embodiments, the first resistivity is at least 10% less than the second resistivity.

[0160] In another example, a semiconductor structure includes a substrate, a dielectric layer disposed over the substrate, a resistor disposed in the dielectric layer and extending from a first sidewall to a second sidewall in a first horizontal direction, and a resistor contact structure disposed on the resistor. The resistor contact structure further includes a plurality of resistor vias contacts disposed in the dielectric layer and spaced apart from each other, wherein each resistor via contact extends from a first side to a second side in the first horizontal direction, and further includes a first layer disposed on the resistor and in contact with the resistor, a second layer disposed on the first layer and in contact with the first layer, and a third layer disposed on the second layer and in contact with the second layer. The first layer has a first thickness and includes a first material having a first resistivity, the second layer has a second thickness and includes a second material, and the third layer has a third thickness and includes a third material having a second resistivity. The first thickness is greater than the third thickness, and the first resistivity is less than the second resistivity.

[0161] In some embodiments, the resistor via contacts are configured in a row and aligned in the first horizontal direction. In some embodiments, the resistor via contacts are configured in a column and aligned in a second horizontal direction that is substantially perpendicular to the first horizontal direction. In some embodiments, the resistor via contacts are configured in multiple rows and multiple columns in a horizontal plane. In some embodiments, the total number of resistor via contacts is at least 9. In some embodiments, the second material is a mixture of the first material and the third material. In some embodiments, each resistor via contact has a total thickness of from 0.3 nanometers to 170 nanometers, where the total thickness is measured as the sum of the first thickness, the second thickness, and the third thickness.

[0162] In a further example, a semiconductor structure includes a substrate, a dielectric layer disposed over the substrate, a resistor disposed in the dielectric layer and extending from a first sidewall to a second sidewall along a first horizontal direction, and a resistor contact structure disposed in the dielectric layer. The resistor contact structure further includes a plurality of resistor via contacts, wherein the resistor via contacts are configured substantially in a second horizontal direction that is perpendicular to the first horizontal direction and aligned in a column. Each resistor via contact continuously extends from a first side to a second side in the first horizontal direction, and further includes a first layer disposed on the resistor and in contact with the resistor, a second layer disposed on the first layer and in contact with the first layer, and a third layer disposed on the second layer and in contact with the second layer. The first layer has a first thickness and includes a first material having a first resistivity, the second layer has a second thickness and includes a second material, and the third layer has a third thickness and includes a third material having a second resistivity. The first thickness is greater than the third thickness, the third thickness is greater than the second thickness, and the first resistivity is less than the second resistivity by at least 10%.

[0163] In some embodiments, the total number of resistor vias is at least 3. In some embodiments, the resistor has a length (L R ) measured by the distance between the first sidewall and the second sidewall, the resistor via has a length (L VC ) measured by the distance between the first side and the second side, and the length (L R ) of the resistor is greater than the length (L VC ) of the resistor via.

[0164] One aspect of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a substrate, a dielectric layer, a resistor, and resistor via contacts. The dielectric layer is disposed over the substrate. The resistor is disposed within the dielectric layer, and the resistor extends from a first sidewall to a second sidewall along a first horizontal direction. The resistor via contacts are disposed within the dielectric layer, wherein the resistor via contacts extend continuously from a first side to a second side along the first horizontal direction. The resistor via contacts further include a first layer, a second layer, and a third layer. The first layer is disposed on and in contact with the resistor, wherein the first layer has a first thickness and a first resistivity. The second layer is disposed on and in contact with the first layer, wherein the second layer has a second thickness. The third layer is disposed on and in contact with the second layer, wherein the third layer has a third thickness and a second resistivity. Wherein the first thickness is greater than the third thickness, and the first resistivity is less than the second resistivity.

[0165] One aspect of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a substrate, a dielectric layer, a resistor, and a resistor contact structure. The dielectric layer is disposed over the substrate. The resistor is disposed within the dielectric layer, and the resistor extends from a first sidewall to a second sidewall along a first horizontal direction. The resistor contact structure includes a plurality of resistor via contacts disposed in the dielectric layer, wherein each resistor via contact extends continuously from a first side to a second side along the first horizontal direction. Each resistor via contact further includes a first layer, a second layer, and a third layer. The first layer, disposed on and in contact with the resistor, wherein the first layer has a first thickness and a first resistivity. The second layer is disposed on and in contact with the first layer, wherein the second layer has a second thickness. The third layer is disposed on and in contact with the second layer, wherein the third layer has a third thickness and a second resistivity. Wherein the first thickness is greater than the third thickness, and the first resistivity is less than the second resistivity.

[0166] One aspect of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a substrate, a dielectric layer, a resistor, and a resistor contact structure. The dielectric layer is disposed over the substrate. The resistor is disposed within the dielectric layer and extends from a first sidewall to a second sidewall along a first horizontal direction. The resistor contact structure includes a plurality of resistor vias contacts arranged in columns along a second horizontal direction substantially perpendicular to the first horizontal direction, and each resistor via contact continuously extends from a first side to a second side along the first horizontal direction. Each resistor via contact further includes a first layer, a second layer, and a third layer. The first layer is disposed on and in contact with the resistor, wherein the first layer has a first thickness and a first resistivity. The second layer is disposed on and in contact with the first layer, wherein the second layer has a second thickness. The third layer is disposed on and in contact with the second layer, wherein the third layer has a third thickness and a second resistivity. Wherein the first thickness is greater than the third thickness, the third thickness is greater than the second thickness, and the first resistivity is at least 10% less than the second resistivity.

[0167] The features of several embodiments are outlined above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that the present disclosure can be readily used as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made herein by those skilled in the art.

Claims

1. A semiconductor structure, characterized in that: include: a substrate; a dielectric layer disposed above the substrate; a resistor disposed in the dielectric layer, the resistor extending from a first side wall to a second side wall along a first horizontal direction; and a resistive via contact disposed in the dielectric layer, wherein the resistive via contact extends continuously from a first side to a second side along the first horizontal direction, and the resistive via contact further comprises: a first layer disposed on the resistor and in contact with the resistor, wherein the first layer has a first thickness and a first resistivity; a second layer disposed on and in contact with the first layer, wherein the second layer has a second thickness; and a third layer disposed on and in contact with the second layer, wherein the third layer has a third thickness and a second resistivity, The first thickness is greater than the third thickness, and the first resistivity is less than the second resistivity.

2. The semiconductor structure according to claim 1, wherein: The resistive via contact has a length measured from the first side to the second side, and the length of the resistive via contact is 3 nanometers to 2000 nanometers.

3. The semiconductor structure according to claim 2, wherein: The resistor has a length measured from the first sidewall to the second sidewall, and the length of the resistor is less than the length of the resistive via contact.

4. The semiconductor structure according to claim 2, wherein: The first layer of the resistive via contact further includes a main portion disposed on a top surface of the resistor, and two side portions disposed on the first side wall and the second side wall, respectively.

5. The semiconductor structure according to claim 1, wherein: The resistor has a thickness of at least 1 nanometer.

6. The semiconductor structure according to claim 1, wherein: The first thickness is 0.3 nanometers to 100 nanometers, the second thickness is 0 nanometers to 20 nanometers, and the third thickness is 0 nanometers to 50 nanometers.

7. A semiconductor structure, characterized in that: include: a substrate; a dielectric layer disposed above the substrate; a resistor disposed in the dielectric layer, the resistor extending from a first side wall to a second side wall along a first horizontal direction; and A resistive contact structure includes a plurality of resistive through-hole contacts disposed in the dielectric layer, wherein each of the resistive through-hole contacts extends continuously from a first side to a second side along the first horizontal direction, and each of the resistive through-hole contacts further includes: a first layer disposed on the resistor and in contact with the resistor, wherein the first layer has a first thickness and a first resistivity; a second layer disposed on and in contact with the first layer, wherein the second layer has a second thickness; and a third layer disposed on and in contact with the second layer, wherein the third layer has a third thickness and a second resistivity, The first thickness is greater than the third thickness, and the first resistivity is less than the second resistivity.

8. The semiconductor structure according to claim 7, wherein: Each of the resistive via contacts has a total thickness of 0.3 nm to 170 nm, wherein the total thickness is measured as the sum of the first thickness, the second thickness, and the third thickness.

9. A semiconductor structure, characterized in that: include: a substrate; a dielectric layer disposed above the substrate; a resistor disposed in the dielectric layer, the resistor extending from a first side wall to a second side wall along a first horizontal direction; and A resistive contact structure, wherein the resistive contact structure comprises a plurality of resistive through-hole contacts, the plurality of resistive through-hole contacts are arranged in a row along a second horizontal direction substantially perpendicular to the first horizontal direction, each of the resistive through-hole contacts continuously extends from a first side to a second side along the first horizontal direction, and each of the resistive through-hole contacts further comprises: a first layer disposed on the resistor and in contact with the resistor, wherein the first layer has a first thickness and a first resistivity; a second layer disposed on and in contact with the first layer, wherein the second layer has a second thickness; and a third layer disposed on and in contact with the second layer, wherein the third layer has a third thickness and a second resistivity, wherein the first thickness is greater than the third thickness, the third thickness is greater than the second thickness, and The first resistivity is at least 10% less than the second resistivity.

10. The semiconductor structure according to claim 9, wherein: The total number of the plurality of resistive through-hole contacts is at least three.

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