Chip packaging structure, circuit board and electronic equipment

Abstract

The utility model provides a chip packaging structure, a circuit board and electronic equipment, and relates to the technical field of semiconductor manufacturing, the chip packaging structure comprises a plurality of rewiring layers, a plastic packaging layer, a bridging chip and at least two active chips, the plurality of rewiring layers are provided with hollow areas for accommodating the bridging chip, and the bridging chip is located in the hollow areas; the bridging chip comprises a first surface and a second surface which are oppositely arranged, and the first surface is provided with bridging pins; the at least two active chips are located on one side of the rewiring layer, and the bridging chip is electrically connected with the at least two active chips through bridging pins; the plastic package layer and the active chips are located on the same side of the rewiring layer, and the plastic package layer is filled between the active chips, so that accurate positioning of the bridging chip can be realized, and the bridging chip is prevented from deviating; in addition, the signal transmission efficiency can be improved, the packaging space can be saved, the packaging thickness can be reduced, and the high-density packaging requirement can be met.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly, to a chip packaging structure, a circuit board, and an electronic device. Background Art

[0002] With the continuous development of semiconductor technology, miniaturization in size and high integration in structure and function have become the development trends of semiconductor components.

[0003] In a chip packaging structure integrating multiple active chips, the signal transmission lines between multiple active chips are very dense. If only the redistribution layer (RDL) is used to achieve signal transmission and interconnection, the demand for dense signal transmission cannot be met. Therefore, it is necessary to introduce a bridging chip and utilize its internal high-density interconnection structure to make up for the defect of the redistribution layer in signal transmission.

[0004] However, introducing a bridging chip to achieve the interconnection of active chips is relatively complex in the manufacturing process and may cause an increase in the thickness of the chip packaging structure. Summary of the Utility Model

[0005] In order to at least overcome the above deficiencies in the prior art, the purpose of this application is to provide a chip packaging structure, a circuit board, and an electronic device.

[0006] In a first aspect, an embodiment of this application provides a chip packaging structure, which includes:

[0007] Multiple redistribution layers, where the multiple redistribution layers are provided with hollow areas for accommodating a bridging chip, and the bridging chip is located within the hollow areas;

[0008] The bridging chip includes a first surface and a second surface that are oppositely arranged, and the first surface is provided with bridging pins;

[0009] At least two active chips, where at least two active chips are located on one side of the redistribution layer, and the bridging chip is electrically connected to at least two active chips through the bridging pins;

[0010] A plastic encapsulation layer, which is on the same side of the redistribution layer as the active chips, and the plastic encapsulation layer fills the space between the active chips.

[0011] In a possible implementation, the bridging chip is provided with a plurality of through holes penetrating the first surface and the second surface, and the first surface and the second surface are electrically connected through the conductive material filled in the through holes.

[0012] In a possible implementation, the thicknesses of the plurality of the redistribution layers are equal to the thickness of the bridging chip.

[0013] In a possible implementation, the chip package structure further includes a plurality of external pins, and the plurality of external pins are disposed on a side of the redistribution layer away from the encapsulation layer.

[0014] In a possible implementation, the chip package structure further includes a filling layer, and the filling layer is disposed between the active chip and the bridging chip.

[0015] In a possible implementation, a plurality of connection pins are disposed on a side of the active chip close to the redistribution layer, and the bridging chip is electrically connected to at least two of the active chips through the bridging pins and the connection pins.

[0016] In a possible implementation, the material of the encapsulation layer includes epoxy molding compound.

[0017] In a possible implementation, the chip package structure includes a plurality of the bridging chips, and the plurality of bridging chips are respectively electrically connected to at least two of the active chips.

[0018] In a second aspect, an embodiment of the present application further provides a circuit board, and the circuit board includes the chip package structure described in any of the above aspects.

[0019] In a third aspect, an embodiment of the present application further provides an electronic device, and the electronic device includes the chip package structure described in any of the above aspects.

[0020] Based on any of the above aspects, for the chip package structure, circuit board, and electronic device provided by the embodiments of the present application, by providing a hollowed-out area in the redistribution layer and placing the bridging chip in the hollowed-out area, accurate positioning of the bridging chip can be achieved, and the offset of the bridging chip can be avoided; in addition, by placing the bridging chip in the hollowed-out area of the redistribution layer and realizing the interconnection of at least two active chips through the bridging chip, the signal transmission efficiency can be improved, the package space can be saved, the package thickness can be reduced, and the high-seal package requirements can be met. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be referred to in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0022] Figure 1One of the schematic diagrams of the chip packaging structure in the prior art;

[0023] Figure 2 Another schematic diagram of the chip packaging structure in the prior art;

[0024] Figure 3 One of the schematic diagrams of the chip packaging structure provided by this embodiment;

[0025] Figure 4 Another schematic diagram of the chip packaging structure provided by this embodiment;

[0026] Figure 5 Another schematic diagram of the chip packaging structure provided by this embodiment;

[0027] Figure 6 Another schematic diagram of the chip packaging structure provided by this embodiment;

[0028] Figure 7 Another schematic diagram of the chip packaging structure provided by this embodiment;

[0029] Figure 8 Another schematic diagram of the chip packaging structure provided by this embodiment;

[0030] Figure 9 Another schematic diagram of the chip packaging structure provided by this embodiment;

[0031] Icon: 100 - Redistribution layer; 200 - Plastic encapsulation layer; 300 - Bridging chip; 310 - Bridging pin; 320 - Through hole; 400 - Active chip; 410 - Connection pin; 500 - External pin; 600 - Filling layer. Detailed implementation manners

[0032] To make the objectives, technical solutions and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are some but not all of the embodiments of this application. Usually, the components of the embodiments of this application described and illustrated herein can be arranged and designed in various different configurations.

[0033] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of this application which is claimed, but merely represents selected embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of this application without creative efforts fall within the scope of protection of this application.

[0034] It should be noted that similar reference numerals and letters indicate similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0035] In the description of the present application, it should be noted that the orientation or positional relationship indicated by terms such as "upper", "lower", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of this application is usually placed during use. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation of the present application. In addition, terms such as "first", "second", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0036] In addition, terms such as "horizontal", "vertical", "hanging", etc. do not mean that the components are required to be absolutely horizontal or hanging, but can be slightly inclined. For example, "horizontal" only means that its direction is more horizontal relative to "vertical", and does not mean that the structure must be completely horizontal, but can be slightly inclined.

[0037] In the description of the present application, it should also be noted that unless otherwise clearly specified and limited, the terms "set", "installed", "connected", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0038] It should be noted that, without conflict, the different features in the embodiments of the present application can be combined with each other.

[0039] After research by the inventor, it is found that currently, please refer to Figure 1 , when introducing a bridge chip 300' to realize the interconnection of the active chip 400', a groove can be set on the substrate, and the bridge chip 300' is placed in the groove, and the interconnection of the active chip 400' is realized through the bridge chip 300'. However, this method cannot achieve high-density interconnection, and the thickness of the chip packaging structure is relatively large.

[0040] In addition, please refer to Figure 2When the bridge chip 300' is introduced to realize the interconnection of the active chip 400', the bridge chip 300' can also be placed in the plastic packaging layer 200', and the active chip 400' can be interconnected through the bridge chip 300'. The plastic packaging layer 200' is also provided with a plurality of conductive columns penetrating the plastic packaging layer 200'. However, this method may cause the bridge chip 300' to deviate, thereby causing a short circuit, and the thickness of the chip packaging structure is relatively large.

[0041] This embodiment provides a solution that can solve the above-mentioned problem. The specific implementation methods of this application are described in detail below in conjunction with the accompanying drawings.

[0042] Please refer to Figure 3 , Figure 3 A possible schematic diagram of the chip packaging structure provided by this embodiment is shown as an example. The chip packaging structure may include a redistribution layer 100 (RDL), a plastic layer 200, a bridge chip 300, and at least two active chips 400.

[0043] The number of the redistribution layers 100 may be multiple, and the multiple redistribution layers 100 are stacked in sequence and are electrically connected to each other. The multiple redistribution layers 100 are provided with a hollow area for accommodating the bridge chip 300. The bridge chip 300 may be located in the hollow area, and the size of the hollow area matches the size of the bridge chip 300. The hollow area may be formed by a dry film exposure process.

[0044] It should be noted that the number of the redistribution layers 100 can be adjusted according to actual needs.

[0045] The bridge chip 300 may include a first surface and a second surface that are opposite to each other. The first surface may be provided with a plurality of bridge pins 310 , and the second surface may be a ground layer.

[0046] In this embodiment, the bridge chip 300 may include passive components, such as resistors, capacitors, inductors or other similar components. In addition, the bridge chip 300 may also include active components.

[0047] The active chip 400 may be located on a side of the redistribution layer 100 close to the first surface of the bridge chip 300 , and the bridge chip 300 may be electrically connected to at least two of the active chips 400 through the bridge pins 310 .

[0048] In this embodiment, the bridging chip 300 can be electrically connected to two adjacent active chips 400 through the bridging pins 310, and the bridging chip 300 can also be electrically connected to multiple adjacent active chips 400 through the bridging pins 310.

[0049] Among them, the active chip 400 can refer to a chip including active components, and the active components can include transistors, diodes, integrated circuits, optoelectronic components or other suitable components with gain, which are not specifically limited herein. For example, the active chip 400 can be a High Bandwidth Memory (HBM) chip, or an Application Specific Integrated Circuit (ASIC) chip, a system on chip (SoC), etc.

[0050] Specifically, the orthographic projections of at least two active chips 400 on the redistribution layer 100 do not overlap. The at least two active chips 400 can be at least two active chips 400 with the same structure, or at least two active chips 400 with different structures to achieve different functions. For example, when the chip package structure includes two active chips 400, the two active chips 400 can be a system on chip and a high bandwidth memory chip respectively, but not limited thereto.

[0051] The molding layer 200 and the active chip 400 can be located on the same side of the redistribution layer 100, and the molding layer 200 can be filled between the active chips 400. Specifically, the molding layer 200 can be formed by wafer-level or board-level encapsulation, laminating an encapsulation film, thermocompression encapsulation or injection molding encapsulation, which is not specifically limited herein.

[0052] In the above structure, by setting the hollowed-out area in the redistribution layer 100 and placing the bridging chip 300 in the hollowed-out area, accurate positioning of the bridging chip 300 can be achieved, avoiding the offset of the bridging chip 300; in addition, by placing the bridging chip 300 in the hollowed-out area of the redistribution layer 100 and interconnecting at least two active chips 400 through the bridging chip 300, the signal transmission efficiency can be improved, the packaging space can be saved, the packaging thickness can be reduced, and the high-seal packaging requirements can be met.

[0053] In a possible implementation manner, please refer to Figure 4 , the bridging chip 300 can be provided with a plurality of through holes 320 penetrating the first surface and the second surface, and the first surface and the second surface can be electrically connected through the conductive material filled in the through holes 320.

[0054] Specifically, the bridging chip 300 may be provided with a plurality of through holes 320 arranged at intervals. The through holes 320 may be formed by an etching process or an electroplating process. The plurality of through holes 320 penetrate through the bridging chip 300, and the plurality of through holes 320 are filled with a conductive material. The first surface and the second surface of the bridging chip 300 can be electrically connected through the conductive material filled in the through holes 320.

[0055] Exemplarily, the conductive material filled in the through holes 320 may include conductive materials such as copper, aluminum, nickel, or alloys of at least two of the above or combinations of the above, and no specific limitation is made here.

[0056] In a possible implementation, the thicknesses of the plurality of redistribution layers 100 may be equal to the thickness of the bridging chip 300.

[0057] In this embodiment, the plurality of redistribution layers 100 may be stacked, and the thickness of the bridging chip 300 may be approximately equal to the thicknesses of the plurality of redistribution layers 100. In this way, the package thickness can be minimized and the package space can be saved.

[0058] In a possible implementation, please refer to Figure 5 ..., the chip package structure may further include a plurality of external pins 500, and the plurality of external pins 500 may be disposed on a side of the redistribution layer 100 away from the molding compound layer 200.

[0059] In this embodiment, the plurality of external pins 500 may be connected to other components, which helps the chip package structure to further achieve electrical connection with other components.

[0060] In some examples, the external pins 500 may be solder balls, ball grid array (BGA) balls, controlled collapse chip connection (C4) bumps, or micro-bumps.

[0061] It should be noted that, please refer to Figure 6 ..., when the bridging chip 300 is provided with a plurality of through holes 320 penetrating through the first surface and the second surface, some of the external pins 500 may also be electrically connected to the conductive material filling the through holes 320.

[0062] In a possible implementation, please refer to Figure 7, the chip packaging structure may further include a filling layer 600, the filling layer 600 and the plastic encapsulation layer 200 are on the same side of the redistribution layer 100, and the filling layer 600 may be disposed between the active chip 400 and the bridging chip 300.

[0063] In this embodiment, the filling layer 600 can be used to fill the gap between the active chip 400 and the bridging chip 300, can increase the bonding strength between the active chip 400 and the bridging chip 300, can protect the active chip 400 and the bridging chip 300, and improve the reliability of the chip packaging structure.

[0064] In a possible implementation manner, please refer to again Figure 3 , a plurality of connection pins 410 are disposed on a side of the active chip 400 close to the redistribution layer 100, and the bridging chip 300 can be electrically connected to at least two active chips 400 through the bridging pins 310 and the connection pins 410.

[0065] In this embodiment, the bridging pins 310 of one bridging chip 300 can be connected to the connection pins 410 of at least two active chips 400, so as to realize the interconnection of at least two active chips 400.

[0066] Specifically, the pitch between two adjacent connection pins 410 of the active chip 400 may be equal to the pitch between two adjacent bridging pins 310 of the bridging chip 300. A part of the connection pins 410 of the active chip 400 can be electrically connected to the bridging chip 300, and another part of the connection pins 410 of the active chip 400 can be electrically connected to the redistribution layer 100. The bridging chip 300 can be electrically connected to a plurality of active chips 400 through a plurality of bridging pins 310 for realizing the interconnection of a plurality of active chips 400. For example, if the bridging chip 300 is connected to two active chips 400, a part of the bridging pins 310 of the bridging chip 300 can be electrically connected to one active chip 400, and another part of the bridging pins 310 of the bridging chip 300 can be electrically connected to another active chip 400.

[0067] In a possible implementation manner, the material of the plastic encapsulation layer 200 can be an insulating material. For example, epoxy molding compound (EMC).

[0068] In this embodiment, epoxy molding compound (EMC) may be coated around the active chip 400 to form the plastic encapsulation layer 200 . The plastic encapsulation layer 200 and the active chip 400 are located on the same side of the redistribution layer 100 .

[0069] Among them, epoxy molding compound (EMC) is a powder molding compound made of epoxy resin as a base resin, high-performance phenolic resin as a curing agent, silicon micropowder and the like as fillers, and a variety of additives. Epoxy molding compound (EMC) is easy to shape and has a hard texture. It can protect the active chip 400 and the redistribution layer 100, effectively prevent external water and oxygen from contacting the active chip 400 and the redistribution layer 100, and can avoid the failure of the packaged chip caused by rigid collision, thereby improving the strength of the chip packaging structure.

[0070] In one possible implementation, see Figure 8 The chip packaging structure may include a plurality of the bridge chips 300 , and the plurality of the bridge chips 300 may be respectively located in the plurality of the hollow regions of the redistribution layer 100 , and the plurality of the bridge chips 300 may be respectively electrically connected to at least two of the active chips 400 to realize the interconnection of the active chips 400 .

[0071] Please note that, please refer to Figure 9 , the plurality of bridge chips 300 may each be provided with a plurality of through holes 320 penetrating the first surface and the second surface.

[0072] Based on the same concept, an embodiment of the present application further provides a circuit board, which may include the chip packaging structure provided in the present application.

[0073] An embodiment of the present application also provides an electronic device, which may include the chip packaging structure provided in the present application.

[0074] To summarize, the present embodiment provides a chip packaging structure, a circuit board and an electronic device. By setting a hollow area in the redistribution layer and placing the bridge chip in the hollow area, the bridge chip can be accurately positioned to avoid displacement of the bridge chip. In addition, by placing the bridge chip in the hollow area of ​​the redistribution layer and interconnecting at least two active chips through the bridge chip, the signal transmission efficiency can be improved, and the packaging space can be saved, the packaging thickness can be reduced, and the high sealing requirements can be met.

[0075] It should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the said element.

[0076] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A chip packaging structure, characterized in that: include: A plurality of redistribution layers, wherein the plurality of redistribution layers are provided with hollow areas for accommodating bridge chips, and the bridge chips are located in the hollow areas; The bridge chip comprises a first surface and a second surface arranged opposite to each other, and the first surface is provided with a bridge pin; At least two active chips, at least two of the active chips are located on one side of the redistribution layer, and the bridge chip is electrically connected to the at least two active chips through the bridge pins; A plastic encapsulation layer, wherein the plastic encapsulation layer and the active chip are located on the same side of the redistribution layer, and the plastic encapsulation layer is filled between the active chips.

2. The chip packaging structure according to claim 1, characterized in that: The bridge chip is provided with a plurality of through holes penetrating the first surface and the second surface, and the first surface and the second surface are electrically connected via a conductive material filled in the through holes.

3. The chip packaging structure according to claim 1, characterized in that: The thickness of the plurality of redistribution layers is equal to the thickness of the bridge chip.

4. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes a plurality of external pins, and the plurality of external pins are arranged on a side of the redistribution layer away from the plastic packaging layer.

5. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes a filling layer, and the filling layer is arranged between the active chip and the bridge chip.

6. The chip packaging structure according to claim 1, characterized in that: A plurality of connecting pins are disposed on one side of the active chip close to the redistribution layer, and the bridge chip is electrically connected to at least two of the active chips through the bridge pins and the connecting pins.

7. The chip packaging structure according to claim 1, characterized in that: The material of the plastic packaging layer includes epoxy resin molding compound.

8. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure includes a plurality of bridge chips, and the plurality of bridge chips are electrically connected to at least two active chips respectively.

9. A circuit board, characterized in that: The circuit board includes the chip packaging structure according to any one of claims 1-8.

10. An electronic device, characterized in that: The electronic device comprises the chip packaging structure according to any one of claims 1 to 8.

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