Duty ratio adjusting circuit for balancing DC bus voltage

Abstract

The utility model relates to a duty ratio adjusting circuit for balancing DC bus voltage, which is used for adjusting the duty ratio of four switch tubes of a parallel double-BUCK-BOOST circuit in a three-level energy storage inverter control circuit. An operational amplifier, a comparator and a resistor are adopted, and the duty ratio of a parallel double-BUCK-BOOST circuit switch tube is automatically corrected through proportional control by sampling the voltage difference value of a positive direct current bus and a negative direct current bus. Compared with the prior art, the system provided by the utility model has the advantages of high reliability and good real-time performance.

Description

Technical Field

[0001] The utility model relates to the technical field of inverters, in particular to a device for adjusting the duty ratio of a DC bus voltage. Background Technique

[0002] In a three-level energy storage inverter, since the three-level used in the inversion, whether it is in a one-word shape or a T-shape, requires two positive and negative DC buses to provide voltage support, but only one set of energy storage batteries is needed for connection. In this way, two BUCK-BOOST circuits need to be connected in parallel between the energy storage battery and the positive and negative DC bus capacitors. These two sets of parallel BUCK-BOOST circuits jointly complete the discharge of the energy storage battery to the DC bus and the charging of the energy storage battery by the DC bus. At the same time, one set or multiple sets of solar panels need to supply power to the DC bus through a BOOST circuit. The schematic diagram of a single battery charge and discharge with a two-way DC bus energy storage inverter is as Figure 1 shown.

[0003] Figure 1 In the figure, when the battery is in a power-deficient state, when the solar PV panel needs to charge the DC bus through the BOOST circuit or the mains reversely charges the DC bus voltage through the three-level inverter, the electric energy on the DC bus needs to be stored in the battery. The on-off of the switching tubes Q1 and Q3 in the positive-side BUCK-BOOST circuit connected to the positive-side DC bus capacitor belongs to a complementary working mode. When Q1 is on, Q3 is off, and when Q1 is off, Q3 is on. When boosting, Q1 serves as the main control tube to form a positive-side boost BOOST circuit, and when the DC bus charges the battery, Q3 serves as the main control tube to form a positive-side buck BUCK circuit. Similarly, the on-off of the switching tubes Q2 and Q4 in the negative-side BUCK-BOOST circuit connected to the negative-side DC bus capacitor belongs to a complementary working mode. When Q2 is on, Q4 is off, and when Q2 is off, Q4 is on. When boosting, Q2 serves as the main control tube to form a negative-side boost BOOST circuit, and when the DC bus charges the battery, Q4 serves as the main control tube to form a negative-side buck BUCK circuit.

[0004] When the battery is power-deficient and the DC bus needs to charge the battery, when the electric energy on the positive and negative DC buses needs to be transmitted to the battery, the two parallel positive and negative BUCK-BOOST circuits need to be regarded as a whole for step-down operation from right to left. Then Q3 and Q4 need to work synchronously as the active tubes. In this way, when Q3 and Q4 are synchronously turned on, the current flow diagram of the positive and negative DC bus voltages charging the inductors L1 and L2 simultaneously is as Figure 2 shown. In a switching cycle, after the main control tubes Q3 and Q4 are turned off, Q1 and Q2 need to be synchronously conducted to carry out freewheeling for the inductors L1 and L2. The schematic diagram of the inductor current freewheeling flow is as Figure 3 shown. Analyze Figure 2 and Figure 3The working process of charging the battery with the DC bus voltage is feasible.

[0005] However, due to the length of the switching tube drive signals and the individual differences between the switching tubes, in most cases, the switching tubes Q1 and Q2, and the switching tubes Q3 and Q4 cannot be fully synchronized in conduction. In addition, the differences in the capacitance values and self-impedances of the positive and negative DC bus capacitors C1 and C2 will cause a voltage imbalance between Vbus+ and Vbus- during the discharge process of the DC bus composed of C1 and C2 in series to the battery.

[0006] The harm of this voltage imbalance is huge. Since the sum of the positive and negative DC bus voltages remains unchanged during the charging process, once a deviation occurs between Vbus+ and Vbus-, it will cause the voltage of one of the C1 and C2 capacitors to rise. However, since electrolytic capacitors are often used for C1 and C2, and the withstand voltages of electrolytic capacitors are limited, in actual use, in order to save costs, the selected withstand voltage values of capacitors C1 and C2 will not be higher than the maximum value of the sum of Vbus+ and Vbus-. In this way, once a large voltage imbalance occurs between the positive and negative bus voltages, it will cause the capacitor to be damaged by overvoltage, resulting in the equipment being unable to work and endangering the safety of the equipment. Therefore, the problem of voltage imbalance between the positive and negative DC buses in this single-battery charge-discharge architecture must be solved. Summary of the Invention

[0007] The purpose of the present utility model is to provide a duty ratio adjustment circuit for balancing the DC bus voltage. The duty ratio adjustment circuit uses an operational amplifier, a comparator, and resistors to automatically correct the duty ratio of the switching tubes of the parallel dual BUCK-BOOST circuit through proportional control of the sampled difference between the positive and negative DC bus voltages, and can adjust the balance of the positive and negative DC bus voltages in real time, with high reliability and good real-time performance.

[0008] The purpose of the present utility model can be achieved through the following technical solutions:

[0009] A duty ratio adjustment circuit for balancing the DC bus voltage is used to adjust the duty ratio of the four switching tubes of the parallel dual BUCK-BOOST circuit in the control circuit of a three-level energy storage inverter. Among them, in the positive-side BUCK-BOOST circuit connected to the positive-side DC bus capacitor, the first switching tube and the third switching tube. When boosting, the first switching tube is used as the main control tube to form a positive-side boost BOOST circuit, and when the DC bus charges the battery, the third switching tube is used as the main control tube to form a positive-side buck BUCK circuit. The on-off of the second switching tube and the fourth switching tube in the negative-side BUCK-BOOST circuit connected to the negative-side DC bus capacitor belongs to a complementary working mode. When boosting, the second switching tube is used as the main control tube to form a negative-side boost BOOST circuit, and when the DC bus charges the battery, the fourth switching tube is used as the main control tube to form a negative-side buck BUCK circuit.

[0010] The duty cycle adjustment circuit includes a first operational amplifier, a second operational amplifier, a third operational amplifier, a fourth operational amplifier, a fifth operational amplifier, a sixth operational amplifier, a first comparator, a second comparator, a third comparator, a fourth comparator, and a triangular wave generator;

[0011] The positive potential signal V of the DC bus bus+ and the negative potential signal V bus- are respectively connected to the negative input terminal and the positive input terminal of the first operational amplifier;

[0012] The output of the first operational amplifier is connected to the negative input terminal of the second operational amplifier, the output of the second operational amplifier is connected to the negative input terminal of the third operational amplifier, the output of the third operational amplifier is connected to the negative input terminal of the fourth operational amplifier, and the positive half-cycle BUCK-BOOST duty cycle carrier signal is connected to the negative input terminal of the fourth operational amplifier; the output of the fourth operational amplifier is respectively connected to the positive input terminal of the first comparator to output a third PWM signal for driving the third switch tube, and connected to the negative input terminal of the second comparator to output a first PWM signal for driving the first switch tube;

[0013] The output of the first operational amplifier is connected to the negative input terminal of the fifth operational amplifier, the negative half-cycle BUCK-BOOST duty cycle carrier signal is connected to the negative input terminal of the fifth operational amplifier, and the output of the fifth operational amplifier is connected to the negative input terminal of the sixth operational amplifier; the output of the sixth operational amplifier is respectively connected to the positive input terminal of the third comparator to output a fourth PWM signal for driving the fourth switch tube, and connected to the negative input terminal of the fourth comparator to output a second PWM signal for driving the second switch tube;

[0014] The output of the triangular wave generator is respectively connected to the other input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator;

[0015] The first PWM signal and the third PWM signal are complementary, and the second PWM signal and the fourth PWM signal are complementary.

[0016] Preferably, the first operational amplifier, the second operational amplifier, the third operational amplifier, the fourth operational amplifier, the fifth operational amplifier, and the sixth operational amplifier are all configured with resistor negative feedback.

[0017] Preferably, the first operational amplifier is specifically:

[0018] The positive potential signal V of the DC bus bus+ is connected to the negative input terminal of the first operational amplifier after passing through a resistor with a resistance value of R1; a path is led out from the connection line between the resistor with a resistance value of R1 and the negative input terminal of the first operational amplifier and is connected to the output terminal of the first operational amplifier after passing through a resistor with a resistance value of R2;

[0019] DC bus negative potential signal V bus- It is connected to the positive input terminal of the first operational amplifier after passing through a resistor with a resistance value of R1; a path is led out from the connection line between the resistor with a resistance value of R1 and the positive input terminal of the first operational amplifier, and after passing through a resistor with a resistance value of R2, it is grounded.

[0020] Preferably, the second operational amplifier is specifically:

[0021] The output of the first operational amplifier is connected to the negative input terminal of the second operational amplifier after passing through a resistor with a resistance value of R6; a path is led out from the connection line between the resistor with a resistance value of R2 and the negative input terminal of the second operational amplifier, and after passing through a resistor with a resistance value of R6, it is connected to the output of the second operational amplifier;

[0022] The positive input terminal of the second operational amplifier is grounded after passing through a resistor with a resistance value of R6.

[0023] Preferably, the third operational amplifier is specifically:

[0024] The output of the second operational amplifier is connected to the negative input terminal of the third operational amplifier after passing through a resistor with a resistance value of R3; a path is led out from the connection line between the resistor with a resistance value of R3 and the negative input terminal of the third operational amplifier, and after passing through a resistor with a resistance value of R4, it is connected to the output of the second operational amplifier, and a path is led out and connected to the positive half-cycle BUCK - BOOST duty cycle carrier signal after passing through a resistor with a resistance value of R4;

[0025] The positive input terminal of the third operational amplifier is grounded after passing through a resistor with a resistance value of R5.

[0026] Preferably, the fifth operational amplifier is specifically:

[0027] The output of the first operational amplifier is connected to the negative input terminal of the fifth operational amplifier after passing through a resistor with a resistance value of R3; a path is led out from the connection line between the resistor with a resistance value of R3 and the negative input terminal of the fifth operational amplifier, and after passing through a resistor with a resistance value of R4, it is connected to the output of the fifth operational amplifier, and a path is led out and connected to the negative half-cycle BUCK - BOOST duty cycle carrier signal after passing through a resistor with a resistance value of R4;

[0028] The positive input terminal of the fifth operational amplifier is grounded after passing through a resistor with a resistance value of R5.

[0029] Preferably, the fourth operational amplifier is specifically:

[0030] The output of the third operational amplifier is connected to the negative input terminal of the fourth operational amplifier after passing through a resistor with a resistance value of R6; the resistor with a resistance value of R6 is connected to the output of the fourth operational amplifier;

[0031] The positive input terminal of the fourth operational amplifier is grounded after passing through a resistor with a resistance value of R6.

[0032] Preferably, the sixth operational amplifier is specifically:

[0033] The output of the fifth operational amplifier is connected to the negative input terminal of the sixth operational amplifier through a resistor with a resistance value of R6; the resistor with a resistance value of R6 is connected to the output of the sixth operational amplifier.

[0034] The positive input terminal of the sixth operational amplifier is grounded through a resistor with a resistance value of R6.

[0035] Preferably, for the resistors in the first operational amplifier, the second operational amplifier, the third operational amplifier, the fourth operational amplifier, the fifth operational amplifier, and the sixth operational amplifier, the parameter selection satisfies:

[0036] (V bus+ -V bus- ) * R2 * R4 / (R1 * R3) < 0.3 * Vt

[0037] Where: Vt is the amplitude of the triangular wave generated by the triangular wave generator.

[0038] Preferably, the BUCK-BOOST duty cycle carrier signals for driving the positive and negative half-cycles come from an analog controller.

[0039] Compared with the prior art, the present utility model has the following beneficial effects:

[0040] According to the influence of the different working states of the switching tubes in the parallel dual BUCK-BOOST circuit on the positive and negative DC bus capacitors, the present utility model uses operational amplifiers, comparators, and resistors to automatically correct the duty cycle of the switching tubes in the parallel dual BUCK-BOOST circuit by sampling the difference in the positive and negative DC bus voltages through proportional control, and can realize real-time adjustment of the balance of the positive and negative DC bus voltages. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a schematic diagram of a single-battery charge and discharge with a two-way DC bus energy storage inverter;

[0042] Figure 2 It is a schematic diagram of the current flow direction of the inductor when the third switching tube Q3 and the fourth switching tube Q4 are synchronously turned on to charge the inductor;

[0043] Figure 3 It is a schematic diagram of the current flow direction of the inductor when the first switching tube Q1 and the second switching tube Q2 are synchronously turned on to freewheel the inductor current;

[0044] Figure 4 It is a schematic diagram of the inductor current freewheeling loop when the second switching tube Q2 and the third switching tube Q3 are turned on;

[0045] Figure 5Schematic diagram of the inductor current freewheeling loop completed by the conduction of the first switching transistor Q1 and the fourth switching transistor Q4;

[0046] Figure 6 Schematic diagram of automatically adjusting the duty cycle of the dual - path BUCK - BOOST switching transistors according to the difference between the positive and negative DC bus voltages;

[0047] Reference numerals: R1 to R6 correspond to resistors with different resistance values, U1 to U6 are operational amplifiers, and U7 to U8 are comparators. Detailed implementation mode

[0048] The present utility model will be described in detail below with reference to the accompanying drawings and specific embodiments. This embodiment is implemented on the premise of the technical solution of the present utility model, and the detailed implementation mode and specific operation process are given, but the protection scope of the present utility model is not limited to the following embodiments.

[0049] It should be noted that: similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0050] Some implementation modes of the present utility model will be described in detail below with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0051] Embodiment

[0052] When Figure 2 When the inductor current freewheeling mode is turned on after the inductor charging is completed, if the negative - side Q4 is normally turned off and the positive - side Q3 is delayed in turning off, the schematic diagram of the inductor current freewheeling loop at this time is as Figure 4 shown. In this mode, it will cause the electric energy on the positive DC bus capacitor C1 to continue to discharge, which will cause the Vbus + voltage to drop more compared to Vbus -.

[0053] Similarly, when Figure 2 When the inductor current freewheeling mode is turned on after the inductor charging is completed, if the negative - side Q4 is delayed in turning off and the positive - side Q3 is normally turned off, the schematic diagram of the inductor current freewheeling loop is as Figure 5 shown. In this mode, it will cause the electric energy on the C1 capacitor to continue to discharge, which will cause the Vbus - voltage to drop more compared to Vbus +.

[0054] In this way, comprehensively Figure 4 and Figure 5For the circuit analysis, when Vbus+ is higher than Vbus-, appropriately increase the duty cycle of the positive half main control transistor Q3 and decrease the duty cycle of the negative half main control transistor Q4. Similarly, when Vbus- is higher than Vbus+, appropriately increase the duty cycle of the negative half main control transistor Q4 and decrease the duty cycle of the positive half main control transistor Q3. By using the method of the duty cycle difference between the main control transistors Q3 and Q4 of Figure 4 and Figure 5 , the balance of the positive and negative DC bus voltages can be adjusted.

[0055] For the analog proportional controller composed of devices such as operational amplifiers, comparators, and resistors to control Figure 1 the discharge circuit, a device for adjusting the balance of the positive and negative DC bus voltages needs to be designed. By using Figure 4 and Figure 5 , the duty cycle is appropriately corrected so that the positive and negative DC bus voltages can be maintained stable.

[0056] For this reason, this embodiment provides a duty cycle adjustment circuit for balancing the DC bus voltage, as shown in Figure 6 . It is used to adjust the duty cycle of the four switching transistors in the parallel double BUCK-BOOST circuit of the three-level energy storage inverter control circuit. Among them, in the positive BUCK-BOOST circuit connected to the positive DC bus capacitor, the first switching transistor Q1 and the third switching transistor Q3. When boosting, the first switching transistor Q1 serves as the main control transistor to form a positive boost BOOST circuit. When the DC bus charges the battery, the third switching transistor Q3 serves as the main control transistor to form a positive buck BUCK circuit. The on-off of the second switching transistor Q2 and the fourth switching transistor Q4 in the negative BUCK-BOOST circuit connected to the negative DC bus capacitor belongs to a complementary working mode. When boosting, the second switching transistor Q2 serves as the main control transistor to form a negative boost BOOST circuit. When the DC bus charges the battery, the fourth switching transistor Q4 serves as the main control transistor to form a negative buck BUCK circuit.

[0057] The duty cycle adjustment circuit includes a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, a fourth operational amplifier U4, a fifth operational amplifier U5, a sixth operational amplifier U6, a first comparator U7, a second comparator U8, a third comparator U9, a fourth comparator U10, and a triangular wave generator;

[0058] The positive potential signal V of the DC bus bus+ , the negative potential signal V of the DC bus bus- are respectively connected to the negative input terminal and the positive input terminal of the first operational amplifier U1;

[0059] The output of the first operational amplifier U1 is connected to the negative input terminal of the second operational amplifier U2, the output of the second operational amplifier U2 is connected to the negative input terminal of the third operational amplifier U3, the output of the third operational amplifier U3 is connected to the negative input terminal of the fourth operational amplifier U4, and the positive half-cycle BUCK-BOOST duty-cycle carrier signal is connected to the negative input terminal of the fourth operational amplifier U4; the output of the fourth operational amplifier U4 is respectively connected to the positive input terminal of the first comparator U7 to output a third PWM signal for driving the third switching transistor Q3, and connected to the negative input terminal of the second comparator U8 to output a first PWM signal for driving the first switching transistor Q1;

[0060] The output of the first operational amplifier U1 is connected to the negative input terminal of the fifth operational amplifier U5, the negative half-cycle BUCK-BOOST duty-cycle carrier signal is connected to the negative input terminal of the fifth operational amplifier U5, and the output of the fifth operational amplifier U5 is connected to the negative input terminal of the sixth operational amplifier U6; the output of the sixth operational amplifier U6 is respectively connected to the positive input terminal of the third comparator U9 to output a fourth PWM signal for driving the fourth switching transistor Q4, and connected to the negative input terminal of the fourth comparator U10 to output a second PWM signal for driving the second switching transistor Q2;

[0061] The output of the triangular wave generator is respectively connected to the other input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator;

[0062] The first PWM signal and the third PWM signal are complementary, and the second PWM signal and the fourth PWM signal are complementary.

[0063] The first operational amplifier U1, the second operational amplifier U2, the third operational amplifier U3, the fourth operational amplifier U4, the fifth operational amplifier U5, and the sixth operational amplifier U6 are all configured with resistor negative feedback, and the specific settings are as follows:

[0064] 1) The first operational amplifier U1

[0065] The positive potential signal V of the DC bus bus+ After passing through a resistor with a resistance value of R1, it is connected to the negative input terminal of the first operational amplifier U1; a path is led out from the connection line between the resistor with a resistance value of R1 and the negative input terminal of the first operational amplifier U1, and after passing through a resistor with a resistance value of R2, it is connected to the output terminal of the first operational amplifier U1;

[0066] The negative potential signal V of the DC bus bus- After passing through a resistor with a resistance value of R1, it is connected to the positive input terminal of the first operational amplifier U1; a path is led out from the connection line between the resistor with a resistance value of R1 and the positive input terminal of the first operational amplifier U1, and after passing through a resistor with a resistance value of R2, it is grounded.

[0067] 2) The second operational amplifier U2

[0068] The output of the first operational amplifier U1 is connected to the negative input terminal of the second operational amplifier U2 through a resistor with a resistance value of R6; a path is led out from the connection line between the resistor with a resistance value of R2 and the negative input terminal of the second operational amplifier U2, and after passing through a resistor with a resistance value of R6, it is connected to the output of the second operational amplifier U2.

[0069] The positive input terminal of the second operational amplifier U2 is grounded through a resistor with a resistance value of R6.

[0070] 3) The third operational amplifier U3

[0071] The output of the second operational amplifier U2 is connected to the negative input terminal of the second operational amplifier U2 through a resistor with a resistance value of R3; a path is led out from the connection line between the resistor with a resistance value of R3 and the negative input terminal of the third operational amplifier U3, and after passing through a resistor with a resistance value of R4, it is connected to the output of the second operational amplifier U2, and a path is led out and connected to the positive half-cycle BUCK - BOOST duty cycle carrier signal after passing through a resistor with a resistance value of R4.

[0072] The positive input terminal of the third operational amplifier U3 is grounded through a resistor with a resistance value of R5.

[0073] 4) The fourth operational amplifier U4

[0074] The output of the third operational amplifier U3 is connected to the negative input terminal of the fourth operational amplifier U4 through a resistor with a resistance value of R6; the resistor with a resistance value of R6 is connected to the output of the fourth operational amplifier U4.

[0075] The positive input terminal of the fourth operational amplifier U4 is grounded through a resistor with a resistance value of R6.

[0076] 5) The fifth operational amplifier U5

[0077] The output of the first operational amplifier U1 is connected to the negative input terminal of the fifth operational amplifier U5 through a resistor with a resistance value of R3; a path is led out from the connection line between the resistor with a resistance value of R3 and the negative input terminal of the fifth operational amplifier U5, and after passing through a resistor with a resistance value of R4, it is connected to the output of the fifth operational amplifier U5, and a path is led out and connected to the negative half-cycle BUCK - BOOST duty cycle carrier signal after passing through a resistor with a resistance value of R4.

[0078] The positive input terminal of the fifth operational amplifier U5 is grounded through a resistor with a resistance value of R5.

[0079] 6) The sixth operational amplifier U6

[0080] The output of the fifth operational amplifier U5 is connected to the negative input terminal of the sixth operational amplifier U6 through a resistor with a resistance value of R6; the resistor with a resistance value of R6 is connected to the output of the sixth operational amplifier U6.

[0081] The positive input terminal of the sixth operational amplifier U6 is grounded through a resistor with a resistance value of R6.

[0082] In this embodiment, the BUCK - BOOST duty - cycle carrier signals for driving the positive and negative half - cycles come from an analog controller.

[0083] DQ13 and DQ24 are the BUCK - BOOST duty - cycle carrier signals sent by the analog controller to drive the positive and negative half - cycles respectively; Q1 - Duty is the PWM signal for driving the first switching transistor Q1, Q3 - Duty is the PWM signal for driving the third switching transistor Q3, Q2 - Duty is the PWM signal for driving the second switching transistor Q2, and Q4 - Duty is the PWM signal for driving the fourth switching transistor Q4.

[0084] Since Q1 - Duty and Q3 - Duty are in a complementary working mode, and Q2 - Duty and Q4 - Duty are also in a complementary working mode. When charging the battery, Q3 and Q4 are the main control switching transistors, and Q1 and Q2 are the free - wheeling switching transistors. Therefore, when designing the generation of the PWM wave signal, DQ13 - Duty is connected to the positive input terminal of the comparator U7, and the triangular wave generator is connected to the negative input terminal to generate the PWM drive signal Q3 - Duty for driving the Q3 transistor; DQ13 - Duty is connected to the negative input terminal of the comparator U8, and the triangular wave generator is connected to the positive input terminal to generate the PWM drive signal Q1 - Duty for driving the Q1 transistor; similarly, DQ24 - Duty is connected to the positive input terminal of the comparator U9, and the triangular wave generator is connected to the negative input terminal to generate the PWM drive signal Q4 - Duty for driving the Q4 transistor; DQ24 - Duty is connected to the negative input terminal of the comparator U10, and the triangular wave generator is connected to the positive input terminal to generate the PWM drive signal Q2 - Duty for driving the Q2 transistor.

[0085] The drive signals DQ13, DQ24 and the positive and negative potential signals V bus+ 、V bus- After the linear calculation by the operational amplifier, the carrier signals DQ13 - Duty and DQ24 - Duty are obtained:

[0086] DQ13 - Duty = DQ13 + (V bus+ -V bus- )*R2*R4 / (R1*R3) (1)

[0087] DQ24 - Duty = DQ24 - (V bus+ -V bus- )*R2*R4 / (R1*R3) (2)

[0088] The resistor parameter selection satisfies:

[0089] (V bus+-V bus- )*R2*R4 / (R1*R3) < 0.3*Vt (3)

[0090] Among them, Vt represents the amplitude of the triangular wave generated by the triangular wave generator. This means that the duty cycle adjustment component (V bus+ -V bus- )*R2*R4 / (R1*R3) can change the duty cycle carrier signals of DQ13 and DQ24 by up to 30%. When V bus+ is equal to V bus- , (V bus+ -V bus- )*R2*R4 / (R1*R3) is also zero and no adjustment is made.

[0091] In specific design, the resistance parameters are rewritten as:

[0092] V ref *R2*R4 / (R1*R3) < 0.3*Vt (4)

[0093] Among them, V ref is the reference value of the single side of the positive and negative DC bus voltages. Generally speaking, in the ideal state, V bus+ and V bus- are both equal to V ref. .

[0094] According to the influence of the different working states of the switching tubes of the parallel dual BUCK - BOOST circuit on the positive and negative DC bus capacitors, by using devices such as operational amplifiers, comparators, and resistors, the duty cycle of the switching tubes of the parallel dual BUCK - BOOST circuit is automatically corrected through proportional control by sampling the difference between the positive and negative DC bus voltages, so as to achieve the purpose of real - time adjustment of the balance of the positive and negative DC bus voltages.

[0095] The utility model is realized through the design of operational amplifiers and comparators, with high reliability, can effectively solve the balance of the positive and negative DC bus voltages, low cost, and is easy to be applied in practical engineering.

Claims

1. A duty cycle adjustment circuit for balancing DC bus voltage, used for adjusting the duty cycle of four switch tubes of a parallel dual BUCK-BOOST circuit in a three-level energy storage inverter control circuit, wherein: The first switch tube and the third switch tube in the positive-side BUCK-BOOST circuit connected to the positive-side DC bus capacitor, the first switch tube acts as the main control tube to form a positive-side boost BOOST circuit when boosting, and the third switch tube acts as the main control tube to form a positive-side buck BUCK circuit when the DC bus charges the battery, and the opening and closing of the second switch tube and the fourth switch tube in the negative-side BUCK-BOOST circuit connected to the negative-side DC bus capacitor belong to a complementary working mode, the second switch tube acts as the main control tube to form a negative-side boost BOOST circuit when boosting, and the fourth switch tube acts as the main control tube to form a negative-side buck BUCK circuit when the DC bus charges the battery, characterized in that: The duty cycle adjustment circuit includes a first operational amplifier, a second operational amplifier, a third operational amplifier, a fourth operational amplifier, a fifth operational amplifier, a sixth operational amplifier, a first comparator, a second comparator, a third comparator, a fourth comparator and a triangular wave generator; DC bus positive potential signal V bus+ , negative potential signal V bus- are respectively connected to the negative input terminal and the positive input terminal of the first operational amplifier; The output of the first operational amplifier is connected to the negative input terminal of the second operational amplifier, the output of the second operational amplifier is connected to the negative input terminal of the third operational amplifier, the output of the third operational amplifier is connected to the negative input terminal of the fourth operational amplifier, and the positive half-cycle BUCK-BOOST duty cycle carrier signal is connected to the negative input terminal of the fourth operational amplifier; the output of the fourth operational amplifier is respectively connected to the positive input terminal of the first comparator to output a third PWM signal for driving the third switch tube, and connected to the negative input terminal of the second comparator to output a first PWM signal for driving the first switch tube; The output of the first operational amplifier is connected to the negative input terminal of the fifth operational amplifier, the negative half-cycle BUCK-BOOST duty cycle carrier signal is connected to the negative input terminal of the fifth operational amplifier, and the output of the fifth operational amplifier is connected to the negative input terminal of the sixth operational amplifier; the output of the sixth operational amplifier is respectively connected to the positive input terminal of the third comparator to output a fourth PWM signal for driving the fourth switch tube, and is connected to the negative input terminal of the fourth comparator to output a second PWM signal for driving the second switch tube; Connecting the output of the triangular wave generator to the other input terminals of the first comparator, the second comparator, the third comparator and the fourth comparator respectively; The first PWM signal is complementary to the third PWM signal, and the second PWM signal is complementary to the fourth PWM signal.

2. A duty cycle adjustment circuit for balancing a DC bus voltage according to claim 1, characterized in that: The first operational amplifier, the second operational amplifier, the third operational amplifier, the fourth operational amplifier, the fifth operational amplifier and the sixth operational amplifier are all in a resistor negative feedback configuration.

3. A duty cycle adjustment circuit for balancing a DC bus voltage according to claim 2, characterized in that: The first operational amplifier is specifically: DC bus positive potential signal V bus+ A line connected between the resistor with a resistance value of R1 and the negative input terminal of the first operational amplifier is led out through a resistor with a resistance value of R2 and then connected to the output terminal of the first operational amplifier; DC bus negative potential signal V bus- The resistor with a resistance value of R1 is connected to the positive input terminal of the first operational amplifier; a path is led out from the connection line between the resistor with a resistance value of R1 and the positive input terminal of the first operational amplifier and then connected to the ground through a resistor with a resistance value of R2.

4. A duty cycle adjustment circuit for balancing a DC bus voltage according to claim 3, characterized in that: The second operational amplifier is specifically: The output of the first operational amplifier is connected to the negative input terminal of the second operational amplifier through a resistor with a resistance value of R6; a path is led out from the connection line between the resistor with a resistance value of R2 and the negative input terminal of the second operational amplifier through a resistor with a resistance value of R6 and then connected to the output of the second operational amplifier; The positive input terminal of the second operational amplifier is grounded via a resistor R6.

5. The duty cycle adjustment circuit for balancing a DC bus voltage according to claim 1, characterized in that: The third operational amplifier is specifically: The output of the second operational amplifier is connected to the negative input terminal of the second operational amplifier through a resistor with a resistance value of R3; a path is led out from the connection line between the resistor with a resistance value of R3 and the negative input terminal of the third operational amplifier, and then connected to the output of the second operational amplifier through a resistor with a resistance value of R4, and then connected to the positive half-cycle BUCK-BOOST duty cycle carrier signal after being led out through a resistor with a resistance value of R4; The positive input terminal of the third operational amplifier is grounded via a resistor R5.

6. A duty cycle adjustment circuit for balancing a DC bus voltage according to claim 5, characterized in that: The fifth operational amplifier is specifically: The output of the first operational amplifier is connected to the negative input terminal of the fifth operational amplifier through a resistor with a resistance value of R3; a path is led out from the connection line between the resistor with a resistance value of R3 and the negative input terminal of the fifth operational amplifier, and then connected to the output of the fifth operational amplifier through a resistor with a resistance value of R4, and then connected to the negative half-cycle BUCK-BOOST duty cycle carrier signal through a resistor with a resistance value of R4; The positive input terminal of the fifth operational amplifier is grounded via a resistor R5.

7. A duty cycle adjustment circuit for balancing a DC bus voltage according to claim 6, characterized in that: The fourth operational amplifier is specifically: The output of the third operational amplifier is connected to the negative input terminal of the fourth operational amplifier through a resistor with a resistance value of R6; the resistor with a resistance value of R6 is connected to the output of the fourth operational amplifier; The positive input terminal of the fourth operational amplifier is grounded via a resistor with a resistance value of R6.

8. The duty cycle adjustment circuit for balancing a DC bus voltage according to claim 7, characterized in that: The sixth operational amplifier is specifically: The output of the fifth operational amplifier is connected to the negative input terminal of the sixth operational amplifier through a resistor with a resistance value of R6; the resistor with a resistance value of R6 is connected to the output of the sixth operational amplifier; The positive input terminal of the sixth operational amplifier is grounded via a resistor with a resistance value of R6.

9. A duty cycle adjustment circuit for balancing a DC bus voltage according to claim 8, characterized in that: For the resistors in the first operational amplifier, the second operational amplifier, the third operational amplifier, the fourth operational amplifier, the fifth operational amplifier, and the sixth operational amplifier, the parameters are selected to satisfy: (V bus+ -V bus- )*R2*R4 / (R1*R3)<0.3*V Where: Vt is the triangle wave amplitude generated by the triangle wave generator.

10. The duty cycle adjustment circuit for balancing a DC bus voltage according to claim 1, characterized in that: The BUCK-BOOST duty cycle carrier signal used to drive the positive and negative half cycles comes from the analog controller.

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