Circuit board card and signal generator
By designing a circuit board card that includes a low-speed bus interface, a high-speed bus interface and a bus expansion module, the problem that the board card in the prior art only supports one bus communication scenario, and the compatibility of multiple bus communication scenarios is achieved, testing flexibility and production efficiency are improved.
Patent Information
- Application Number
- CN202421991565.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-15
- Publication Date
- 2025-06-03
- Estimated Expiration
- 2034-08-15
AI Technical Summary
In the prior art, circuit boards only support one bus communication scenario, and are difficult to be compatible with multiple bus communication scenarios, which limits the test flexibility and application range of the image generator.
A circuit board card is designed, including the main card and the backboard. The backboard is equipped with a low-speed bus interface, a high-speed bus interface and a child card interface. The main card is equipped with corresponding interfaces. The high-speed bus expansion module is used to realize the expansion of the high-speed bus, and supports the use of low-speed bus and/or high-speed buses between the main card and the child card for communication.
It realizes the compatibility of the board and card for multiple bus communication scenarios, improves testing flexibility, simplifies the R&D and production process, and reduces the inventory and management costs of spare parts.
Smart Images
Figure CN222939486U_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of electronic circuit technology, and more specifically, relates to a circuit board card and a signal generator. Background Art
[0002] Pattern Generator (PG) is a professional test equipment used to evaluate and calibrate the performance of display devices. Display devices can be liquid crystal displays (LCD), light emitting diode displays (LED) or organic light emitting diode displays (OLED). PG can generate a series of standard or customized image patterns to detect the resolution, color accuracy, brightness, contrast, response time, and the presence of dead pixels of display devices.
[0003] Generally, a PG consists of a main card, multiple sub-cards, and a backplane. The main card communicates with multiple sub-cards through the backplane. The main card is used to control each sub-card, and the sub-card is connected to the device under test. The main card and sub-cards can communicate using a high-speed bus or a low-speed bus.
[0004] In the prior art, for the situation that the main card and the sub-card can use a high-speed bus for communication, the corresponding board (including the main card and the backplane, etc.) will be designed. For the situation that the main card and the sub-card can use a low-speed bus for communication, the corresponding board will also be designed. The same board only supports one bus communication scenario (low-speed bus communication scenario or high-speed bus communication scenario). For PG boards, how to be compatible with multiple bus communication scenarios is a technical problem that needs to be solved urgently in the industry. Utility Model Content
[0005] In view of the defects of the prior art, the purpose of this application is to make the PG board compatible with multiple bus communication scenarios.
[0006] To achieve the above-mentioned purpose, in a first aspect, the present application provides a circuit board card, comprising: a main card and a backplane;
[0007] The backplane is configured with a low-speed bus interface for docking the main card, a high-speed bus interface for docking the main card, and multiple sub-card interfaces;
[0008] The main card is equipped with a low-speed bus interface for connecting to the backplane and a high-speed bus interface for connecting to the backplane;
[0009] The low-speed bus interface corresponds to the low-speed bus pins in the multiple daughter card interfaces;
[0010] The high-speed bus interface is connected to the high-speed bus pins in multiple daughter card interfaces through a bus expansion module.
[0011] The board card provided by the embodiment of the present application can support communication between the main card and the daughter card using a low-speed bus and / or a high-speed bus, and can be compatible with multiple bus communication scenarios.
[0012] In a possible implementation manner, the backplane is configured with a bus expansion interface for docking a bus expansion board, and the bus expansion module is specifically a bus expansion board;
[0013] When the main card and the daughter card communicate using a high-speed bus, a bus expansion board is plugged into the bus expansion interface, and the high-speed bus interface is connected to the high-speed bus pins in multiple daughter card interfaces through the bus expansion board.
[0014] In a possible implementation manner, the low-speed bus interface is configured with multiple groups of low-speed bus pins, and a group of low-speed bus pins in the low-speed bus interface is correspondingly connected to a group of low-speed bus pins in a daughter card interface;
[0015] The bus expansion interface is configured with multiple groups of high-speed bus pins, and a group of high-speed bus pins in a daughter card interface is correspondingly connected to a group of high-speed bus pins in the bus expansion interface;
[0016] The high-speed bus interface is configured with at least one group of high-speed bus pins, and a group of high-speed bus pins in the high-speed bus interface is correspondingly connected to a group of high-speed bus pins in the bus expansion interface.
[0017] In a possible implementation manner, the bus expansion board is configured with at least one high-speed bus switching chip. The high-speed bus pins in the same group in the high-speed bus interface are connected to the same high-speed bus switching chip. The high-speed bus switching chip is used to expand each group of high-speed bus pins in the high-speed bus interface into multiple groups of high-speed bus pins, and each group of the expanded multiple groups of high-speed bus pins is correspondingly connected to a group of high-speed bus pins in a daughter card interface.
[0018] In a possible implementation manner, the bus expansion interface and the bus expansion board are provided with a first high-speed snap connector, and each group of high-speed bus pins in the high-speed bus interface of the backplane is connected to the high-speed bus switching chip through the first high-speed snap connector;
[0019] The bus expansion interface and the bus expansion board are provided with a second high-speed snap connector, and the high-speed bus pins in each daughter card interface are connected to the high-speed bus switching chip through the second high-speed snap connector.
[0020] In a possible implementation manner, on the backplane, the low-speed bus interface and the high-speed bus interface use the same high-speed bus connector;
[0021] On the main card, the low-speed bus interface and the high-speed bus interface use the same high-speed bus connector;
[0022] The high-speed bus connector on the backplane is a male or female socket. Correspondingly, the high-speed bus connector on the main card is a female or male socket.
[0023] In a possible implementation, the main card is configured with a master control chip slot, which is connected to the low-speed bus interface of the main card and is also connected to the high-speed bus interface of the main card.
[0024] Optionally, a master control chip is placed on the master control chip slot. The master control chip is configured with a low-speed bus, and the low-speed bus of the master control chip is connected to the low-speed bus interface.
[0025] Optionally, a master control chip is placed on the master control chip slot. The master control chip is configured with a high-speed bus, and the high-speed bus of the master control chip is connected to the high-speed bus interface.
[0026] Optionally, the master control chip is an FPGA or an MCU.
[0027] In a possible implementation, the main card includes: a master control chip carrier board and a low-speed bus interface board;
[0028] The master control chip carrier board is configured with a master control chip slot, a high-speed bus interface for docking with the backplane, and a low-speed bus slot for carrying the low-speed bus interface board in a stacked manner;
[0029] The low-speed bus interface board is configured with a low-speed bus interface for docking with the backplane;
[0030] The master control chip slot is connected to the low-speed bus interface through the low-speed bus slot, and the master control chip slot is connected to the high-speed bus interface.
[0031] In a possible implementation, the low-speed bus interface is configured with multiple pins for transmitting slot status signals, and / or the high-speed bus interface is configured with multiple pins for transmitting slot status signals;
[0032] On the backplane, a pin for transmitting a slot status signal is correspondingly connected to a slot status signal pin of a daughter card interface to receive the slot status signal sent by the daughter card;
[0033] On the main card, each pin for transmitting a slot status signal is connected to the master control chip slot.
[0034] In a possible implementation, the low-speed bus interface is configured with multiple pins for transmitting synchronization signals, and / or the high-speed bus interface is configured with multiple pins for transmitting synchronization signals;
[0035] On the backplane, a pin for transmitting a synchronization signal is correspondingly connected to a synchronization signal pin of a daughter card interface;
[0036] On the main card, each pin for transmitting a synchronization signal is connected to a main control chip slot.
[0037] In a possible implementation, the high-speed bus is a PCIe bus.
[0038] In a possible implementation, the low-speed bus is an SPI bus or an I2C bus.
[0039] In a second aspect, the present application further provides a signal generator, including: a daughter card and any one of the above circuit boards.
[0040] Generally speaking, compared with the prior art, the above technical solution conceived by the present application has the following beneficial effects:
[0041] (1) Improve R & D and production efficiency: During the R & D process, only one general-purpose board needs to be developed and iterated, instead of multiple different boards, which simplifies the R & D process and improves the R & D work efficiency; During the production process, only one general-purpose board needs to be operated, instead of multiple different boards, which simplifies the training process for production personnel, reduces the operation difficulty of production personnel, and improves the work efficiency of production personnel.
[0042] (2) Enhance the flexibility of testing: During the testing process, flexible switching between high-speed bus communication and low-speed bus communication can be achieved without replacing the board. It can also support the testing scenario where both low-speed bus communication and high-speed bus communication are used between the main card and multiple daughter cards, expanding the application range of the board.
[0043] (3) Reduce spare parts: Since one board can be applicable to multiple bus communication scenarios, there is no need to prepare multiple dedicated boards for different bus communication requirements, which can reduce the inventory of spare parts and lower the management cost. Description of the Drawings
[0044] Figure 1 is one of the schematic structural diagrams of the backplane provided by the embodiment of the present application;
[0045] Figure 2 is one of the schematic structural diagrams of the main card provided by the embodiment of the present application;
[0046] Figure 3It is the second schematic structural diagram of the backplane provided by the embodiment of the present application;
[0047] Figure 4 It is the second schematic structural diagram of the main card provided by the embodiment of the present application;
[0048] Figure 5 It is the schematic pin configuration diagram of the low-speed bus interface provided by the embodiment of the present application;
[0049] Figure 6 It is the schematic pin configuration diagram of the high-speed bus interface provided by the embodiment of the present application. Specific embodiments
[0050] To facilitate a clearer understanding of the embodiments of the present application, some relevant background knowledge is introduced as follows.
[0051] If the main card and the daughter card can communicate using a high-speed bus, the control modules on the main card and the daughter card need to support the high-speed bus communication standard. Moreover, since the high-speed bus resources of the control module on the main card are limited (generally, there is 1 or 2 high-speed buses configured in the control module on the main card, and the number of high-speed buses configured by the control module is less than the number of daughter cards, which cannot meet the requirement of the main card to communicate with multiple daughter cards), it is necessary to set a bus expansion module on the backplane. The bus expansion module is used to expand the high-speed bus of the main card, expanding one high-speed bus into multiple high-speed buses, so that the number of expanded high-speed buses matches the number of daughter cards.
[0052] If the main card and the daughter card can communicate using a low-speed bus, the control modules on the main card and the daughter card need to support the low-speed bus communication standard. Moreover, since the low-speed bus resources of the control module on the main card are relatively rich (generally, there are multiple low-speed buses configured in the control module on the main card, which can meet the requirement of the main card to communicate with multiple daughter cards), it is not necessary to set a bus expansion module on the backplane.
[0053] The same board card (including the main card and the backplane, etc.) only supports one bus communication scenario, either the low-speed bus communication scenario or the high-speed bus communication scenario, with poor compatibility.
[0054] To overcome the above defects, the present application provides a circuit board card and a signal generator, which can support communication between the main card and the daughter card using a low-speed bus and / or a high-speed bus, realizing compatibility with multiple bus communication scenarios.
[0055] To make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0056] In this text, the term "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In this text, the symbol " / " indicates that the associated objects are in an "or" relationship. For example, A / B means A or B.
[0057] In the embodiments of this application, words such as "exemplary" or "for example" are used to give examples, illustrations, or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner.
[0058] In the description of the embodiments of this application, unless otherwise specified, "a plurality of" means two or more. For example, a plurality of processing units means two or more processing units, and a plurality of components means two or more components.
[0059] The embodiments of this application will be described below in conjunction with the accompanying drawings in the embodiments of this application.
[0060] The embodiments of this application provide a circuit board card, which includes a main card and a backplane.
[0061] Figure 1 is one of the structural schematic diagrams of the backplane provided by the embodiments of this application. As Figure 1 shown, the backplane is configured with a low-speed bus interface for docking with the main card, a high-speed bus interface for docking with the main card, and a plurality of daughter card interfaces. Figure 1 The number of daughter card interfaces shown in [the figure] is m. The low-speed bus interface is connected to the low-speed bus pins in the plurality of daughter card interfaces. As Figure 1 shown, a group of low-speed bus pins in each daughter card interface is connected to the low-speed bus interface.
[0062] The high-speed bus interface can be connected to the high-speed bus pins in the plurality of daughter card interfaces through a bus expansion module. The bus expansion module can expand the high-speed bus of the main control chip, and the number of high-speed buses obtained after expansion is the same as the number of daughter card interfaces. The bus expansion module can be a module integrated on the backplane; the bus expansion module can also be a discrete module, which is plugged into the backplane when the main card and the daughter card communicate using a high-speed bus.
[0063] Optionally, as Figure 1As shown in the figure, the backplane is configured with a bus expansion interface for docking with a bus expansion board. The bus expansion module is specifically a bus expansion board, which can expand the high-speed bus of the main control chip. The number of high-speed buses obtained after expansion is the same as the number of daughter card interfaces. When the main card and the daughter card communicate using a high-speed bus, a bus expansion board is plugged into the bus expansion interface, and the high-speed bus interface is connected to the high-speed bus pins of multiple daughter card interfaces through the bus expansion board.
[0064] Figure 2 is one of the structural schematic diagrams of the main card provided by the embodiment of the present application. As Figure 2 shown, the main card is configured with a low-speed bus interface for docking with the backplane and a high-speed bus interface for docking with the backplane.
[0065] The low-speed bus of the main control chip on the main card can be connected to the low-speed bus pins of multiple daughter card interfaces via the low-speed bus interface, and it can support communication between the main card and the daughter card using a low-speed bus.
[0066] The high-speed bus of the main control chip on the main card can be connected to the bus expansion module via the high-speed bus interface. The bus expansion module can expand the high-speed bus of the main control chip. The number of high-speed buses obtained after expansion is the same as the number of daughter card interfaces. The high-speed buses obtained after expansion are connected to the high-speed bus pins of multiple daughter card interfaces, realizing the connection between the high-speed bus interface and the high-speed bus pins of multiple daughter card interfaces through the bus expansion module, and it can support communication between the main card and the daughter card using a high-speed bus.
[0067] Therefore, the board card provided by the embodiment of the present application can support communication between the main card and the daughter card using a low-speed bus and / or a high-speed bus, realizing compatibility with multiple bus communication scenarios.
[0068] In a possible implementation, the circuit board card includes: a main card and a backplane.
[0069] Figure 3 is the second structural schematic diagram of the backplane provided by the embodiment of the present application. As Figure 3 shown, the backplane is configured with a low-speed bus interface for docking with the main card, a high-speed bus interface for docking with the main card, a bus expansion interface for docking with the bus expansion board, and multiple daughter card interfaces (one daughter card interface is connected to one daughter card). The communication rate of the high-speed bus is higher than that of the low-speed bus.
[0070] Figure 4 is the second structural schematic diagram of the main card provided by the embodiment of the present application. As Figure 4As shown in the figure, the main card is configured with a main control chip slot (for carrying the main control chip), a low-speed bus interface for docking with the backplane, and a high-speed bus interface for docking with the backplane. The main control chip slot is connected to the low-speed bus interface and the high-speed bus interface.
[0071] Optionally, as Figure 4 shown in the figure, the main card is also configured with an external interface. Exemplarily, the main card can communicate with the host computer through the external interface.
[0072] The low-speed bus interface is configured with multiple groups of low-speed bus pins. One group of low-speed bus pins is used to transmit multiple low-speed bus signals. One group of low-speed bus pins in the low-speed bus interface corresponds to and is connected to one group of low-speed bus pins in a daughter card interface; the high-speed bus interface is configured with at least one group of high-speed bus pins. One group of high-speed bus pins is used to transmit one high-speed bus signal.
[0073] Exemplarily, Figure 5 is a schematic diagram of the pin configuration of the low-speed bus interface provided by an embodiment of the present application. As Figure 5 shown in the figure, the low-speed bus interface can be configured with m groups of low-speed bus pins, where m can represent the number of daughter card interfaces. Figure 6 is a schematic diagram of the pin configuration of the high-speed bus interface provided by an embodiment of the present application. As Figure 6 shown in the figure, the high-speed bus interface can be configured with n groups of high-speed bus pins, where n can represent the number of high-speed bus lines supported by the main control chip.
[0074] When the main card and the daughter card communicate using the high-speed bus, a bus expansion board is plugged into the bus expansion interface. The bus expansion board is configured with at least one high-speed bus switching chip. The same group of high-speed bus pins in the high-speed bus interface is connected to the same high-speed bus switching chip. The high-speed bus switching chip is used to expand each group of high-speed bus pins in the high-speed bus interface into multiple groups of high-speed bus pins. Each group of the expanded high-speed bus pins corresponds to and is connected to one group of high-speed bus pins in a daughter card interface.
[0075] Next, the working principle of the circuit board card provided by the embodiment of the present application will be introduced.
[0076] During the process of assembling the board card, the low-speed bus interface and the high-speed bus interface on the main card can be aligned with the low-speed bus interface and the high-speed bus interface on the backplane. When they are aligned, the main card is plugged into the backplane. After the plugging is completed, the low-speed bus interface on the main card is electrically connected to the low-speed bus interface on the backplane, and the high-speed bus interface on the main card is electrically connected to the high-speed bus interface on the backplane.
[0077] The low-speed bus interface on the backplane is a male or female socket. Correspondingly, the low-speed bus interface on the main card is a female or male socket, so as to ensure that the low-speed bus interface on the backplane can be adapted to the low-speed bus interface on the main card, and realize a reliable electrical connection between the low-speed bus on the backplane and the low-speed bus on the main card.
[0078] The high-speed bus interface on the backplane is a male or female socket. Correspondingly, the high-speed bus interface on the main card is a female or male socket, so as to ensure that the high-speed bus interface on the backplane can be adapted to the high-speed bus interface on the main card, and realize a reliable electrical connection between the high-speed bus on the backplane and the high-speed bus on the main card.
[0079] Exemplarily, the high-speed bus is a PCIe bus; the low-speed bus is an SPI bus or an I2C bus. For the Inter-Integrated Circuit (I2C) internal bus of an integrated circuit, I2C is a multi-master serial communication protocol, which is often used to connect low-speed peripheral device chips. For the Serial Peripheral Interface (SPI), SPI is a full-duplex, synchronous communication protocol, which is mainly used for short-distance communication.
[0080] A group of low-speed bus pins is connected to a daughter card interface. Correspondingly, the daughter card interface is also configured with a group of low-speed bus pins.
[0081] Each group of high-speed bus pins obtained after expansion is connected to a daughter card interface. Correspondingly, the daughter card interface is also configured with a group of high-speed bus pins.
[0082] One or more high-speed bus switching chips can be configured on the bus expansion board, and the number of high-speed bus switching chips can be determined according to the processing capacity of the high-speed bus switching chips and the number of daughter card interfaces.
[0083] If the main control chip is configured with multiple high-speed buses and there is one high-speed bus switching chip configured on the bus expansion board, then the multiple high-speed buses on the main control chip are connected to the same high-speed bus switching chip on the bus expansion board via the high-speed bus interface. If the main control chip is configured with multiple high-speed buses and there are multiple high-speed bus switching chips configured on the bus expansion board, then for any two high-speed buses on the main control chip, these two high-speed buses can be connected to the same high-speed bus switching chip on the bus expansion board via the high-speed bus interface, and these two high-speed buses can also be connected to different high-speed bus switching chips on the bus expansion board via the high-speed bus interface.
[0084] For example, the number of high-speed bus lines supported by the main control chip is 2, and the number of daughter card interfaces is 8. In this case, it is necessary to expand 2 high-speed bus lines into 8 high-speed bus lines. If the processing capacity of a high-speed bus switching chip can meet the requirement of expanding 2 high-speed bus lines into 8 high-speed bus lines, then one high-speed bus switching chip can be configured on the bus expansion board, and the 2 high-speed bus lines on the main control chip are connected to the same high-speed bus switching chip on the bus expansion board via the high-speed bus interface.
[0085] Another example, the number of high-speed bus lines supported by the main control chip is 2, and the number of daughter card interfaces is 10. In this case, it is necessary to expand 2 high-speed bus lines into 10 high-speed bus lines. If the processing capacity of a high-speed bus switching chip cannot meet the requirement of expanding 2 high-speed bus lines into 10 high-speed bus lines, then 2 high-speed bus switching chips can be configured on the bus expansion board, and the 2 high-speed bus lines on the main control chip are connected to different high-speed bus switching chips on the bus expansion board via the high-speed bus interface. Each high-speed bus switching chip expands 1 high-speed bus line into 5 high-speed bus lines.
[0086] The bus expansion interface is at least configured with n + m groups of high-speed bus pins. n represents the number of high-speed bus lines supported by the main control chip. Correspondingly, the high-speed bus interface is configured with n groups of high-speed bus pins. m represents the number of daughter card interfaces, that is, how many groups of high-speed bus pins are obtained after expansion by the high-speed bus switching chip on the bus expansion board, and n < m.
[0087] Exemplarily, as Figure 3 shown, the bus expansion interface includes a high-speed snap connector male seat 1 (that is, the first high-speed snap connector of the bus expansion interface) and a high-speed snap connector male seat 2 (that is, the second high-speed snap connector of the bus expansion interface). The high-speed snap connector male seat 1 is configured with n groups of high-speed bus pins, and the high-speed snap connector male seat 2 is configured with m groups of high-speed bus pins. Correspondingly, as Figure 3 shown, the bus expansion board includes a high-speed snap connector female seat 1 (that is, the first high-speed snap connector of the bus expansion board) and a high-speed snap connector female seat 2 (that is, the second high-speed snap connector of the bus expansion board). The high-speed snap connector female seat 1 is configured with n groups of high-speed bus pins, and the high-speed snap connector female seat 2 is configured with m groups of high-speed bus pins.
[0088] The high-speed bus interface is connected to the high-speed bus switching chip on the bus expansion board through n groups of high-speed bus pins (which can be used to transmit n high-speed bus signals) in the bus expansion interface, as Figure 3As shown, the first high-speed bus is connected to the high-speed bus switching chip 1, and the nth high-speed bus is connected to the high-speed bus switching chip 2. For the bus between the first high-speed bus and the nth high-speed bus, it can be connected to the high-speed bus switching chip 1 and the high-speed bus switching chip 2 in an evenly divided manner, so that each group of high-speed bus pins in the high-speed bus interface is connected to a high-speed bus switching chip. Through the expansion of the high-speed bus switching chip on the bus expansion board, the n high-speed buses are expanded into m high-speed buses. The m high-speed buses are connected to the daughter card interface on the backplane through m groups of high-speed bus pins (such as Figure 3 shown, the m groups of high-speed bus pins in the female high-speed snap connector 2). The number of high-speed buses obtained after expansion is equal to the number of daughter card interfaces, so that each group of high-speed bus pins in the multiple groups of high-speed bus pins obtained after expansion is connected to a daughter card interface.
[0089] For the high-speed bus switching chip, it can be a chip with a switch function in the corresponding bus architecture, and it can route and manage data between multiple devices. A high-speed bus signal on the main card is transmitted to the high-speed bus switching chip through a group of high-speed bus pins in the high-speed bus interface. The high-speed bus switching chip can route a high-speed bus signal transmitted from the main card to multiple high-speed buses, so as to expand a group of high-speed bus pins (corresponding to a high-speed bus on the main card) into multiple groups of high-speed bus pins (corresponding to the multiple high-speed buses routed to).
[0090] For example, when the high-speed bus is a PCIe bus, the high-speed bus switching chip can be a PCIe SWITCH chip. The PCIe SWITCH chip is a "PCIe switching chip". Here, "PCIe" is the abbreviation of "Peripheral Component Interconnect Express" (peripheral component interconnect express), and "SWITCH" represents the function of a switch. The "PCIe switching chip" is a chip with a switch function used in the PCI Express bus architecture, and it can route and manage data between multiple devices.
[0091] Optionally, a main control chip is placed in the main control chip slot, and the main control chip is configured with a low-speed bus, and the low-speed bus of the main control chip is connected to the low-speed bus interface.
[0092] Optionally, a main control chip is placed in the main control chip slot, and the main control chip is configured with a high-speed bus, and the high-speed bus of the main control chip is connected to the high-speed bus interface. Exemplarily, as Figure 4 shown, the main control chip is configured with n high-speed buses, and n can be equal to 1 or 2, etc.
[0093] Optionally, the main control chip can be configured with both a high-speed bus and a low-speed bus. In this case, the low-speed bus of the main control chip is connected to the low-speed bus interface, and the high-speed bus of the main control chip is connected to the high-speed bus interface.
[0094] Exemplarily, the main control chip is an FPGA or an MCU.
[0095] It can be understood that when communicating between the main card and the sub-card using a low-speed bus, a main control chip that supports the low-speed bus can be installed in the main control chip slot. The low-speed bus of the main control chip is connected to the sub-card interface through the low-speed bus interface. The main control chip can be equipped with multiple low-speed buses. Assuming the number of sub-card interfaces is m and the main control chip is configured with k×m low-speed buses (k is an integer greater than or equal to 2), k low-speed buses are in a group. A group of low-speed buses is connected to the corresponding sub-card interface through a group of low-speed bus pins (for transmitting k low-speed bus signals) in the low-speed bus interface, so that each group of low-speed buses on the main control chip can be connected to the corresponding sub-card interface.
[0096] It should be noted that the communication rate of 1 low-speed bus is limited. By connecting a group of low-speed buses on the main control chip to the corresponding sub-card interface, the communication rate between the main control chip and the sub-card can be improved, and the communication efficiency can be effectively improved when communicating using a low-speed bus.
[0097] When communicating between the main card and the sub-card using a high-speed bus, a main control chip that supports the high-speed bus can be installed in the main control chip slot, and a bus expansion board can be plugged into the bus expansion interface on the backplane. The main control chip can be equipped with one or multiple high-speed buses. Assuming the main control chip is configured with n high-speed buses and the number of sub-card interfaces is m, the n high-speed buses of the main control chip pass through the high-speed bus interface and are expanded by the high-speed bus switching chip of the bus expansion board. After expansion, m high-speed buses are obtained. The m high-speed buses are connected to m sub-card interfaces through m groups of high-speed bus pins, which can establish a communication connection that supports the high-speed bus standard between the main control chip and m sub-cards when the number of high-speed buses n of the main control chip is less than the number of sub-cards m.
[0098] When communicating between the main card and a part of the sub-cards (assuming the number of this part of sub-cards is m 1 ) using a low-speed bus, and communicating between the main card and another part of the sub-cards (assuming the number of this part of sub-cards is m 2 ) using a high-speed bus, a main control chip that supports both the low-speed bus and the high-speed bus can be installed in the main control chip slot. The main control chip is configured with k×m 1The low-speed bus. k low-speed buses form a group. A group of low-speed buses is connected to the corresponding daughter card interface through a group of low-speed bus pins in the low-speed bus interface (for transmitting k low-speed bus signals), and this daughter card interface is docked with one of the above-mentioned m 1 daughter cards; the main control chip is also configured with n high-speed buses. The n high-speed buses of the main control chip pass through the high-speed bus interface and are expanded by the high-speed bus switching chip of the bus expansion board. After expansion, m 2 high-speed buses are obtained. The m 2 high-speed buses are connected to m 2 groups of high-speed bus pins and m 2 daughter card interfaces (this daughter card interface is docked with one of the above-mentioned m 2 daughter cards).
[0099] Therefore, the board card provided by the embodiment of the present application can support communication between the main card and the daughter card using low-speed buses and / or high-speed buses, realizing compatibility with multiple bus communication scenarios. The board card can adapt to different types of daughter cards and has strong scalability.
[0100] In a possible implementation manner, the main card includes a main control chip carrier board and a low-speed bus interface board;
[0101] As Figure 4 shown, the main control chip carrier board is configured with a main control chip slot, a high-speed bus interface for docking with the backplane, and a low-speed bus slot for carrying the low-speed bus interface board in a stacked manner (a slot supporting the transmission of low-speed bus signals);
[0102] As Figure 4 shown, the low-speed bus interface board is configured with a low-speed bus interface for docking with the backplane. The low-speed bus interface board is also configured with a low-speed snap connector, and the low-speed snap connector can be snapped with the low-speed bus slot;
[0103] As Figure 4 shown, the main control chip slot is connected to the low-speed bus interface through the low-speed bus slot, and the main control chip slot is connected to the high-speed bus interface.
[0104] It can be understood that in the prior art, since the main card of the PG can only be applicable to high-speed bus communication scenarios or low-speed bus communication scenarios, generally only an interface for a high-speed bus or an interface for a low-speed bus is provided on the main card. However, in the embodiments of the present application, the main card is not only configured with a low-speed bus interface but also a high-speed bus interface. Configuring two types of bus interfaces on one main card will cause an increase in the size of the board. In order to effectively control the size of the board, the main card is configured as a main control chip carrier board and a low-speed bus interface board. The low-speed bus interface board is plugged into the main control chip carrier board through a low-speed bus slot. The main control chip carrier board and the low-speed bus interface board can be assembled in a stacked manner, avoiding placing the low-speed bus interface and the high-speed bus interface on one plane, and effectively reducing the size (area) of the main card.
[0105] It should be noted that compared with the high-speed bus, the low-speed bus has a lower requirement for impedance continuity. Therefore, leading the low-speed bus to the backplane through the low-speed bus interface board has less impact on the signal quality on the low-speed bus.
[0106] In a possible implementation, the low-speed bus interface is configured with multiple pins for transmitting slot status signals, and / or the high-speed bus interface is configured with multiple pins for transmitting slot status signals;
[0107] On the backplane, a pin for transmitting a slot status signal is correspondingly connected to a slot status signal pin of a daughter card interface to receive the slot status signal sent by the daughter card (this signal is used to indicate that a daughter card is plugged into the daughter card interface);
[0108] On the main card, each pin for transmitting a slot status signal is connected to the main control chip slot.
[0109] As Figure 3 shown, a pin for transmitting a slot status signal is connected to a daughter card interface. Correspondingly, the daughter card interface is also configured with a pin for transmitting a slot signal, that is, Figure 3 the slot status signal pin in
[0110] It can be understood that when the daughter card is plugged into the daughter card interface, the daughter card will send a slot status signal through the corresponding pin (the pin for transmitting the slot status signal) on the daughter card interface. Then, the slot status signal is transmitted to the main control chip via the low-speed bus interface or the high-speed bus interface. Then, the main control chip can know whether a daughter card is plugged into each daughter card interface and can perform corresponding operations when detecting the slot status signal, such as reporting a plug-in event message (indicating an event that a daughter card is plugged into the daughter card interface) to the upper computer, realizing efficient monitoring of the slot status of the daughter card interface.
[0111] In a possible implementation, the low-speed bus interface is configured with multiple pins for transmitting synchronization signals, and / or the high-speed bus interface is configured with multiple pins for transmitting synchronization signals;
[0112] On the backplane, a pin for transmitting a synchronization signal is correspondingly connected to a synchronization signal pin of a daughter card interface;
[0113] On the main card, each pin for transmitting a synchronization signal is connected to a main control chip slot.
[0114] As Figure 3 shown, a pin for transmitting a synchronization signal is connected to a daughter card interface. Correspondingly, the daughter card interface is also configured with a pin for transmitting a synchronization signal, that is, Figure 3 the synchronization signal pin in
[0115] It can be understood that during the communication between the main card and multiple daughter cards, it may be necessary to maintain the synchronization of the communication between the main card and multiple daughter cards. To meet the requirements of this service scenario, the main card transmits synchronization signals to each daughter card through the corresponding pins (pins for transmitting synchronization signals) on the low-speed bus interface or high-speed bus interface configuration, so as to achieve communication synchronization between the main card and multiple daughter cards.
[0116] Optionally, as Figure 3 shown, the daughter card interface is configured with power pins for supplying power to the daughter card.
[0117] In a possible implementation, on the backplane, the low-speed bus interface and the high-speed bus interface adopt the same high-speed bus connector (a connector suitable for transmitting high-speed bus signals, such as a PCIe slot, an ADF connector, or an HM connector, etc.);
[0118] On the main card, the low-speed bus interface and the high-speed bus interface adopt the same high-speed bus connector;
[0119] The high-speed bus connector on the backplane is a male connector or a female connector. Correspondingly, the high-speed bus connector on the main card is a female connector or a male connector.
[0120] It should be noted that in the prior art, generally different types of connectors are configured for the low-speed bus interface and the high-speed bus interface. For example, in the case where the low-speed bus and the high-speed bus are an SPI bus and a PCIe bus respectively, the SPI bus interface is configured as a plug-in connector (such as a Header connector), and the PCIe bus interface is configured as a PCIe slot.
[0121] In the board card provided in the embodiment of the present application, a low-speed bus interface and a high-speed bus interface are configured on the main card, and a low-speed bus interface and a high-speed bus interface are also configured on the backplane. If different types of connectors are used for the low-speed bus interface and the high-speed bus interface, then during the process of plugging the main card onto the backplane or unplugging the main card from the backplane, the forces on the low-speed bus interface and the high-speed bus interface are different, and the forces on different interfaces are uneven, resulting in a shortened service life of the interfaces.
[0122] To overcome the defect of uneven forces between interfaces, the low-speed bus interface and the high-speed bus interface can be configured with the same high-speed bus connector. For example, when the high-speed bus is a PCIe bus, the high-speed bus connector can include an ADF connector and an HM connector. The ADF connector is used to transmit bus signals, and the HM connector is used to transmit other signals (such as synchronization signals or slot status signals, etc.).
[0123] The HM connector, also known as the Hard Metric connector, is usually used in industrial applications, especially related to the PCI bus standard of computers. The centerline pitch of the HM connector is generally 2mm and can be used for board-to-board connections.
[0124] The ADF (Advanced Differential Fabric) connector is a high-speed differential connector that can support high-speed data transmission and has a high-density signal line layout.
[0125] Since the high-speed bus connector can adapt to transmit high-speed bus signals, the high-speed bus connector can be compatible with transmitting low-speed bus signals. Thus, during the process of plugging the main card onto the backplane or unplugging the main card from the backplane, because the low-speed bus interface and the high-speed bus interface use the same high-speed bus connector, the number of pins, the pin size, and the pin arrangement of the low-speed bus interface are the same as those of the high-speed bus interface. The forces on the low-speed bus interface and the high-speed bus interface are the same, and the forces on different interfaces are uniform, effectively preventing the uneven forces between different interfaces from shortening the service life of the interfaces.
[0126] In addition, configuring the low-speed bus interface and the high-speed bus interface with the same high-speed bus connector can unify the interface types between the main card and the backplane, improving production and maintenance efficiency.
[0127] The present application also provides a signal generator, including: a daughter card and any one of the above circuit board cards. The number of daughter cards in the signal generator can be one or more, and the daughter cards are plugged into the daughter card interfaces of the circuit board card. The signal generator can specifically be an image generator (PG) or a semiconductor test device.
[0128] It should be understood that expressions such as "comprising" and "may comprise" that can be used in this application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In this application, terms such as "comprising" and / or "having" can be interpreted as indicating specific characteristics, numbers, operations, constituent elements, components, or combinations thereof, but cannot be interpreted as excluding the existence or possibility of addition of one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.
[0129] In addition, in the embodiments of this application, mathematical concepts such as symmetry, equality, parallelism, and perpendicularity are mentioned. These definitions are all in view of the current technological level, rather than the absolutely strict definitions in the mathematical sense. A small deviation is allowed, and being approximately symmetric, approximately equal, approximately parallel, approximately perpendicular, etc. are all acceptable. For example, when it is said that A is parallel to B, it means that A is parallel to B or approximately parallel to B, and the included angle between A and B can be between 0 degrees and 10 degrees. When it is said that A is perpendicular to B, it means that A is perpendicular to B or approximately perpendicular to B, and the included angle between A and B can be between 80 degrees and 100 degrees.
[0130] As described above, the above are only specific embodiments of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed in this application can easily think of changes or substitutions, and all should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.
Claims
1. A circuit board card, characterized in that: include: Main card and back panel; The backplane is configured with a low-speed bus interface for docking the main card, a high-speed bus interface for docking the main card, and a plurality of sub-card interfaces; The main card is configured with a low-speed bus interface for docking with the backplane and a high-speed bus interface for docking with the backplane; The low-speed bus interface is correspondingly connected to the low-speed bus pins in the plurality of daughter card interfaces; The high-speed bus interface is connected to the high-speed bus pins in the plurality of daughter card interfaces through a bus expansion module.
2. The circuit board card according to claim 1, characterized in that: The backplane is provided with a bus expansion interface for docking with a bus expansion board, and the bus expansion module is specifically the bus expansion board; In the case where the main card and the daughter card communicate using a high-speed bus, a bus expansion board is plugged into the bus expansion interface, and the high-speed bus interface is connected to the high-speed bus pins in the plurality of daughter card interfaces through the bus expansion board.
3. The circuit board card according to claim 2, characterized in that: The low-speed bus interface is configured with multiple groups of low-speed bus pins, and a group of low-speed bus pins in the low-speed bus interface is correspondingly connected to a group of low-speed bus pins in a daughter card interface; The bus extension interface is configured with multiple groups of high-speed bus pins, and a group of high-speed bus pins in a daughter card interface corresponds to a group of high-speed bus pins in the bus extension interface; The high-speed bus interface is configured with at least one group of high-speed bus pins, and a group of high-speed bus pins in the high-speed bus interface corresponds to a group of high-speed bus pins in the bus extension interface.
4. The circuit board card according to claim 3, characterized in that: The bus expansion board is configured with at least one high-speed bus switching chip. The same group of high-speed bus pins in the high-speed bus interface are connected to the same high-speed bus switching chip. The high-speed bus switching chip is used to expand each group of high-speed bus pins in the high-speed bus interface into multiple groups of high-speed bus pins. Each group of high-speed bus pins in the multiple groups of high-speed bus pins obtained after expansion corresponds to a group of high-speed bus pins in a daughter card interface.
5. The circuit board card according to claim 4, characterized in that: The bus expansion interface and the bus expansion board are provided with a first high-speed buckle connector, and each group of high-speed bus pins in the high-speed bus interface of the backplane is connected to the high-speed bus switching chip through the first high-speed buckle connector; The bus expansion interface and the bus expansion board are provided with a second high-speed snap-on connector, and the high-speed bus pins in each daughter card interface are connected to the high-speed bus switching chip through the second high-speed snap-on connector.
6. The circuit board card according to claim 1, characterized in that: The main card is configured with a main control chip slot, the main control chip slot is connected to the low-speed bus interface of the main card, and the main control chip slot is connected to the high-speed bus interface of the main card.
7. The circuit board card according to claim 6, characterized in that: The main card includes: a main control chip carrier board and a low-speed bus interface board; The main control chip carrier is configured with a main control chip slot, a high-speed bus interface for docking with a backplane, and a low-speed bus slot for carrying the low-speed bus interface board in a stacked manner; The low-speed bus interface board is provided with a low-speed bus interface for docking with a backplane; The main control chip slot is connected to the low-speed bus interface through the low-speed bus slot, and the main control chip slot is connected to the high-speed bus interface.
8. The circuit board card according to claim 6, characterized in that: The low-speed bus interface is configured with a plurality of pins for transmitting slot status signals, and / or the high-speed bus interface is configured with a plurality of pins for transmitting slot status signals; On the backplane, a pin for transmitting a slot status signal is correspondingly connected to a slot status signal pin of a daughter card interface to receive the slot status signal sent by the daughter card; On the main card, each pin for transmitting a slot status signal is connected to the main control chip slot.
9. The circuit board card according to claim 6, characterized in that: The low-speed bus interface is configured with a plurality of pins for transmitting synchronization signals, and / or the high-speed bus interface is configured with a plurality of pins for transmitting synchronization signals; On the backplane, a pin for transmitting a synchronization signal is connected correspondingly to a synchronization signal pin of a daughter card interface; On the main card, each pin for transmitting a synchronization signal is connected to a main control chip slot.
10. A signal generator, characterized in that: include: A daughter card and a circuit board card as claimed in any one of claims 1 to 9.