Battery management controller

Abstract

The utility model relates to a battery management controller, relates to the technical field of automobiles, and protects a control chip by additionally arranging a voltage stabilizing circuit to suppress transient voltage of a power supply port. The battery management controller comprises a control chip and N interface circuits; the control chip comprises N groups of input ends, and one group of input ends comprises a first input end and a second input end. The input end of the interface circuit is electrically connected with the power supply end, the interface circuit comprises a first output end and a second output end, and the first output end and the second output end of the interface circuit are correspondingly and electrically connected with the first input end and the second input end of the group of input ends of the control chip respectively; n > = 2. The interface circuits comprise voltage stabilizing circuits, except the Nth interface circuit, the first end of the voltage stabilizing circuit of the Mth interface circuit in the N interface circuits is electrically connected with the first output end of the Mth interface circuit, the second end of the voltage stabilizing circuit of the Mth interface circuit is electrically connected with the first output end of the (M + 1) th interface circuit, and M is larger than or equal to 1 and smaller than N.

Description

Technical Field

[0001] The present application relates to the automotive field, in particular to the automotive battery protection technology field, and specifically to a battery management controller. Background Art

[0002] The AFE chip of the current battery management controller uses the ADBMS6815_ADI chip. The ADBMS6815_ADI is a multi-cell battery stack monitor produced by Analog Devices Inc., capable of measuring up to 12 series-connected battery cells. It has a battery measurement range of 0V to 5V and is suitable for most battery chemistry applications.

[0003] Inside the ADBMS6815_ADI chip, the ESD protection between Cn / Sn / V+ / V- is intricate, with many circuits and a low withstand voltage. The action of hot plugging will generate heat instantly, but it cannot dissipate, causing the Zener diode inside the chip to break down and burn, resulting in a pin short circuit. Utility Model Content

[0004] The present application provides a battery management controller, which protects the control chip by adding a voltage stabilization circuit and a protection circuit to suppress the transient voltage of the power supply port. The technical solution of the present application is as follows:

[0005] According to the first aspect of the present application, a battery management controller is provided, the battery management controller comprising: a control chip and N interface circuits; the control chip comprises N groups of input terminals, one group of input terminals comprises a first input terminal and a second input terminal. The input terminal of the interface circuit is electrically connected to the power supply terminal, the interface circuit comprises a first output terminal and a second output terminal, the first output terminal and the second output terminal of the interface circuit are respectively electrically connected to the first input terminal and the second input terminal of a group of input terminals of the control chip; N≥2.

[0006] The interface circuit includes: a voltage stabilizing circuit, except for the Nth interface circuit, a first end of the voltage stabilizing circuit of the Mth interface circuit among the N interface circuits is electrically connected to a first output end of the Mth interface circuit, and a second end of the voltage stabilizing circuit of the Mth interface circuit is electrically connected to a first output end of the M+1th interface circuit, 1≤M<N.

[0007] Based on the above technical means, the present application provides a battery management controller, which suppresses the transient high voltage generated during hot plugging by adding a voltage stabilizing circuit, prevents the transient high voltage from entering the control chip, and protects the control chip.

[0008] In a possible implementation, the voltage stabilizing circuit includes: a first voltage stabilizing diode; a first end of the first voltage stabilizing diode is electrically connected to a first end of the voltage stabilizing circuit, and a second end of the first voltage stabilizing diode is electrically connected to a second end of the voltage stabilizing circuit.

[0009] According to the above technical means, the first voltage stabilizing diode in the present application can clamp the transient high voltage within the rated range of the control chip to prevent damage to the control chip.

[0010] In a possible implementation, the interface circuit further includes: an energy storage circuit; a first end of the energy storage circuit is electrically connected to the input end of the interface circuit, and a second end of the energy storage circuit is electrically connected to the ground end.

[0011] According to the above technical means, in the present application, part of the electric energy is stored in the energy storage circuit so that the interface circuit can still work for a period of time after the power is cut off.

[0012] In a possible implementation, the energy storage circuit includes: a first capacitor and a second capacitor; the first end of the first capacitor is electrically connected to the first end of the energy storage circuit, the second end of the first capacitor is electrically connected to the first end of the second capacitor, and the second end of the second capacitor is electrically connected to the second end of the energy storage circuit.

[0013] According to the above technical means, the energy storage circuit mainly stores electric energy in the first capacitor and the second capacitor. The first capacitor and the second capacitor have larger capacitance values ​​and can store more electric energy.

[0014] In a possible implementation, the interface circuit further includes: a protection circuit; a first end of the protection circuit is electrically connected to the first output end of the interface circuit, and a second end of the protection circuit is electrically connected to the second output end of the interface circuit.

[0015] According to the above technical means, the energy storage circuit in the present application will generate a large current at the moment of charging, and the large current will break down the diode inside the control chip, causing circuit damage. The protection circuit is used to share the current of the diode inside the control chip, thereby protecting the control chip.

[0016] In a possible implementation, the protection circuit includes: a first diode; a first end of the first diode is electrically connected to a first end of the protection circuit, and a second end of the first diode is electrically connected to a second end of the protection circuit.

[0017] According to the above technical means, the parameters of the first diode in the present application are higher than the parameters of the diode inside the control chip, thereby achieving the purpose of protecting the control chip.

[0018] In a possible implementation, the interface circuit further includes: a first filter circuit; a first end of the first filter circuit is electrically connected to the first output end of the interface circuit, and a second end of the first filter circuit is electrically connected to the ground end.

[0019] According to the above technical means, the first filter circuit is configured to filter out or prevent the current of a specific frequency from passing through when the interface circuit is working, so as to reduce or eliminate unnecessary noise or interference.

[0020] In a possible implementation, the first filtering circuit includes: a third capacitor and a fourth capacitor; the first end of the third capacitor is electrically connected to the first end of the filtering circuit, the second end of the third capacitor is electrically connected to the first end of the fourth capacitor, and the second end of the fourth capacitor is electrically connected to the second end of the first filtering circuit.

[0021] According to the above technical means, the third capacitor and the fourth capacitor in the present application have relatively small capacitance values ​​and are suitable as filter capacitors for reducing noise and interference in the power supply.

[0022] In a possible implementation, the interface circuit further includes: a first resistor, a second resistor, a third resistor and a fourth resistor; the first end of the first resistor is electrically connected to the input end of the interface circuit and is also electrically connected to the first end of the energy storage circuit; the second end of the first resistor is electrically connected to the first end of the second resistor and is also electrically connected to the first end of the third resistor; the second end of the second resistor is electrically connected to the first end of the fourth resistor and is also electrically connected to the first end of the filter circuit; the second end of the third resistor is electrically connected to the second output end of the interface circuit; and the second end of the fourth resistor is electrically connected to the first output end of the interface circuit.

[0023] According to the above technical means, the multiple resistors in the present application can play a role in current limiting to prevent large currents from damaging the control chip.

[0024] In a possible embodiment, the battery management controller also includes: a second filtering circuit; the second filtering circuit includes N+1 filtering sub-circuits, the first end of the first filtering sub-circuit is electrically connected to the first voltage end, and the second end of the first filtering sub-circuit is electrically connected to the second output end of the first interface circuit; the first end of the N+1th filtering sub-circuit is electrically connected to the second output end of the Nth interface circuit, and the second end of the N+1th filtering sub-circuit is electrically connected to the second voltage end.

[0025] Except for the first filter sub-circuit and the (N+1)th filter sub-circuit, the first end and the second end of the remaining filter sub-circuits are electrically connected between the second output ends of two adjacent interface circuits.

[0026] According to the above technical means, the filtering subcircuit in the second filtering circuit in the present application can be composed of at least one capacitor, so as to achieve the functions of filtering and preventing voltage mutations.

[0027] Therefore, the above technical features of the present application have the following beneficial effects:

[0028] (1) The voltage stabilization circuit added in the present application suppresses the transient high voltage generated during hot plugging, prevents the transient high voltage from entering the control chip, and protects the control chip.

[0029] (2) In the present application, a protection circuit is added to share the current of the diode inside the control chip when a large current is generated at the moment of charging of the energy storage circuit, thereby protecting the control chip.

[0030] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application, and do not constitute an improper limitation on the present application.

[0032] Figure 1 is an internal circuit diagram of an ADBMS6815_ADI chip according to an exemplary embodiment;

[0033] Figure 2 is a structural schematic diagram of a battery management controller according to an exemplary embodiment;

[0034] Figure 3 is a voltage waveform diagram between two adjacent first input terminals of a control chip before modification of an interface circuit according to an exemplary embodiment;

[0035] Figure 4 is a voltage waveform diagram between two adjacent first input terminals of a control chip after a modified interface circuit according to an exemplary embodiment;

[0036] Figure 5 is a schematic diagram of an interface circuit according to an exemplary embodiment;

[0037] Figure 6 is a voltage waveform diagram between two input terminals of a control chip before modification of an interface circuit according to an exemplary embodiment;

[0038] Figure 7 The figure is a voltage waveform diagram between two input terminals of a control chip after a modified interface circuit according to an exemplary embodiment. DETAILED DESCRIPTION

[0039] In order to enable ordinary persons in the art to better understand the technical solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0040] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims.

[0041] The AFE chip of the current battery management controller uses the ADBMS6815_ADI chip. The ADBMS6815_ADI is a multi-cell battery stack monitor produced by Analog Devices Inc., capable of measuring up to 12 series-connected battery cells. It has a battery measurement range of 0V to 5V and is suitable for most battery chemistry applications.

[0042] Inside the ADBMS6815_ADI chip, the ESD protection between Cn / Sn / V+ / V- is complicated, with many circuits and a low withstand voltage. The action of hot plugging will generate heat instantly, but it cannot dissipate, causing the diode inside the chip to break down and burn, resulting in a pin short circuit.

[0043] Reference Figure 1 It can be seen that Figure 1 This is the internal circuit diagram of the ADBMS6815_ADI chip. C12 and S12 are a set of input terminals of the chip. During hot plugging, a large current will be generated, causing the diode between C12 and S12 to break down and burn, resulting in a pin short circuit.

[0044] It should be noted that the main function of the AFE chip is to convert the analog signals collected from the sensor into digital signals for pre-processing. These pre-processing include amplification, filtering, sampling and other work to ensure the quality and accuracy of the digital signal. In the battery management controller, the AFE chip mainly plays the role of monitoring and protecting the battery. During the charging and discharging process, the battery will generate various signals such as voltage, current, temperature, etc. The AFE chip can collect, process and analyze these signals to achieve battery monitoring and protection.

[0045] Based on this, the present application provides a battery management controller. Figure 2 As shown, the battery management controller 1000 includes: a control chip 100 and N interface circuits 200 .

[0046] The control chip 100 includes: N groups of input terminals, one group of input terminals includes a first input terminal C and a second input terminal S.

[0047] Reference Figure 2 The input terminal 2000 of the interface circuit 200 is electrically connected to the power supply terminal B, and the interface circuit 200 includes: a first output terminal 2001 and a second output terminal 2002.

[0048] The first output terminal 2001 and the second output terminal 2002 of the interface circuit are electrically connected to the first input terminal C and the second input terminal S of a group of input terminals of the control chip respectively; N≥2.

[0049] In some embodiments, reference Figure 1 and Figure 5 It can be seen that C0 and S0 are a group of input terminals, C1 and S1 are a group of input terminals, and CN and SN are a group of input terminals. The power supply terminal B includes: a first power supply terminal B0, a second power supply terminal B1, and so on to the Nth power supply terminal.

[0050] Among them, the first power supply terminal B0 is connected to the input terminal of the group of C0 and S0, that is, the input terminal 2000 of the first interface circuit 200 is electrically connected to the first power supply terminal B0, the first output terminal 2001 of the first interface circuit 200 is electrically connected to the first first input terminal C0, and the second output terminal 2002 of the first interface circuit 200 is electrically connected to the first second input terminal S0. Similarly, the Nth power supply terminal BN is connected to the input terminal of the group of CN and SN, which will not be repeated here.

[0051] The interface circuit 200 includes: a voltage stabilizing circuit 1. The voltage stabilizing circuit 1 includes: a first terminal 101 and a second terminal 102.

[0052] Except for the Nth interface circuit 200, the first end 101 of the voltage stabilizing circuit 1 of the Mth interface circuit 200 among the N interface circuits 200 is electrically connected to the first output end of the Mth interface circuit, and the second end of the voltage stabilizing circuit of the Mth interface circuit is electrically connected to the first output end of the M+1th interface circuit, 1≤M<N.

[0053] For example, N=13, M=3; the first end 101 of the voltage stabilizing circuit 1 of the third interface circuit 200 among the 13 interface circuits 200 is electrically connected to the first output end 2001 of the third interface circuit, and the second end 102 of the voltage stabilizing circuit 1 of the third interface circuit 200 is electrically connected to the first output end 2001 of the fourth interface circuit 200.

[0054] For the 13th interface circuit 200, the first terminal 101 of the voltage stabilizing circuit 1 of the 13th interface circuit 200 is electrically connected to the first output terminal 2001 of the 13th interface circuit, and the second terminal 102 of the voltage stabilizing circuit 1 of the 13th interface circuit 200 is electrically connected to the remaining circuits. The remaining circuits may be circuits that generate high voltages, so that the high voltages can be suppressed by the voltage stabilizing circuit in the 13th interface circuit 200.

[0055] Reference Figure 3 It can be seen that Figure 3 The voltage waveform between two adjacent first input terminals of the control chip before the interface circuit is modified. When hot plugging, an uncertain voltage will be generated. Figure 3 The sudden voltage in the circuit is an uncertain voltage, which will exceed the rated voltage of the control chip and thus damage the circuit structure inside the chip.

[0056] Reference Figure 4 It can be seen that after the above-mentioned voltage stabilizing circuit 1 is added to the interface circuit 200, the maximum voltage value of the voltage stabilizing circuit is set to be lower than the rated voltage of the control chip. Then, after the high voltage passes through the voltage stabilizing circuit 1, the voltage stabilizing circuit will clamp the high voltage below the rated voltage of the control chip, thereby achieving the purpose of protecting the control chip.

[0057] For example, refer to Figure 3 and Figure 4 Without adding a voltage stabilizing circuit, the voltage between the two adjacent first input terminals Cn and Cn-1 of the control chip will reach 12 V. Among them, the rated voltage value of the control chip is -0.3V to +8V, that is, when the voltage between the two adjacent first input terminals Cn and Cn-1 of the control chip is between -0.3V and +8V, the control chip is safe and will not be damaged.

[0058] and Figure 3 The voltage between two adjacent first input terminals Cn and Cn-1 of the control chip in the circuit will reach 12V, which exceeds the rated voltage value of the control chip, thereby causing damage to the control chip. Figure 4 After the voltage stabilizing circuit 1 is added, the maximum voltage between the two adjacent first input terminals Cn and Cn-1 of the control chip is 6.2V, which meets the rated voltage value of the control chip of -0.3V to +8V. Therefore, the voltage stabilizing circuit can protect the control chip during hot plugging.

[0059] It should be noted that Figure 3 and Figure 4 This is the waveform diagram of the oscilloscope test. Figure 4 relatively Figure 3 , it is obvious that the waveform is relatively flat.

[0060] In summary, the present application provides a battery management controller, which suppresses the transient high voltage generated during hot plugging by adding a voltage stabilizing circuit, prevents the transient high voltage from entering the control chip, and protects the control chip.

[0061] like Figure 5As shown, the voltage stabilizing circuit 1 includes: a first voltage stabilizing diode D1; a first end of the first voltage stabilizing diode D1 is electrically connected to a first end 101 of the voltage stabilizing circuit 1, and a second end of the first voltage stabilizing diode D1 is electrically connected to a second end 102 of the voltage stabilizing circuit 1.

[0062] Among them, the Zener diode, also known as the Zener diode, is a semiconductor device that uses the phenomenon that when the PN junction is in reverse breakdown, its current can vary in a wide range while the voltage remains basically unchanged, thereby stabilizing the voltage. This diode has a very high resistance until the critical reverse breakdown voltage. After exceeding this critical point, the reverse resistance is reduced to a very small value. In this low resistance area, the current increases while the voltage remains constant. The working principle of the Zener diode is that before the reverse breakdown voltage, its operating current varies in a wide range while the voltage at both ends remains basically unchanged.

[0063] The voltage regulator diode has the unidirectional conductivity of ordinary diodes, which means that it can be tested by the forward and reverse resistance of the multimeter. In addition, the biggest difference between voltage regulator diodes and ordinary diodes is that they can keep the voltage stable under certain conditions, instead of working only within a fixed voltage range like ordinary diodes.

[0064] Zener diodes are widely used in various voltage stabilization circuits, voltage reference components, and other occasions. For example, in the battery management system (BMS) of new energy vehicles, Zener diodes can continue to work in a breakdown state to ensure the stability of the output voltage. In addition, Zener diodes are also commonly used in circuit design to provide a stable voltage and limit voltage fluctuations in the circuit.

[0065] In general, the Zener diode is an electronic component with advantages such as good stability, high reliability, and easy use, and is widely used in various electronic devices. When choosing a Zener diode, you need to choose the appropriate Zener diode model according to the specific application scenario and needs.

[0066] It should be noted that the first end of the first voltage stabilizing diode D1 is the cathode of the first voltage stabilizing diode D1, and the second end of the first voltage stabilizing diode D1 is the anode of the first voltage stabilizing diode D1. The cathode of the first voltage stabilizing diode D1 is electrically connected to the first end 101 of the voltage stabilizing circuit 1, and the anode of the first voltage stabilizing diode D1 is electrically connected to the second end 102 of the voltage stabilizing circuit 1.

[0067] like Figure 5 As shown, the interface circuit 200 further includes: an energy storage circuit 2. The energy storage circuit 2 includes: a first terminal 201 and a second terminal 202.

[0068] The first end 201 of the energy storage circuit 2 is electrically connected to the input end of the interface circuit 200, and the second end of the energy storage circuit 2 is electrically connected to the ground end GND.

[0069] In some embodiments, the energy storage circuit 2 includes: a first capacitor C1 and a second capacitor C2.

[0070] The first end of the first capacitor C1 is electrically connected to the first end 201 of the energy storage circuit 2 , the second end of the first capacitor C1 is electrically connected to the first end of the second capacitor C2 , and the second end of the second capacitor C2 is electrically connected to the second end 202 of the energy storage circuit 2 .

[0071] The energy storage circuit is configured to store part of the electrical energy in the energy storage circuit so that the interface circuit can still work for a period of time after the interface circuit is powered off.

[0072] In some embodiments, reference Figure 5 The interface circuit further includes: a plurality of second voltage stabilizing diodes D2; two ends of the second voltage stabilizing diodes D2 are connected between input ends of the Mth and M+2th interface circuits.

[0073] like Figure 5 As shown, the interface circuit 200 further includes: a protection circuit 3 ; the protection circuit 3 includes: a first terminal 301 and a second terminal 302 .

[0074] The first terminal 301 of the protection circuit 3 is electrically connected to the first output terminal 2001 of the interface circuit 200 , and the second terminal 302 of the protection circuit 3 is electrically connected to the second output terminal 2002 of the interface circuit 200 .

[0075] In some embodiments, the protection circuit 3 includes: a first diode D3; a first end of the first diode D3 is electrically connected to a first end of the protection circuit, and a second end of the first diode is electrically connected to a second end of the protection circuit.

[0076] It should be noted that the first end of the first diode D3 refers to the cathode of the first diode D3 , and the second end of the first diode D3 refers to the anode of the first diode D3 .

[0077] Reference Figure 1 , Figure 6 and Figure 7 , the insertion voltage between C12 and V+ can reach up to 7.8V ( Figure 6 ), and the overshoot voltage fluctuates greatly. The control chip withstands a voltage of 7.5V. Adding a first diode D3 between S12 and C12 can absorb the voltage between the power supply port V+ and C12, and protect the diode between S12 and C12 inside the chip.

[0078] It should be noted that from Figure 6 It can be seen that the voltage in the waveform diagram rises instantly at a certain moment, which is the overshoot voltage. Figure 7The waveform in is relatively gentle, indicating that the addition of the first diode D3 suppresses the overshoot voltage, thereby protecting the control chip from damage.

[0079] like Figure 5 As shown, the interface circuit 200 further includes: a first filtering circuit 4 ; the first filtering circuit 4 includes: a first end 401 and a second end 402 .

[0080] The first terminal 401 of the first filter circuit 4 is electrically connected to the first output terminal 2001 of the interface circuit 200 , and the second terminal 402 of the first filter circuit 4 is electrically connected to the ground terminal GND.

[0081] In some embodiments, the first filter circuit 4 includes: a third capacitor C3 and a fourth capacitor C4; the first end of the third capacitor C3 is electrically connected to the first end 401 of the first filter circuit 4, the second end of the third capacitor C3 is electrically connected to the first end of the fourth capacitor C4, and the second end of the fourth capacitor C4 is electrically connected to the second end 402 of the first filter circuit 4.

[0082] like Figure 5 As shown, the interface circuit 200 also includes: a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4; the first end of the first resistor R1 is electrically connected to the input end 2000 of the interface circuit 200, and is also electrically connected to the first end 201 of the energy storage circuit 2, the second end of the first resistor R1 is electrically connected to the first end of the second resistor R2, and is also electrically connected to the first end of the third resistor R3; the second end of the second resistor R2 is electrically connected to the first end of the fourth resistor R4, and is also electrically connected to the first end 401 of the first filter circuit 4; the second end of the third resistor R3 is electrically connected to the second output end 2002 of the interface circuit 200; the second end of the fourth resistor R4 is electrically connected to the first output end 2001 of the interface circuit 200.

[0083] The first resistor R1 , the second resistor R2 , the third resistor R3 and the fourth resistor R4 play a role in current limiting to prevent large current from damaging the control chip.

[0084] like Figure 5 As shown, the battery management controller 1000 further includes: a second filtering circuit 500 ; the second filtering circuit 500 includes N+1 filtering sub-circuits 50 .

[0085] A first terminal of the first filter sub-circuit 50 is electrically connected to the first voltage terminal VCC, and a second terminal of the first filter sub-circuit 50 is electrically connected to the second output terminal 2002 of the first interface circuit 200 .

[0086] A first end of the N+1th filter subcircuit is electrically connected to the second output end of the Nth interface circuit, and a second end of the N+1th filter subcircuit is electrically connected to the second voltage end.

[0087] Except for the first filter sub-circuit and the (N+1)th filter sub-circuit, the first end and the second end of the remaining filter sub-circuits are electrically connected between the second output ends of two adjacent interface circuits.

[0088] That is to say, except for the first filter sub-circuit and the last filter sub-circuit, the first end and the second end of the remaining filter sub-circuit are electrically connected between the second output ends of two adjacent interface circuits.

[0089] For example, N=12, the second filter circuit 500 includes 13 filter sub-circuits 50. A first terminal of the first filter sub-circuit 50 is electrically connected to the first voltage terminal VCC, and a second terminal of the first filter sub-circuit 50 is electrically connected to the second output terminal 2002 of the first interface circuit 200.

[0090] A first terminal of the 13th filter sub-circuit 50 is electrically connected to the second output terminal 2002 of the 12th interface circuit, and a second terminal of the 13th filter sub-circuit 50 is electrically connected to the second voltage terminal GND.

[0091] The first end and the second end of the second to twelfth filter sub-circuits 50 are electrically connected between the second output ends 2002 of two adjacent interface circuits 200 .

[0092] In some embodiments, the filter subcircuit 50 includes at least one filter capacitor Cx. The filter subcircuit in the second filter circuit may be composed of at least one capacitor, thereby achieving the functions of filtering and preventing voltage mutation.

[0093] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A battery management controller, characterized in that: The battery management controller comprises: A control chip; the control chip comprises N groups of input terminals, one group of input terminals comprises a first input terminal and a second input terminal; N interface circuits, the input end of the interface circuit is electrically connected to the power supply end, the interface circuit includes a first output end and a second output end, the first output end and the second output end of the interface circuit are respectively electrically connected to a first input end and a second input end of a group of input ends of the control chip; N≥2; The interface circuit comprises: A voltage stabilizing circuit, except for the Nth interface circuit, a first end of the voltage stabilizing circuit of the Mth interface circuit among the N interface circuits is electrically connected to a first output end of the Mth interface circuit, and a second end of the voltage stabilizing circuit of the Mth interface circuit is electrically connected to a first output end of the M+1th interface circuit, 1≤M<N.

2. The battery management controller according to claim 1, characterized in that: The voltage stabilizing circuit comprises: a first voltage stabilizing diode; The first end of the first voltage stabilizing diode is electrically connected to the first end of the voltage stabilizing circuit, and the second end of the first voltage stabilizing diode is electrically connected to the second end of the voltage stabilizing circuit.

3. The battery management controller according to claim 1 or 2, characterized in that: The interface circuit also includes: an energy storage circuit; The first end of the energy storage circuit is electrically connected to the input end of the interface circuit, and the second end of the energy storage circuit is electrically connected to the ground end.

4. The battery management controller according to claim 3, characterized in that: The energy storage circuit comprises: a first capacitor and a second capacitor; The first end of the first capacitor is electrically connected to the first end of the energy storage circuit, the second end of the first capacitor is electrically connected to the first end of the second capacitor, and the second end of the second capacitor is electrically connected to the second end of the energy storage circuit.

5. The battery management controller according to claim 4, characterized in that: The interface circuit also includes: a protection circuit; The first end of the protection circuit is electrically connected to the first output end of the interface circuit, and the second end of the protection circuit is electrically connected to the second output end of the interface circuit.

6. The battery management controller according to claim 5, characterized in that: The protection circuit comprises: a first diode; A first end of the first diode is electrically connected to a first end of the protection circuit, and a second end of the first diode is electrically connected to a second end of the protection circuit.

7. The battery management controller according to claim 1, characterized in that: The interface circuit further includes: a first filtering circuit; The first end of the first filter circuit is electrically connected to the first output end of the interface circuit, and the second end of the first filter circuit is electrically connected to the ground end.

8. The battery management controller according to claim 7, characterized in that: The first filtering circuit includes: a third capacitor and a fourth capacitor; The first end of the third capacitor is electrically connected to the first end of the first filter circuit, the second end of the third capacitor is electrically connected to the first end of the fourth capacitor, and the second end of the fourth capacitor is electrically connected to the second end of the first filter circuit.

9. The battery management controller according to claim 7 or 8, characterized in that: The interface circuit further includes: a first resistor, a second resistor, a third resistor and a fourth resistor; The first end of the first resistor is electrically connected to the input end of the interface circuit and is also electrically connected to the first end of the energy storage circuit. The second end of the first resistor is electrically connected to the first end of the second resistor and is also electrically connected to the first end of the third resistor. The second end of the second resistor is electrically connected to the first end of the fourth resistor, and is also electrically connected to the first end of the filter circuit; The second end of the third resistor is electrically connected to the second output end of the interface circuit; The second end of the fourth resistor is electrically connected to the first output end of the interface circuit.

10. The battery management controller according to claim 9, characterized in that: The battery management controller also includes: a second filtering circuit; The second filtering circuit includes N+1 filtering sub-circuits, a first end of the first filtering sub-circuit is electrically connected to the first voltage end, and a second end of the first filtering sub-circuit is electrically connected to the second output end of the first interface circuit; A first end of the N+1th filter subcircuit is electrically connected to the second output end of the Nth interface circuit, and a second end of the N+1th filter subcircuit is electrically connected to the second voltage end; Except for the first filtering sub-circuit and the (N+1)th filtering sub-circuit, the first end and the second end of the remaining filtering sub-circuits are electrically connected between the second output ends of two adjacent interface circuits.

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