Logic control circuit for improving self-locking protection into self-recovery

Abstract

The utility model discloses a logic control circuit for improving self-locking protection into self-recovery, which is used for starting control of a power management chip and comprises a starting circuit, a turn-off control circuit, a first diode, a second diode and a first capacitor. The input end of the starting circuit is connected with the power input end, and the output end is connected with the power input end of the power management chip through a first diode. The input end of the turn-off control circuit is connected with the auxiliary power supply, the output end of the turn-off control circuit is connected with the control end of the starting circuit, and when the auxiliary power supply is powered down, the output of the starting circuit is turned off; the auxiliary power supply outputs a feedback signal for the power supply management chip; the auxiliary power supply is connected with the power supply input end of the power supply management chip through a second diode; the power input end is grounded through the first capacitor; in the circuit, the cathode of the first diode and the cathode of the second diode are connected with the power supply input end. The circuit solves the problem of consistency of high-voltage and low-voltage protection states of the DC-DC power supply with wide input range, and is low in cost and low in power consumption.

Description

Technical Field

[0001] The utility model relates to the field of electronic circuits, in particular to a logic control circuit which improves self-locking protection into self-recovery. Background Art

[0002] In current DC-DC power conversion circuits, highly integrated power management chips are often used as core controllers. Figure 1 As shown, conventional power management chips have the following characteristics: (1) The working mode of the power management chip usually requires VCC to reach the starting voltage (current) before it can start working (issue PWM). (2) The VCC pin of the power management chip usually has a voltage regulator to limit the starting working voltage of the VCC pin, for example 18V. (3) Power management chips with high-voltage startup are usually powered by connecting the bus voltage to the starting resistor to the VCC pin of the power management chip. After normal startup, the auxiliary circuit will maintain the main power supply to VCC. (4) Protection mechanism (locking) of the power management chip: When abnormal conditions such as short circuit and overcurrent occur, the power management chip will turn off PWM regardless of whether the abnormal state is resolved. If the PWM output needs to be restored, the VCC power supply needs to drop to the undervoltage point, that is, the input needs to be disconnected (the input is not disconnected, which means that there is a continuous voltage to maintain the VCC power supply through the starting resistor).

[0003] For power management chips with a self-locking mechanism, the startup resistor is continuously powered. ① When the startup resistor is set too high, the VCC will power off quickly in an abnormal situation and achieve self-recovery, but it will cause the startup time to not meet the requirements and the problem of being unable to start under heavy load; ② When the startup resistor is set too low, it will enter the locked state in an abnormal situation, but the standby power consumption will not meet the requirements; ③ The startup time requirements and standby power consumption requirements need to be met, and the startup resistor is set moderately. In the application scenario of wide voltage, it will lead to two protection mechanisms under high and low input voltages, that is, under high voltage, it will enter the locked state in an abnormal situation, and under low voltage, it will enter the self-recovery state in an abnormal situation.

[0004] For example: Applications with 40VDC-100VDC input. When the input voltage is low (for example: 40V), an abnormal state occurs. The charging current provided by the input voltage through the startup resistor is less than the working current of the power management chip in the abnormal state, which can force VCC to power off quickly. Once the protection state is released, self-recovery can be achieved. When the input voltage is high (for example: 100V), an abnormal state occurs. The charging current provided by the input voltage through the startup resistor is greater than the working current of the power management chip in the abnormal state. VCC cannot power off quickly, which means that even if the abnormal state is released, it cannot self-recover. There is a defect that the protection state is inconsistent under high and low voltages. Utility Model Content

[0005] In order to solve the defect of inconsistent protection states under high and low voltages in the prior art, the utility model provides a logic control circuit which improves self-locking protection to self-recovery as a start-up control circuit of a power management chip.

[0006] The technical solution is as follows:

[0007] A logic control circuit for improving self-locking protection to self-recovery, used for startup control of a power management chip, comprising a startup circuit, a shutdown control circuit, a first diode, a second diode and a first capacitor;

[0008] The startup circuit has an input end connected to the power input end, and an output end connected to the power input end of the power management chip through the first diode;

[0009] The shutdown control circuit has an input end connected to the auxiliary power supply, and an output end connected to the control end of the startup circuit, and is used to shut down the output of the startup circuit when the auxiliary power supply is powered off; the auxiliary power supply is an output feedback signal of the power management chip;

[0010] The auxiliary power supply is connected to the power input terminal of the power management chip through the second diode; the power input terminal of the power management chip is grounded through the first capacitor;

[0011] Wherein, the cathode of the first diode, the cathode of the second diode and the power input terminal of the power management chip are connected.

[0012] Furthermore, the startup circuit includes a bias resistor, a startup resistor, a first switch tube, and a first voltage regulator tube;

[0013] The first switching tube is a field effect tube, whose gate is connected to the power input terminal through the bias resistor, and is connected to the negative electrode of the first voltage regulator tube and the output terminal of the shutdown control circuit; its drain is connected to the power input terminal through the starting resistor, and its source is connected to the positive electrode of the first voltage regulator tube and the positive electrode of the first diode.

[0014] Furthermore, the resistance of the bias resistor is 135 kΩ.

[0015] Furthermore, the resistance of the startup resistor is 1 kΩ.

[0016] Furthermore, the breakdown voltage of the first voltage regulator tube is 5.1V.

[0017] Furthermore, the shutdown control circuit includes a second switch tube and a second capacitor, the second switch tube, a control end of which is directly or through a resistor connected to the auxiliary power supply, a first output end of which is grounded, and a second output end and an output end of the shutdown control circuit; the two ends of the second capacitor are respectively connected to the first output end and the second output end of the second switch tube.

[0018] Furthermore, the second switch tube is an NPN transistor or an N-channel field effect transistor.

[0019] Furthermore, it also includes a second voltage regulator tube, whose cathode is connected to the power input terminal of the power management chip and whose anode is grounded.

[0020] The utility model achieves the following technical effects:

[0021] (1) Replace the traditional startup resistor to solve the consistency problem of high and low voltage protection status of DC-DC power supply with wide input range;

[0022] (2) It can improve the locked state of the power management chip and convert it into self-recovery mode;

[0023] (3) Turning off the startup circuit after the power management chip is started can achieve lower standby power consumption;

[0024] (4) The control circuit based on the switch tube has the characteristics of low cost and high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a startup circuit of a power management chip in the prior art;

[0026] Figure 2 The utility model relates to a startup circuit of a power management chip. DETAILED DESCRIPTION

[0027] To further illustrate each embodiment, the present invention provides drawings. These drawings are part of the disclosure of the present invention, which are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these contents, ordinary technicians in this field should be able to understand other possible implementations and advantages of the present invention.

[0028] The utility model is now further described in conjunction with the accompanying drawings and specific implementation methods.

[0029] Embodiment 1:

[0030] like Figure 2As shown, the utility model provides a logic control circuit for improving self-locking protection to self-recovery, which is composed of a start-up circuit 10, a shutdown control circuit 20, a diode D1, a diode D2, a voltage regulator DZ2, a capacitor EC1 and the like.

[0031] The input end of the startup circuit 10 is connected to the power supply VIN, and the output end thereof is connected to the power input end IC1.7 of the power management chip IC1, which is the core component of the power management circuit 30, through the diode D1, that is, connected to the power supply VCC1; wherein, the positive electrode of the diode D1 is connected to the output end of the startup circuit 10, and the negative electrode of the diode D1 is connected to the power supply VCC1.

[0032] In this embodiment, the startup circuit 10 is composed of resistors R1, R2, N-channel field effect transistor Q1 and voltage stabilizing diode DZ1, etc. Resistor R1 is a bias resistor, R2 is a startup resistor, and voltage stabilizing diode DZ1 is connected across the gate and source of Q1, and is used to maintain the gate and source voltage difference of Q1 when a high voltage is input to the gate of Q1, thereby controlling the on-resistance or on-current of Q1 and realizing constant current control.

[0033] The shutdown control circuit 20 is connected to the control terminal of the startup circuit 10 and is used to turn on or off the output of the startup circuit 10 ; the shutdown control circuit 20 is controlled by the output feedback signal of the power management chip IC1 , ie, the auxiliary power supply VCC.

[0034] In this embodiment, the shutdown control circuit 20 includes an NPN transistor Q2, resistors R4, R5 and a capacitor C2. The base of Q2 is connected to the auxiliary power supply VCC through the resistor R5; the collector of Q2 is grounded (i.e., the negative electrode of the power supply Vin-), and the emitter is connected to the gate of Q1. Resistors R4 and R5 form a voltage divider circuit to provide a bias voltage for the base of the NPN transistor Q2. Capacitor C2 is connected across the collector and emitter of Q2, and its function is to control the gate voltage of Q1 to rise or fall slowly through charging and discharging.

[0035] The auxiliary power supply VCC is grounded through the energy storage capacitor EC2, and is connected to the power input terminal IC1.7 of the power management chip IC1 through the diode D2; the power input terminal IC1.7 is grounded through the voltage regulator DZ2 and the capacitor EC2; wherein, the positive electrode of the diode D2 is connected to the auxiliary power supply VCC, and the negative electrode of the diode D2 is connected to the power input terminal IC1.7 of the power management chip IC1. D2 plays a reverse cutoff role to prevent the power supply VCC1 from reversely supplying power to the auxiliary power supply VCC when the auxiliary power supply VCC loses power.

[0036] Working principle:

[0037] At startup, the power supply VIN is pre-charged through R1, DZ1, and D1 to provide a forward bias voltage for the field effect tube Q1 to turn on. Before pre-charging, due to the presence of capacitor C2, the power supply VIN first charges C2, that is, the gate voltage of the field effect tube Q1 rises slowly. When the field effect tube Q1 is turned on, the input bus voltage VIN charges VCC1 through resistor R2.

[0038] Start-up charging current I start =Bias current I b +R2 current I D The bias current is at μA level, and the R2 current is at mA level. Design according to the actual startup time requirements. Among them, the bias current I b Refers to the pre-charge current through R1, DZ1, D1, R2 current I D It refers to the current passing through R2 when Q1 is turned on.

[0039] When the startup voltage VCC1 reaches the minimum startup voltage point of the power management chip IC1, the power management chip IC starts to work, the secondary output is normal, and VCC1 is continuously powered by the auxiliary power supply VCC.

[0040] At the same time, the auxiliary power supply VCC is divided by resistors R5 and R4, turning on the NPN transistor Q2, pulling the gate level of Q1 down to zero, and disconnecting the startup circuit 10. At this time, the power management chip IC1 is completely powered by the auxiliary power supply VCC.

[0041] Because the gate of the field effect transistor Q1 is pulled low, the voltage regulator diode DZ1 is forward-conducted at this time, so the diode D1 is added to prevent VCC1 from being pulled low.

[0042] When an abnormal situation such as overcurrent or short circuit occurs in the output, the auxiliary power supply VCC is forced to disconnect, the base voltage of Q2 drops to a low level, and the transistor Q2 is turned off. Due to the working requirements of the power management chip IC1, the voltage of VCC1 is consumed quickly. At the same time, the gate voltage of the field effect transistor Q1 rises slowly. At this time, the charging speed of the startup circuit 10 is at the μA level, and the discharge current of VCC1 is at the mA level. VCC1 can drop to the undervoltage point VCC1 (OFF). Once the abnormal state is removed, VCC1 can reach VCC1 (OFF), meeting the self-recovery requirements of the power management circuit with the power management chip IC1 as the core.

[0043] Preferably, the breakdown voltage of the voltage regulator tube DZ1 is 5.1V, which can ensure the effective conduction of the field effect tube Q1 and a small on-resistance.

[0044] Preferably, Q2 may also be an N-channel field effect transistor, in which case the gate of Q2 may be directly connected to the auxiliary power supply VCC.

[0045] Simulation and parameter calculation: Assuming the minimum input voltage VIN min =40V, maximum input voltage VIN max =100V.

[0046] 1. Startup circuit

[0047] Assumptions: At the lowest input voltage, the startup time is about T≈500ms. The maximum charging voltage is 18V, and the undervoltage point is 9V. The startup current of VCC1 is 100μA, and the operating current is 5mA.

[0048] Setting: Bias current I b =100μA, the startup time caused by the bias current is designed to be about 15us, I=C×U÷T=C×18÷15×0.001=100μA, and C=82uF.

[0049] The startup charging current I=C×U÷T=C×18÷500×0.001=2.952mA, that is, the charging current needs to be set greater than this value. The maximum value of R2 resistance R2=[VIN(min)-VCC1-VF(D1)]÷I=[40V-18V-0.7V]÷0.002952A=7215Ω, so select R2=1kΩ.

[0050] The breakdown voltage of the voltage regulator DZ1 is 5.1V, and the Vgs voltage of the clamping field effect tube Q1 is used. Then the voltage of R1 = VIN-VCC1-V(D1)-V(DZ1) = 40-18-0.7-5.1 = 16.2V, and the bias current is set to 0.1mA, so R1 = 16.2÷0.0001 = 162KΩ (the actual value is 135KΩ).

[0051] The presence of capacitor C2 forces the FET Q1 to turn on later. That is, the bias circuit charges C2 first, during which time VCC1 has quickly powered down to the VCC undervoltage point, achieving self-recovery.

[0052] 2. Shutdown control circuit:

[0053] The voltage of R4 is 0.7V. Assuming the bias is 0.1mA, then R4 = 0.7÷0.0001 = 7kΩ, and the value is 10kΩ.

[0054] Then R5 = (VCC-0.7) ÷ 0.0001 = 123kΩ (R5 mainly has the function of current limiting, and its value is less than this value, and the actual value is 10kΩ).

[0055] The standby power consumption after normal startup, in addition to the operating current of the power management chip, is composed of R5, R4, and R1, which is less than the power consumption of a single startup resistor.

[0056] In a specific application, preferably, the resistance value of R1 is 100 kΩ to 150 kΩ; the resistance value of R2 is 1 kΩ to 5.1 kΩ.

[0057] The improved self-locking protection is a self-recovering logic control circuit, which has the following advantages:

[0058] (1) Replace the traditional startup resistor to solve the consistency problem of high and low voltage protection status of DC-DC power supply with wide input range;

[0059] (2) It can improve the locked state of the power management chip and convert it into self-recovery mode;

[0060] (3) Turning off the startup circuit after the power management chip is started can achieve lower standby power consumption;

[0061] (4) The control circuit based on the switch tube has the characteristics of low cost and high reliability.

[0062] Although the present invention has been specifically demonstrated and described in conjunction with the preferred embodiments, those skilled in the art should understand that various changes may be made to the present invention in form and detail without departing from the spirit and scope of the present invention as defined in the appended claims, all of which are within the scope of protection of the present invention.

Claims

1. A logic control circuit for improving self-locking protection to self-recovery, used for startup control of a power management chip, characterized in that: It includes a start-up circuit, a shutdown control circuit, a first diode, a second diode and a first capacitor; The startup circuit has an input end connected to the power input end, and an output end connected to the power input end of the power management chip through the first diode; The shutdown control circuit has an input end connected to the auxiliary power supply, and an output end connected to the control end of the startup circuit, and is used to shut down the output of the startup circuit when the auxiliary power supply is powered off; the auxiliary power supply is an output feedback signal of the power management chip; The auxiliary power supply is connected to the power input terminal of the power management chip through the second diode; the power input terminal of the power management chip is grounded through the first capacitor; Wherein, the cathode of the first diode, the cathode of the second diode and the power input terminal of the power management chip are connected.

2. The logic control circuit for improving self-locking protection to self-recovery as claimed in claim 1, characterized in that: The startup circuit includes a bias resistor, a startup resistor, a first switch tube, and a first voltage regulator tube; The first switch tube is a field effect tube, the gate of which is connected to the power input terminal through the bias resistor, and is connected to the negative electrode of the first voltage regulator tube and the output terminal of the shutdown control circuit; Its drain is connected to the power input terminal through a starting resistor, and its source is connected to the positive electrode of the first voltage regulator tube and the positive electrode of the first diode.

3. The logic control circuit for improving self-locking protection to self-recovery as claimed in claim 2, characterized in that: The resistance of the bias resistor is 135 kΩ.

4. The logic control circuit for improving self-locking protection to self-recovery as claimed in claim 2, characterized in that: The resistance of the startup resistor is 1 kΩ.

5. The logic control circuit for improving self-locking protection to self-recovery as claimed in claim 2, characterized in that: The breakdown voltage of the first voltage regulator tube is 5.1V.

6. The logic control circuit for improving self-locking protection to self-recovery as claimed in claim 1, characterized in that: The shutdown control circuit includes a second switch tube and a second capacitor. The control end of the second switch tube is directly or through a resistor connected to the auxiliary power supply, the first output end is grounded, and the second output end is connected to the output end of the shutdown control circuit; the two ends of the second capacitor are respectively connected to the first output end and the second output end of the second switch tube.

7. The logic control circuit for improving self-locking protection to self-recovery as claimed in claim 6, characterized in that: The second switch tube is an NPN transistor or an N-channel field effect tube.

8. The logic control circuit for improving self-locking protection to self-recovery as claimed in claim 1, characterized in that: It also includes a second voltage regulator tube, whose cathode is connected to the power input terminal of the power management chip and whose anode is grounded.

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