High-performance SIP circuit based on FPGA

Abstract

The utility model relates to the field of chip integration, in particular to a high-performance SIP (session initiation protocol) circuit based on an FPGA (field programmable gate array). Comprising a base, and a system integrated chip based on an FPGA is integrated on the base; the plurality of DDR3 chips are integrated on the base and are connected with the system integrated chip; the QSPI Flash is integrated on the base and is connected with the system integrated chip; the eMMC is integrated on the base and is connected with the system integrated chip; a micro-processing module is formed by the base, the DDR3 chip, the QSPI Flash, the system integrated chip and the eMMC, and the micro-processing module is connected with the outside through various interfaces. According to the utility model, the micro-processing module is packaged on the plastic package substrate, so that the integration level is improved, the performance is also improved, and the effects of high-speed data transmission and high-speed serial data transmission are realized by arranging the pins to be connected with external equipment.

Description

Technical Field

[0001] The utility model relates to the field of chip integration, in particular to a high-performance SIP circuit based on FPGA. Background Art

[0002] The high-performance general-purpose image digital signal processing SIP circuit based on FPGA is a combined signal processing system that integrates computing and storage devices. This system solves many challenges in the field of signal processing by combining different computing devices, such as signal processors, unit controllers, and high-speed data transmission devices. The combined signal processing system has the advantages of high performance, high reliability, and high integration, and is an important trend in the development of networked systems.

[0003] Each single signal processing system has its own unique advantages and limitations. By combining multiple different single systems, multiple information sources can be used to complement each other to build a multifunctional signal processing system with higher performance and larger capacity. High-performance processors have become one of the indispensable core components of various large-scale computing devices.

[0004] In the application of modern signal processors, the requirements for functions are getting higher and higher, and the functions that the system needs to implement are becoming more and more complex. However, the increase in functions is often accompanied by an increase in the number of devices and functions, which may lead to an increase in the volume and weight of the overall solution. Therefore, how to effectively reduce the volume and weight of the system while maintaining enhanced functions is an important long-term research topic. Utility Model Content

[0005] In order to overcome the above-mentioned technical problems existing in the prior art, an embodiment of the utility model provides a high-performance SIP circuit based on FPGA, which realizes a system-level packaged circuit by directly packaging an FPGA-based system integrated chip and key functions on a base.

[0006] In order to achieve the above-mentioned purpose, an embodiment of the utility model provides a high-performance SIP circuit based on FPGA, comprising: a base, on which a system integrated chip based on FPGA is integrated; multiple DDR3 chips, which are integrated on the base and connected to the system integrated chip; QSPI Flash, which is integrated on the base and connected to the system integrated chip; eMMC, which is integrated on the base and connected to the system integrated chip; a microprocessing module is formed by the base, the DDR3 chip, the QSPI Flash, the system integrated chip and the eMMC, and the microprocessing module is connected to the outside through multiple interfaces.

[0007] Preferably, the base is a ceramic substrate.

[0008] Preferably, the system integrated chip is arranged in the middle of the ceramic substrate, the DDR3 chip is arranged on the upper side of the system integrated chip, the QSPI Flash and the eMMC are arranged on the lower side of the ceramic substrate, the QSPI Flash is configured on the side of the ceramic substrate away from the interface, and the eMMC is configured on the side of the ceramic substrate close to the interface.

[0009] Preferably, the number of the DDR3 chips is 2.

[0010] Preferably, the DDR3 chip further includes an auxiliary power supply, and the model of the auxiliary power supply is: JPL51200.

[0011] Preferably, the system integrated chip includes an ARM processing chip and an FPGA bare chip.

[0012] Preferably, the model of the system integrated chip is: Huawei HiSilicon Kunpeng 920, the model of the ARM processing chip is: PS Cortex A9, and the model of the FPGA bare chip is: FMQL45T900.

[0013] Preferably, the microprocessor module is connected to an external crystal oscillator, and the interface includes a UART interface, a CAN bus interface, an I2C bus interface, an XADC interface and an expandable IO interface.

[0014] Preferably, the FPGA-based high-performance SIP circuit further includes a power supply module connected to the micro-processing module for providing a stable power supply to the micro-processing module.

[0015] Preferably, the eMMC is connected to a mobile storage unit, the mobile storage unit is an SD card / TF card, and the QSPI Flash is connected to a peripheral device via a PCIe bus.

[0016] Through the technical solution provided by the utility model, the utility model has at least the following technical effects:

[0017] By encapsulating the microprocessor module on the plastic package substrate, the integration is improved and the performance is also improved. At the same time, by setting pins to connect with external devices, high-speed data transmission and high-speed serial data transmission are achieved. Other features and advantages of the embodiment of the utility model will be described in detail in the subsequent specific implementation method section. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide a further understanding of the embodiments of the present utility model and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present utility model, but do not constitute a limitation on the embodiments of the present utility model. In the accompanying drawings:

[0019] Figure 1 It is a structural schematic diagram of a high-performance SIP circuit based on FPGA provided by an embodiment of the utility model. DETAILED DESCRIPTION

[0020] The specific implementation of the embodiment of the utility model is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the utility model, and is not used to limit the embodiment of the utility model.

[0021] The terms "system" and "network" in the embodiments of the present invention can be used interchangeably. "Multiple" refers to two or more than two. In view of this, in the embodiments of the present invention, "multiple" can also be understood as "at least two". "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the previous and subsequent associated objects are in an "or" relationship. In addition, it should be understood that in the description of the embodiments of the present invention, words such as "first" and "second" are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0022] See also Figure 1 The utility model embodiment is a high-performance SIP circuit based on FPGA, comprising: a base, on which a system integrated chip based on FPGA is integrated; a plurality of DDR3 chips, which are integrated on the base and connected to the system integrated chip; a QSPI Flash, which is integrated on the base and connected to the system integrated chip; an eMMC, which is integrated on the base and connected to the system integrated chip; a microprocessing module is formed by the base, the DDR3 chip, the QSPI Flash, the system integrated chip and the eMMC, and the microprocessing module is connected to the outside through a variety of interfaces.

[0023] Preferably, the base is a ceramic substrate.

[0024] In a possible implementation, a high degree of integration is achieved by integrating the microprocessor module on the base. On this basis, the DDR3 chip is further connected to the system integrated chip, and the DDR3 memory module provides the necessary data storage and cache for the system integrated chip to support the data processing requirements of the system integrated chip. QSPI Flash and eMMC are connected to the system integrated chip, where QSPI Flash is usually used to store the boot loader, which is loaded into RAM for execution when the system starts. eMMC is used to store information of external devices.

[0025] In an embodiment of the utility model, the system integrated chip is arranged in the middle of the ceramic substrate, the DDR3 chip is arranged on the upper side of the system integrated chip, the QSPI Flash and the eMMC are arranged on the lower side of the ceramic substrate, the QSPI Flash is configured on the side of the ceramic substrate away from the interface, and the eMMC is configured on the side of the ceramic substrate close to the interface.

[0026] Preferably, the number of the DDR3 chips is 2.

[0027] Preferably, the DDR3 chip further includes an auxiliary power supply, and the model of the auxiliary power supply is: JPL51200.

[0028] In one possible implementation, by placing the system integrated chip in the middle of the ceramic substrate and connecting it with multiple DDR3 chips, QSPI Flash and eMMC, the wiring is minimized and the space utilization is optimized. This design not only simplifies the layout, but also improves the performance and reliability of the overall system. The use of ceramic substrates can also provide better heat dissipation and electrical characteristics, and is suitable for applications requiring high performance and stability.

[0029] Furthermore, by configuring two DDR3 chips, the system not only obtains a larger storage capacity to meet the needs of large-capacity memory, but also implements fault isolation. This design strategy ensures that even if a DDR3 chip fails, the entire system can continue to operate stably. Fault isolation can improve system reliability, which is particularly important in application scenarios that have strict requirements on system stability.

[0030] Furthermore, the auxiliary power supply in the DDR3 memory chip, model JPL51200, is a component specially designed to provide additional power support. It is usually used to ensure that the memory chip can maintain stable operation under the condition of large voltage fluctuations or load changes. This auxiliary power supply can not only ensure the normal operation of each part of the memory module, but also improve the electrical stability and performance of the entire system.

[0031] In the embodiment of the utility model, the system integrated chip includes an ARM processing chip and an FPGA bare chip.

[0032] Preferably, the model of the system integrated chip is: Huawei HiSilicon Kunpeng 920, and the system integrated chip adopts a domestic chip. The model of the ARM processing chip is: PS Cortex A9, and the model of the FPGA bare chip is: FMQL45T900.

[0033] In one possible implementation, the system integrated chip combines an ARM processor and an FPGA bare chip. This design allows for both general processing power and programmable logic flexibility on a single chip. The ARM processor provides powerful general computing and processing capabilities, capable of running a variety of applications and operating systems. The FPGA bare chip, through programmable logic resources, allows hardware-level acceleration and processing tasks to be customized according to specific needs, thereby achieving performance optimization and power efficiency.

[0034] This integrated solution enables the system to be flexible in various application scenarios, whether it requires high-performance computing, real-time data processing or low-power operation, it can find a balance. By combining the advantages of ARM processors and FPGA bare chips, users can customize and optimize the system to meet complex computing needs and performance challenges.

[0035] Furthermore, Zynq SoC integrates the ARM Cortex A9 processor and the FPGA bare chip on a single chip. This high degree of integration provides processing power and programmable logic flexibility, enabling the system to handle general computing tasks and customized hardware acceleration requirements on the same platform. The ARM Cortex A9 processor provides powerful general computing capabilities and is suitable for software execution in various application scenarios. At the same time, the FPGA bare chip can be optimized at the hardware level according to specific needs to accelerate specific tasks such as signal processing, image processing, etc., thereby improving the overall performance and response speed of the system.

[0036] In an embodiment of the utility model, the microprocessor module is connected to an external crystal oscillator, and the interface includes a UART interface, a CAN bus interface, an I2C bus interface, an XADC interface and an expandable IO interface.

[0037] In one possible implementation, UART is used to implement serial communication, such as console output or device control. CAN bus is used for network communication in vehicles and industrial applications. I2C bus is used for low-speed device communication. PCle is used for high-speed data transmission and expansion, such as connecting external storage devices or network cards. The expandable IO interface is usually used to connect external expansion boards or other external devices, providing a general digital input and output interface.

[0038] In an embodiment of the utility model, the FPGA-based high-performance SIP circuit further includes a power supply module connected to the micro-processing module for providing a stable power supply to the micro-processing module.

[0039] In a possible implementation, the power supply module is designed to provide a stable voltage output to ensure that the microprocessor module is not affected by power supply fluctuations during operation, thereby ensuring the stability and reliability of the system.

[0040] In an embodiment of the utility model, the eMMC is connected to a mobile storage unit, the mobile storage unit is an SD card / TF card, and the QSPI Flash is connected to a peripheral device through a PCIe bus.

[0041] In one possible implementation, the eMMC and SD card / TF card provide non-volatile data storage for storing operating systems, applications, and user data. In a multi-device system, the SD card / TF card can be used to share data between different devices.

[0042] The optional implementation modes of the embodiments of the utility model are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the utility model are not limited to the specific details in the above implementation modes. Within the technical concept of the embodiments of the utility model, the technical scheme of the embodiments of the utility model can be subjected to various simple modifications, and these simple modifications all belong to the protection scope of the embodiments of the utility model.

[0043] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the embodiments of the utility model will not further describe various possible combinations.

[0044] In addition, various implementations of the embodiments of the present utility model can also be arbitrarily combined, as long as they do not violate the concept of the embodiments of the present utility model, they should also be regarded as the contents disclosed in the embodiments of the present utility model.

Claims

1. A high-performance SIP circuit based on FPGA, characterized in that: include: A base, on which a system integration chip based on FPGA is integrated; A plurality of DDR3 chips are integrated on the base and connected to the system integrated chip; QSPI Flash, integrated on the base and connected to the system integrated chip; eMMC, integrated on the base and connected to the system integrated chip; The base, the DDR3 chip, the QSPI Flash, the system integrated chip and the eMMC form a microprocessing module, and the microprocessing module is connected to the outside through a variety of interfaces.

2. The high-performance SIP circuit based on FPGA according to claim 1, characterized in that: The base is a ceramic substrate.

3. The high-performance SIP circuit based on FPGA according to claim 2, characterized in that: The system integrated chip is arranged in the middle of the ceramic substrate, the DDR3 chip is arranged on the upper side of the system integrated chip, the QSPI Flash and the eMMC are arranged on the lower side of the ceramic substrate, the QSPI Flash is configured on the side of the ceramic substrate away from the interface, and the eMMC is configured on the side of the ceramic substrate close to the interface.

4. The high-performance SIP circuit based on FPGA according to claim 2, characterized in that: The number of the DDR3 chips is 2.

5. The high-performance SIP circuit based on FPGA according to claim 4, characterized in that: The DDR3 chip also includes an auxiliary power supply, and the model of the auxiliary power supply is: JPL51200.

6. The high-performance SIP circuit based on FPGA according to claim 2, characterized in that: The system integrated chip includes an ARM processing chip and an FPGA bare chip.

7. The high-performance SIP circuit based on FPGA according to claim 2, characterized in that: The model of the system integrated chip is: Huawei HiSilicon Kunpeng 920, the model of the ARM processing chip is: PS Cortex A9, and the model of the FPGA bare chip is: FMQL45T900.

8. The high-performance SIP circuit based on FPGA according to claim 1, characterized in that: The microprocessor module is connected to an external crystal oscillator, and the interface includes a UART interface, a CAN bus interface, an I2C bus interface, an XADC interface, and an expandable IO interface.

9. The high-performance SIP circuit based on FPGA according to claim 1, characterized in that: The FPGA-based high-performance SIP circuit also includes a power supply module connected to the microprocessing module and used to provide a stable power supply for the microprocessing module.

10. The high-performance SIP circuit based on FPGA according to claim 1, characterized in that: The eMMC is connected to a mobile storage unit, the mobile storage unit is an SD card / TF card, and the QSPI Flash is connected to a peripheral device via a PCIe bus.

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