Data line test circuit and display panel
By setting a test device that can be connected with lasers on the display panel, the problems of low data line testing efficiency and electrostatic damage in the prior art are solved, and efficient testing and electrostatic elimination are achieved.
Patent Information
- Application Number
- CN202421643978.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-11
- Publication Date
- 2025-06-10
- Estimated Expiration
- 2034-07-11
AI Technical Summary
The prior art tests the data lines of display panels using GIP technology, and the test efficiency is inefficient and cannot effectively eliminate the electrostatic damage caused by the array circuit.
A data line testing circuit is designed, and by setting a test device on the display panel, the test device is disconnected internally. When testing is required, the test line is connected to the corresponding data line through laser melting, so that any data line can be tested. At the same time, the peripheral test line is connected to the anti-static wire, which can effectively eliminate static electricity generated by the array circuit.
It improves the efficiency of data line testing, effectively eliminates the electrostatic damage caused by the array circuit, and extends the service life of the display panel.
Smart Images

Figure CN222965331U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of display panels, and particularly relates to a data line test circuit and a display panel. Background Art
[0002] With the development of panel technology, narrow-bezel display panels with a higher screen-to-body ratio are gradually becoming the mainstream and are evolving towards borderless displays. Currently, the so-called borderless display panels on the market all have relatively narrow black outer borders, under which display driving circuits such as GIP (Gate Driver In Panel) are distributed.
[0003] The GIP technology moves the shift register of the gate circuit in the integrated circuit to the display panel side. The advantage of this is that it can save scan chips, reduce material costs, reduce process steps and shorten process time, thereby reducing the panel cost and enabling a narrower bezel design.
[0004] In the prior art, when testing the data lines of a display panel using GIP technology, the test data lines can only test a few individual data lines. For example, Figure 1 in [reference], only the signal condition of one of the data can be tested, and this signal is only the signal from the Pad of the IC to the test Pad, rather than the signal condition of the data line actually connected to the active display area AA, resulting in very low test efficiency.
[0005] On the other hand, the array circuit of the display panel is prone to generating static electricity, but the existing test lines have poor anti-static ability and are likely to damage the display panel circuit. Summary of the Invention
[0006] In the prior art, when testing a display panel, the test efficiency is low, and the static electricity damage generated by the array circuit cannot be effectively eliminated.
[0007] To address the above problems, a data line test circuit and a display panel are proposed. By setting a test device on the display panel, the inside of the test device is disconnected. When testing is required, the test line is connected to the corresponding data line through laser melting, so that any data line can be tested, improving the test efficiency. In addition, the peripheral test line is also connected to an anti-static line, which can effectively eliminate the static electricity generated by the array circuit.
[0008] In a first aspect, a data line test circuit includes:
[0009] Peripheral test lines;
[0010] Test pads;
[0011] Multiple test devices;
[0012] The test devices are respectively connected to the data lines one by one;
[0013] The test pad is electrically connected to one end of the peripheral test line;
[0014] One end of the test device is respectively electrically connected to the corresponding data line, and the other end is connected to the peripheral test line;
[0015] The inside of the test device is disconnected. When it is necessary to test the data line, the inside of the test device corresponding to the data line is connected and conducted through laser melting for testing.
[0016] Combined with the data line test circuit of the present invention, in the first possible implementation manner, the data line test circuit further includes:
[0017] An anti-static line;
[0018] The anti-static line is arranged outside the peripheral test line;
[0019] The anti-static line is respectively electrically connected to the peripheral test line and the peripheral VCOM line, and is used to eliminate the static electricity generated during the test.
[0020] Combined with the first possible implementation manner of the present invention, in the second possible implementation manner, the test device is a TFT transistor device.
[0021] Combined with the second possible implementation manner of the present invention, in the third possible implementation manner, the TFT transistor device includes:
[0022] A first SD terminal;
[0023] A second SD terminal;
[0024] A gate terminal;
[0025] The first SD terminal is electrically connected to the data line of the corresponding AA area;
[0026] The second SD terminal is electrically connected to the peripheral test line;
[0027] The gate terminal is arranged staggeredly above the first SD terminal and the second SD terminal and is suspended.
[0028] Combined with the third possible implementation manner of the present invention, in the fourth possible implementation manner, during the test, the anti-static line disconnects the connection between the peripheral test line and the anti-static line through laser melting.
[0029] Combined with the fourth possible implementation mode of the present utility model, in the fifth possible implementation mode, the first SD terminal is connected to the gate terminal by laser melting during testing, and the second SD terminal is connected to the gate terminal by laser melting during testing.
[0030] In a second aspect, a display panel includes the data line testing circuit described in the first aspect.
[0031] Implementing the data line testing circuit and the display panel of the present utility model, by setting a testing device on the display panel, the inside of the testing device is disconnected, and when testing is required, the testing line is connected to the corresponding data line by laser melting, so that any data line can be tested, improving the testing efficiency, and the peripheral testing line is also connected to the anti-static line, which can effectively eliminate the static electricity generated by the array circuit. Description of the Drawings
[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0033] Figure 1 Schematic diagram of a data line testing circuit in the prior art;
[0034] Figure 2 Schematic diagram of the data line testing circuit in the present utility model;
[0035] Figure 3 Partial enlarged schematic diagram of the data line testing circuit in the present utility model;
[0036] Figure 4 Partial enlarged schematic diagram of the data line testing circuit during testing in the present utility model;
[0037] Figure 5 Enlarged schematic diagram of the TFT transistor device in the present utility model. Detailed Embodiments
[0038] The following will clearly and completely describe the technical solutions in the present utility model in conjunction with the drawings in the utility model. Obviously, the described embodiments are only some embodiments of the present utility model, rather than all embodiments. Based on the embodiments in the present utility model, other embodiments obtained by those of ordinary skill in the art without creative efforts all belong to the scope of protection of the present utility model.
[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this utility model belongs. The terms used in the description of this utility model in this article are only for the purpose of describing specific embodiments, and are not intended to limit this utility model. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.
[0040] It should be noted that when an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.
[0041] It should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to this application.
[0042] In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality" means two or more, unless otherwise specifically defined.
[0043] In the prior art, when testing a display panel, the test efficiency is low, and the electrostatic damage generated by the array circuit cannot be effectively eliminated, such as Figure 1 , Figure 1 is a schematic diagram of a data line test circuit in the prior art.
[0044] In view of the above problems, a data line test circuit and a display panel are proposed.
[0045] In the first aspect, as Figure 2 and Figure 3 , Figure 2 is a schematic diagram of the data line test circuit in this utility model, Figure 3It is a partially enlarged schematic diagram of the data line test circuit in the present utility model; a data line test circuit includes an external test line 100, a test pad 200, and a plurality of test devices 300; the test devices 300 are respectively connected to the data lines one by one; the test pad 200 is electrically connected to one end of the external test line 100; one end of the test device 300 is electrically connected to the corresponding data line respectively, and the other end is connected to the external test line 100; the inside of the test device 300 is disconnected, and when it is necessary to test the data line, the inside of the test device 300 corresponding to the data line is connected and conducted through laser melting for testing. By arranging the test device 300 on the display panel, the inside of the test device 300 is disconnected, and when it is necessary to test, the test line 100 is connected to the corresponding data line through laser melting, so that any data line can be tested, improving the test efficiency, and the external test line 100 is also connected to the anti-static line 400, which can effectively eliminate the static electricity generated by the array circuit.
[0046] Furthermore, the data line test circuit further includes an anti-static line 400; the anti-static line 400 is arranged outside the external test line 100; the anti-static line 400 is respectively electrically connected to the external test line 100 and the external VCOM line for eliminating the static electricity generated during the test.
[0047] Preferably, as Figure 5 , Figure 5 It is a partially enlarged schematic diagram of the TFT transistor device in the present utility model. The test device 300 is a TFT transistor device. The TFT transistor device includes a first SD terminal 310, a second SD terminal 320, and a gate terminal 330 (Gate); the first SD terminal 310 is electrically connected to the data line in the corresponding AA area; the second SD terminal 320 is electrically connected to the external test line 100; the gate terminal 330 (Gate) is staggered above the first SD terminal 310 and the second SD terminal 320 and is suspended.
[0048] As Figure 4 , Figure 4 It is a partially enlarged schematic diagram when the data line test circuit in the present utility model is tested; when the anti-static line 400 is tested, the connection between the external test line 100 and the anti-static line 400 is disconnected through laser melting. The first SD terminal 310 is connected to the gate terminal 330 (Gate) through laser melting during the test, and the second SD terminal 320 is connected to the gate terminal 330 (Gate) through laser melting during the test.
[0049] The test device 300 is a TFT transistor. The gate terminal 330 (Gate) is in a floating state. The second SD terminal 320 is connected to the peripheral test line 100, and the first SD terminal 310 is connected to the data line in the AA effective display area, that is, each data line is connected to this device. Since the gate terminal 330 (Gate) is floating, this TFT transistor device is normally in an off state. When static electricity exists, it will conduct through this TFT transistor device (which is equivalent to a large resistor at this time) to the peripheral VCOM, thereby avoiding static electricity accumulation and improving the anti-static ability of the product.
[0050] If it is necessary to test the signal condition of one of the data lines, laser fusion can be used to short-circuit this TFT transistor device, that is, the first SD terminal 310 and the second SD terminal 320 of this TFT transistor device are connected to the Gate through laser. In addition, it is also necessary to use laser fusion to disconnect the connection between the peripheral test line 100 and the peripheral VCOM. In this way, the signal condition of any data line can be tested, and the signal line is the actual signal line passing through the AA area. The data line tested in this way is more reliable. This device realizes the functions of anti-static and testing the signal of the data line, thereby improving the competitiveness of the product.
[0051] In the second aspect, a display panel includes the data line test circuit of the first aspect.
[0052] Implementing a data line test circuit and a display panel of the present utility model, by setting a test device 300 on the display panel, the inside of the test device 300 is disconnected. When testing is required, the test line 100 is connected to the corresponding data line through laser melting, so that any data line can be tested, improving the test efficiency. In addition, the peripheral test line 100 is also connected to the anti-static line 400, which can effectively eliminate the static electricity generated by the array circuit.
[0053] The above are only the preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.
Claims
1. A data line test circuit, characterized in that: include: Peripheral test line; Test pad; Multiple test fixtures; The test devices are connected one by one with the data lines respectively; The test pad is electrically connected to one end of the peripheral test line; One end of the test device is electrically connected to the corresponding data line, and the other end is connected to the peripheral test line; The testing device is internally disconnected. When the data line needs to be tested, the internal connection of the testing device corresponding to the data line is made conductive by laser melting to perform the test.
2. The data line test circuit according to claim 1, characterized in that: The data line test circuit also includes: Anti-static wire; The anti-static wire is arranged at the periphery of the peripheral test wire; The anti-static wire is electrically connected to the peripheral test wire and the peripheral VCOM wire respectively, and is used to eliminate static electricity generated during the test process.
3. The data line test circuit according to claim 2, characterized in that: The test device is a TFT transistor device.
4. The data line test circuit according to claim 3, characterized in that: The TFT transistor device comprises: First SD terminal; Second SD terminal; Gate terminal; The first SD terminal is electrically connected to the data line of the corresponding AA area; The second SD terminal is electrically connected to the peripheral test line; The gate terminals are alternately arranged above the first SD terminal and the second SD terminal and are suspended.
5. The data line test circuit according to claim 4, characterized in that: When the anti-static wire is tested, the connection between the peripheral test wire and the anti-static wire is disconnected by laser melting.
6. The data line test circuit according to claim 5, characterized in that: The first SD terminal is connected to the gate terminal by laser melting during testing, and the second SD terminal is connected to the gate terminal by laser melting during testing.
7. A display panel, characterized in that: The invention comprises the data line test circuit as described in any one of claims 1 to 6.