Electronic package

Abstract

An electronic package is mainly characterized in that a soldering tin bump is formed on a bearing structure provided with an electronic element, a conductive column is arranged on the soldering tin bump, and the electronic element, the soldering tin bump and the conductive column are coated with a coating layer, so that a wiring structure is arranged on the coating layer. Therefore, by means of the design that the soldering tin protruding block is connected with the bearing structure and the conductive column is connected with the wiring structure, the bearing structure and the wiring structure are connected through the soldering tin protruding block and the conductive column, and the problem of bridging short circuit of the soldering tin protruding block is avoided.

Description

Technical Field

[0001] This application relates to a semiconductor packaging technology, particularly an electronic package that can meet the requirements of high-density contacts. Background Art

[0002] To ensure the continuous miniaturization and multifunctionality requirements of electronic products, semiconductor packaging needs to develop towards smaller sizes to facilitate the connection of multiple pins and have high functionality. For example, in advanced packaging processes, common packaging types such as 2.5D packaging processes, Fan-Out wiring combined with embedded component processes, etc.

[0003] Figure 1 FIG. 12 is a schematic cross-sectional view of a conventional semiconductor package 1. In the semiconductor package 1, a semiconductor chip 11 with a plurality of electrode pads 110 and a plurality of solder balls 13 are disposed on a substrate structure 10 having a circuit layer 101. Then, a semiconductor chip 11 and the solder balls 13 are covered with a coating layer 15. After that, a wiring structure 16 electrically connecting the electrode pads 110 and the solder balls 13 is formed on the coating layer 15. A plurality of functional components 14 electrically connected to the wiring structure 16 are disposed on the wiring structure 16 through conductive bumps 17, and the functional components 14 are covered with a packaging layer 18. In addition, the substrate structure 10 is placed on a circuit board 1a through a plurality of solder bumps 12, and the solder balls 13 are electrically connected to the circuit layer 101.

[0004] However, in the conventional semiconductor package 1, the substrate structure 10 and the wiring structure 16 are interconnected through the solder balls 13. The solder balls 13 have too large a volume at the middle section, so they are prone to contact each other, resulting in bridge short circuits. Therefore, the number of solder balls 13 arranged is limited, which easily leads to the problem of too few contacts, so that the specifications of the semiconductor package 1 cannot meet the requirements of high-density contacts.

[0005] Therefore, how to overcome the problems of the above-mentioned prior art has actually become a difficult problem that the industry urgently needs to overcome. Summary of the Utility Model

[0006] In view of the above-mentioned various deficiencies of the prior art, this application provides an electronic package, including: a carrier structure having a circuit layer, which defines opposite first and second sides; solder bumps disposed on the first side of the carrier structure and electrically connected to the circuit layer; conductive pillars disposed on the solder bumps; at least one electronic component disposed on the first side of the carrier structure and electrically connected to the circuit layer; a coating layer disposed on the first side of the carrier structure and covering the solder bumps, conductive pillars and electronic components; and a wiring structure disposed on the coating layer and having at least one wiring layer electrically connecting the electronic component and the conductive pillar.

[0007] The present application also provides a method for manufacturing an electronic package, including: providing a carrier structure having a circuit layer, which defines opposite first and second sides; forming solder bumps on the first side of the carrier structure, and the solder bumps are electrically connected to the circuit layer; forming conductive pillars on the solder bumps; disposing at least one electronic component on the first side of the carrier structure, and the electronic component is electrically connected to the circuit layer; forming a coating layer on the first side of the carrier structure to coat the solder bumps, conductive pillars and electronic components with the coating layer; and forming a wiring structure on the coating layer, wherein the wiring structure has at least one wiring layer electrically connecting the electronic component and the conductive pillar.

[0008] In the above-mentioned electronic package and its manufacturing method, the conductive pillar is a metal pillar.

[0009] In the above-mentioned electronic package and its manufacturing method, a plurality of conductive elements are provided on the wiring structure.

[0010] In the above-mentioned electronic package and its manufacturing method, at least one functional element is provided on the wiring structure.

[0011] In the above-mentioned electronic package and its manufacturing method, a plurality of the electronic components are embedded in the coating layer.

[0012] In the above-mentioned electronic package and its manufacturing method, at least one electronic device electrically connected to the circuit layer is provided on the second side of the carrier structure. For example, the electronic device is a semiconductor chip or a packaging module.

[0013] In the above-mentioned electronic package and its manufacturing method, an encapsulation layer covering the carrier structure and the coating layer is further included. For example, the wiring structure is also formed on the encapsulation layer.

[0014] In the above-mentioned electronic package and its manufacturing method, the width of the carrier structure is smaller than the width of the wiring structure.

[0015] As can be seen from the above, in the electronic package and its manufacturing method of the present application, mainly through the design of connecting the carrier structure by the solder bumps and connecting the wiring structure by the conductive pillars, the carrier structure and the wiring structure are interconnected by the solder bumps and the conductive pillars. Therefore, compared with the prior art, the volume of the conductive pillars in the middle section is much smaller than that of the existing solder balls, so they will not contact each other, thereby avoiding the problem of bridging short circuit. As a result, the number of their layouts can be greatly increased without the problem of too few contact points, which is beneficial to meeting the requirements of high-density contacts for the electronic package of the present application. Description of the Drawings

[0016] Figure 1 It is a schematic cross-sectional view of an existing semiconductor package.

[0017] Figures 2A to 2ECross-sectional schematic diagram of the first embodiment of the method for manufacturing the electronic package of the present application.

[0018] Figures 3A to 3D Cross-sectional schematic diagram of the second embodiment of the method for manufacturing the electronic package of the present application.

[0019] Figure 3E is Figure 3D bottom view schematic diagram of

[0020] Figures 4A to 4C Cross-sectional schematic diagram of other different embodiments of the electronic package of the present application.

[0021] Description of main component symbols

[0022] 1 Semiconductor package

[0023] 1a Circuit board

[0024] 10 Substrate structure

[0025] 101, 201 Circuit layers

[0026] 11 Semiconductor chip

[0027] 110, 210 Electrode pads

[0028] 12, 22 Solder bumps

[0029] 13 Solder balls

[0030] 14, 28 Functional elements

[0031] 15, 25 Coating layers

[0032] 16, 26 Wiring structures

[0033] 17, 280, 440, 490 Conductive bumps

[0034] 18 Encapsulation layer

[0035] 2, 3, 4 Electronic packages

[0036] 20 Carrier structure

[0037] 20a First side

[0038] 20b Second side

[0039] 200 First dielectric layer

[0040] 21, 41 Electronic components

[0041] 21a Active surface

[0042] 21b Non-active surface

[0043] 211 Conductive body

[0044] 212 Insulating protective film

[0045] 213 Adhesive layer

[0046] 23 Conductive post

[0047] 260 Second dielectric layer

[0048] 261 Wiring layer

[0049] 27 Conductive element

[0050] 3a Electronic module

[0051] 35 Encapsulation layer

[0052] 44, 49 Electronic device

[0053] 9 Carrier

[0054] D, R Width

[0055] S, L Cutting path Detailed implementation manners

[0056] The following illustrates the implementation manners of the present application through specific specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification.

[0057] It should be noted that the structures, ratios, sizes, etc. shown in the attached drawings of this specification are only used to cooperate with the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present application can be implemented. Therefore, they do not have a substantial technical meaning. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present application can produce and the purposes that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in the present application. At the same time, the terms such as "upper", "first", "second", and "one" cited in this specification are only for the convenience of clear narration and are not used to limit the scope under which the present application can be implemented. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope under which the present application can be implemented.

[0058] Figures 2A to 2E It is a schematic cross-sectional view of the manufacturing method of the first embodiment of the electronic package 2 of the present application.

[0059] As Figure 2A shown, a carrier structure 20 is provided, which has opposite first side 20a and second side 20b, and a plurality of solder bumps 22 are formed on the first side 20a of the carrier structure 20, and then conductive posts 23 are formed on these solder bumps 22.

[0060] In this embodiment, the carrier structure 20 is, for example, a packaging substrate having a core layer and a circuit structure, a packaging substrate in the form of a coreless circuit structure, a silicon interposer (TSI) with through-silicon vias (TSV), or other board types, which includes at least one first dielectric layer 200 and at least one circuit layer 201 bonded to the first dielectric layer 200, such as at least one fan-out type redistribution layer (RDL).

[0061] Furthermore, the material for forming the circuit layer 201 is copper, and the conductive pillar 23 is a metal pillar such as a copper pillar. For example, the conductive pillar 23 is first erected on the solder bump 22, and then the solder bump 22 is reflowed.

[0062] Also, the material for forming the first dielectric layer 200 is such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or other dielectric materials.

[0063] It should be understood that the carrier structure 20 can also be other substrates for carrying chips, such as a lead frame, a wafer, or other board bodies with metal routing, etc., and is not limited to the above.

[0064] As Figure 2B shown, an electronic component 21 is disposed on the first side 20a of the carrier structure 20. The electronic component 21 is an active component, a passive component, or a combination thereof. Among them, the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor.

[0065] In this embodiment, the electronic component 21 is a semiconductor chip, which has opposite functional surfaces 21a and non-functional surfaces 21b. The electronic component 21 is disposed on the first side 20a of the carrier structure 20 with its non-functional surface 21b through an adhesive layer 213 (such as a thermal conductive adhesive), and the functional surface 21a has a plurality of electrode pads 210 to bond conductors 211 such as columnar, needle-shaped, or other bump-shaped conductors, and an insulating protective film 212 covering the conductors 211 is formed on the functional surface 21a to expose the conductors 211 outside the insulating protective film 212.

[0066] It should be understood that in the process sequence, the electronic component 21 can also be disposed first, and then the solder bump 22 and the conductive pillar 23 are formed.

[0067] As Figure 2C shown, a cladding layer 25 is formed on the first side 20a of the carrier structure 20, so that the cladding layer 25 covers the electronic component 21, the solder bumps 22 and the conductive pillars 23.

[0068] In this embodiment, the material for forming the cladding layer 25 is an insulating material such as polyimide (PI for short), dry film, epoxy resin or molding compound, etc., but is not limited to the above. For example, the cladding layer 25 can be formed on the first side 20a of the carrier structure 20 by means of lamination or molding.

[0069] Furthermore, a planarization process can be performed as required, so that the upper surface of the cladding layer 25 is flush with the end faces of the conductive pillars 23, the surface of the insulating protective film 212 and the top surface of the conductor 211, so that the end faces of the conductive pillars 23, the surface of the insulating protective film 212 and the top surface of the conductor 211 are exposed from the cladding layer 25. For example, the planarization process can be carried out by grinding to remove part of the materials of the conductive pillars 23, part of the materials of the insulating protective film 212, part of the materials of the conductor 211 and part of the materials of the cladding layer 25.

[0070] As Figure 2D shown, a wiring structure 26 is formed on the cladding layer 25, so that the wiring structure 26 is electrically connected to the conductive pillars 23 and the conductors 211.

[0071] In this embodiment, the wiring structure 26 has at least one second dielectric layer 260 and a wiring layer 261 (such as RDL) provided on the second dielectric layer 260, so that the wiring layer 261 of the wiring structure 26 is electrically connected to the conductive pillars 23 and the conductor 211, and is electrically connected to the electrode pad 210 through the conductors 211.

[0072] Furthermore, the material for forming the wiring layer 261 is copper, and the material for forming the second dielectric layer 260 is such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

[0073] As Figure 2E shown, a dicing process is performed along the dicing path S as Figure 2D shown, to obtain a plurality of electronic packages 2.

[0074] In this embodiment, in subsequent processes, a plurality of conductive elements 27 such as solder balls or other metal bumps (such as copper pillars) can be formed on the wiring layer 261 of the wiring structure 26, so that the electronic package 2 can be placed on an electronic device (not shown) such as a circuit board through these conductive elements 27.

[0075] Furthermore, in subsequent processes, a plurality of functional elements 28 can also be disposed on the wiring layer 261 of the wiring structure 26. For example, the functional element 28 is an active element, a passive element, or a combination of both, and the active element is, for example, a semiconductor chip, and the passive element is, for example, a resistor, a capacitor, and an inductor.

[0076] Further, the functional element 28 is electrically connected to the wiring layer 261 of the wiring structure 26 in a flip-chip manner through a plurality of conductive bumps 280 such as solder bumps, copper bumps, or others; it should be understood that there are various ways for the functional element 28 to be connected to the wiring structure 26, such as wire bonding packaging, and it is not limited to the above.

[0077] Therefore, the manufacturing method of this embodiment mainly connects the carrier structure 20 through the solder bumps 22 and the wiring structure 26 through the conductive pillars 23, so that the carrier structure 20 and the wiring structure 26 are interconnected by the solder bumps 22 and the conductive pillars 23. Therefore, compared with the prior art, the volume of the conductive pillar 23 at the middle section is much smaller than that of the existing solder balls, so they will not contact each other, thereby avoiding the problem of bridging short circuits. As a result, the number of their layouts can be greatly increased without the problem of too few contact points, which is beneficial to meeting the requirements of high-density contacts for the electronic package 2 of this application.

[0078] Figures 3A to 3D It is a cross-sectional schematic diagram of the manufacturing method of the second embodiment of the electronic package 3 of this application.

[0079] As Figure 3A shown, following Figure 2C the shown process, a singulation process is performed to obtain a plurality of electronic modules 3a. Then, the electronic module 3a is disposed on a carrier 9.

[0080] In this embodiment, the carrier 9 is a plate body such as a semiconductor material, a dielectric material, a ceramic material, a glass, or a metal material, but is not limited thereto, and the size of the carrier 9 can be a wafer form substrate or a general panel form substrate according to requirements, and can be formed on the plate body by a bonding layer such as a release film or an adhesive in a coating or bonding manner, so that the electronic module 3a is combined on the bonding layer.

[0081] As Figure 3BAs shown, an encapsulation layer 35 is formed on the carrier 9 such that the encapsulation layer 35 covers the electronic module 3a.

[0082] In this embodiment, the encapsulation layer 35 covers the coating layer 25 and the carrier structure 20.

[0083] Furthermore, the encapsulation layer 35 is an insulating material, such as polyimide (PI for short), dry film, encapsulation colloid or encapsulation material (molding compound) such as epoxy resin, which can be formed on the wiring structure 26 by lamination or molding. It should be understood that the material forming the encapsulation layer 35 can be the same as or different from the material of the coating layer 25.

[0084] Also, a planarization process can be performed as needed to make the upper surface of the encapsulation layer 35 flush with the upper surface of the coating layer 25, the end faces of the conductive posts 23, the surface of the insulating protective film 212, and the top surface of the conductor 211, so that the end faces of the conductive posts 23, the surface of the insulating protective film 212, and the top surface of the conductor 211 are exposed outside the encapsulation layer 35 and the coating layer 25. For example, the planarization process can be performed by grinding to remove part of the materials of the encapsulation layer 35, the conductive posts 23, the insulating protective film 212, the conductor 211, and the coating layer 25.

[0085] As Figure 3C shown, a wiring structure 26 is formed on the coating layer 25 and the encapsulation layer 35 to electrically connect the conductive posts 23 and the conductors 211.

[0086] As Figure 3D shown, the carrier 9 is removed, and a singulation process is performed along the cutting path L as Figure 3C shown to obtain a plurality of electronic packages 3.

[0087] In this embodiment, the width D of the carrier structure 20 is smaller than the width R of the wiring structure 26, and as Figure 3E shown, the encapsulation layer 35 covers the side surface of the carrier structure 20 to prevent the carrier structure 20 from being damaged.

[0088] Furthermore, in subsequent processes, a plurality of conductive elements 27 and the functional element 28 can be formed on the wiring layer 261 of the wiring structure 26.

[0089] Also, based on the first and second embodiments, in other embodiments, a plurality of electronic components 41 can also be embedded in the coating layer 25, such as Figure 4AThe electronic package 4 shown. Alternatively, other electronic devices 44, 49 can be provided on the second side 20b of the carrier structure 20 as required, such as Figure 4B the semiconductor chip shown or such as Figure 4C the packaged module shown.

[0090] The semiconductor chip is electrically connected to the circuit layer 201 in a flip-chip manner through a plurality of conductive bumps 440 such as solder bumps, copper bumps or others; it should be understood that there are various ways for the semiconductor chip to be electrically connected to the circuit layer 201, such as wire bonding packaging, which is not limited to the above.

[0091] The packaged module is, for example, a dynamic random-access memory (DRAM), which is stacked on the carrier structure 20 through a plurality of conductive bumps 490 such as solder bumps, copper bumps or others.

[0092] In addition, the specification types of the electronic components 21, 41, the functional components 28 and the electronic devices 44, 49 can be adjusted as required.

[0093] Therefore, the manufacturing method of this embodiment mainly connects the carrier structure 20 and the conductive column 23 to connect the wiring structure 26 through the design of the solder bump 22, so that the carrier structure 20 and the wiring structure 26 are interconnected by the solder bump 22 and the conductive column 23. Therefore, compared with the prior art, the volume of the conductive column 23 in the middle section is much smaller than that of the existing solder balls, so they will not contact each other, thus avoiding the problem of bridging short circuit. Therefore, the number of their arrangements can be greatly increased without the problem of too few contact points, which is beneficial to meeting the requirements of high-density contacts for the electronic package 3 of this application.

[0094] This application also provides an electronic package 2, 3, 4, including: a carrier structure 20 having a circuit layer 201, a plurality of solder bumps 22, a plurality of conductive columns 23, at least one electronic component 21, 41, a coating layer 25 and a wiring structure 26.

[0095] The carrier structure 20 defines opposite first side 20a and second side 20b.

[0096] The solder bumps 22 are provided on the first side 20a of the carrier structure 20 and are electrically connected to the circuit layer 201.

[0097] The conductive columns 23 are provided on the solder bumps 22.

[0098] The electronic components 21, 41 are provided on the first side 20a of the carrier structure 20 and are electrically connected to the circuit layer 201.

[0099] The described coating layer 25 is disposed on the first side 20a of the carrier structure 20 and coats the solder bumps 22, the conductive posts 23, and the electronic components 21.

[0100] The described wiring structure 26 is disposed on the coating layer 25 and has at least one wiring layer 261 that electrically connects the electronic components 21, 41 and the conductive posts 23.

[0101] In one embodiment, the conductive post 23 is a metal post.

[0102] In one embodiment, a plurality of conductive elements 27 are provided on the wiring structure 26.

[0103] In one embodiment, at least one functional element 28 is provided on the wiring structure 26.

[0104] In one embodiment, a plurality of the electronic components 41 are embedded in the coating layer 25.

[0105] In one embodiment, at least one electronic device 44, 49 that electrically connects to the circuit layer 201 is provided on the second side 20b of the carrier structure 20. For example, the electronic device 44, 49 is a semiconductor chip or a packaging module.

[0106] In one embodiment, the electronic package 3 further includes a packaging layer 35 that coats the carrier structure 20 and the coating layer 25. For example, the wiring structure 26 is also formed on the packaging layer 35.

[0107] In one embodiment, the width D of the carrier structure 20 is less than the width R of the wiring structure 26.

[0108] In summary, for the electronic package and its manufacturing method of the present application, through the design of connecting the carrier structure with the solder bumps and connecting the wiring structure with the conductive posts, the carrier structure and the wiring structure are interconnected by the solder bumps and the conductive posts. Therefore, the volume of the conductive posts in the middle section of the present application is much smaller than that of the existing solder balls, so they will not contact each other, thus avoiding the problem of bridging short circuit. As a result, the number of their layouts can be significantly increased without the problem of too few contact points, which is beneficial for the specifications of the electronic package of the present application to meet the requirements of high-density contacts.

[0109] The above embodiments are used to exemplarily illustrate the principle and its effects of the present application, rather than to limit the present application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present application. Therefore, the scope of the rights protection of the present application should be as listed in the claims.

Claims

1. An electronic package, characterized in that: include: A bearing structure having a circuit layer and defining a first side and a second side opposite to each other; A solder bump, which is disposed on the first side of the supporting structure and electrically connected to the circuit layer; A conductive column disposed on the solder bump; An electronic component, which is disposed on the first side of the supporting structure and electrically connected to the circuit layer; A coating layer, which is disposed on the first side of the supporting structure and covers the solder bump, the conductive column and the electronic component; as well as The wiring structure is arranged on the cladding layer and has a wiring layer electrically connecting the electronic element and the conductive column.

2. The electronic package according to claim 1, wherein: The conductive column is a metal column.

3. The electronic package according to claim 1, wherein: A plurality of conductive elements are arranged on the wiring structure.

4. The electronic package according to claim 1, wherein: Functional elements are arranged on the wiring structure.

5. The electronic package according to claim 1, wherein: A plurality of electronic components are embedded in the coating layer.

6. The electronic package according to claim 1, wherein: An electronic device electrically connected to the circuit layer is disposed on the second side of the supporting structure.

7. The electronic package according to claim 6, wherein: The electronic device is a semiconductor chip or a packaging module.

8. The electronic package according to claim 1, wherein: The electronic package also includes a packaging layer covering the supporting structure and the covering layer.

9. The electronic package according to claim 8, wherein: The wiring structure is also formed on the packaging layer.

10. The electronic package according to claim 1, wherein: The width of the supporting structure is smaller than the width of the wiring structure.

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