Substrate device and semiconductor packaging piece

Abstract

The embodiment of the utility model provides a substrate device and a semiconductor packaging piece. The substrate device comprises first insulating layers and first functional layers with metal patterns, wherein the first insulating layers and the first functional layers are alternately stacked; the metal pattern comprises an inductance coil, and the substrate device is used for being arranged on a substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor devices, and particularly to a substrate device and a semiconductor package. Background Art

[0002] With the continuous improvement of the integration degree of semiconductor devices, radio frequency front-end chips are more and more widely used. Therefore, radio frequency front-end chips need to support more frequency bands, need to be smaller in size, and need to be compatible with solutions in multiple countries and regions.

[0003] Inductors have a great influence on the size, integration degree and performance of radio frequency front-end chips. Therefore, there is an urgent need to provide a semiconductor device that meets the requirements of radio frequency front-end chips and includes inductors. Summary of the Utility Model

[0004] In view of this, embodiments of the present disclosure provide a substrate device and a semiconductor package.

[0005] To achieve the above object, the technical solution of the present disclosure is realized as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a substrate device, including: a first insulating layer and a first functional layer with a metal pattern that are alternately stacked; the metal pattern includes an inductor coil, and the substrate device is configured to be disposed on a substrate.

[0007] In some embodiments, the substrate includes multiple second functional layers, and the second functional layers include wiring patterns; along the stacking direction, the distance between adjacent first functional layers on the substrate device is less than the distance between adjacent second functional layers on the substrate, and the stacking direction is the stacking direction of the first insulating layer and the first functional layer.

[0008] In some embodiments, the substrate device is formed by a substrate process.

[0009] In some embodiments, the metal pattern includes multiple inductor coils.

[0010] In some embodiments, the areas of at least two of the multiple inductor coils are different.

[0011] In some embodiments, the metal pattern further includes capacitor plates and / or baluns.

[0012] In some embodiments, along the stacking direction, a plurality of solder balls are disposed on a first surface of the substrate device, and the stacking direction is the stacking direction of the first insulating layer and the first functional layer.

[0013] Second aspect, embodiments of the present disclosure provide a semiconductor package, including the substrate device in any of the above embodiments; and a substrate; the substrate device is disposed on the substrate.

[0014] In some embodiments, a plurality of the substrate devices are included.

[0015] In some embodiments, the substrate includes a second insulating layer and a second functional layer that are alternately stacked; the thickness of the substrate device is greater than the thickness of the substrate, and / or the number of the first functional layers of the substrate device is greater than the number of the second functional layers of the substrate.

[0016] In some embodiments, the thicknesses of at least two of the plurality of substrate devices are different; and / or the number of the first functional layers of at least two of the plurality of substrate devices is different.

[0017] In some embodiments, the substrate includes a second insulating layer and a second functional layer that are alternately stacked; the thickness of the first insulating layer is less than the thickness of the second insulating layer, and / or the thickness of the first functional layer is less than the thickness of the second functional layer.

[0018] In some embodiments, the substrate device further includes a first connection hole for connecting inductance coils on adjacent first functional layers; the substrate includes a second insulating layer and a second functional layer that are alternately stacked, and a second connection hole for connecting wiring patterns on adjacent second functional layers; the size of the first connection hole is less than the size of the second connection hole.

[0019] In some embodiments, a semiconductor chip is further included, and the semiconductor chip and / or the substrate device are arranged side by side on the substrate; and / or, the semiconductor chip and / or the substrate device are stacked on the substrate.

[0020] In some embodiments, a first cavity is formed between the semiconductor chip and the substrate; a second cavity is formed between the substrate device and the substrate.

[0021] Embodiments of the present disclosure provide a substrate device and a semiconductor package. The substrate device includes: a first insulating layer and a first functional layer having a metal pattern that are alternately stacked; the metal pattern includes an inductance coil, and the substrate device is configured to be disposed on a substrate. The substrate device in the embodiments of the present disclosure includes a first functional layer having a metal pattern, wherein the metal pattern includes an inductance coil. By alternately stacking the first insulating layer and the first functional layer having a metal pattern, a substrate device with a large inductance value is provided, so that the inductance can be prevented from being embedded inside the substrate and affecting the thickness or area of the substrate. Description of the Drawings

[0022] Figure 1 Schematic structure of a substrate device provided by an embodiment of the present disclosure Figure 1 ;

[0023] Figure 2 Schematic structure of a substrate device provided by an embodiment of the present disclosure Figure 2 ;

[0024] Figure 3 Schematic bottom view of a device substrate provided by an embodiment of the present disclosure;

[0025] Figure 4 Schematic structure of a substrate device provided by an embodiment of the present disclosure Figure 3 ;

[0026] Figure 5 Provided by an embodiment of the present disclosure Figure 4 Top view schematic of the substrate device in

[0027] Figure 6 Schematic structure of a substrate device provided by an embodiment of the present disclosure Figure 4 ;

[0028] Figure 7 Schematic structure of a substrate provided by an embodiment of the present disclosure;

[0029] Figure 8 Schematic structure of a semiconductor package provided by an embodiment of the present disclosure. Detailed implementation manners

[0030] Next, in combination with the embodiments and drawings of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope protected by the present disclosure.

[0031] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, to avoid confusion with the present disclosure, some well-known technical features are not described; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0032] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same reference numerals denote the same elements throughout.

[0033] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer or portion discussed below may be referred to as the second element, component, region, layer or portion. And when discussing the second element, component, region, layer or portion, it does not imply that there must be a first element, component, region, layer or portion in the present disclosure.

[0034] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0035] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0036] To thoroughly understand the present disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may have other embodiments.

[0037] It should be noted that for ease of description, the directions that may be used in the following description are defined first. The stacking direction of the first insulating layer and the first functional layer of the substrate device is defined as the vertical direction (i.e., the Z direction in the drawings). In the plane perpendicular to the Z direction, an intersecting first direction (i.e., the X direction in the drawings) and a second direction (i.e., the Y direction in the drawings) are defined. The X direction, Y direction, and Z direction can be perpendicular to each other pairwise.

[0038] In the related art, a radio frequency front-end chip includes a substrate and an IC chip and an inductor disposed on the substrate. Among them, the inductor is usually embedded in the substrate. However, embedding the inductor in the substrate will increase the thickness or area of the substrate, which causes great trouble in reducing the chip size and promoting the large-scale application of the chip.

[0039] Therefore, there is an urgent need to provide a semiconductor device with a large inductance value, low cost, and beneficial to improving the integration of radio frequency front-end chips.

[0040] In view of this, an embodiment of the present disclosure provides a substrate device, including: a first insulating layer and a first functional layer having a metal pattern that are alternately stacked; the metal pattern includes an inductor coil, and the substrate device is used to be disposed on a substrate.

[0041] Figure 1 The structural schematic of a substrate device provided by an embodiment of the present disclosure Figure 1 . As Figure 1 shown, the substrate device 100 includes a first insulating layer 110 and a first functional layer 120 having a metal pattern that are alternately stacked. The metal pattern includes an inductor coil 121, and the substrate device 100 is used to be disposed on a substrate.

[0042] In some embodiments, disposing the inductor in the substrate device can avoid embedding the inductor in the substrate, thereby reducing the substrate area. In addition, compared with embedding the inductor in the substrate, the substrate device can be more flexibly disposed on the substrate surface and has more design space. Moreover, compared with embedding the inductor in the substrate, the substrate device can control the thickness of each first insulating layer and first functional layer within a very small range, making the inductor coil closer. In addition, compared with other devices having an inductor, the substrate device provided by the embodiment of the present disclosure has the advantages of low production cost and better performance.

[0043] It should be noted that the inductors in the substrate can either all be replaced by the inductors in the substrate devices, that is, no inductors are provided in the substrate, or some of them can be replaced by the inductors in the substrate devices, with some inductors retained.

[0044] In some embodiments, the material of the first insulating layer 110 may include prepreg (PPG) material, and the prepreg material includes insulating resin, inorganic filler, and glass fiber. The first functional layer 120 includes a metal pattern and a dielectric material, and the dielectric material may include prepreg material with the same or different etching selectivity ratio as that of the first insulating layer. The first insulating layer can also be made of other insulating materials, and the dielectric material can also be made of other materials. The two materials can be the same or different, and the present disclosure does not limit the specific materials of the dielectric material and the first insulating layer.

[0045] In some embodiments, the substrate device 100 is formed by a substrate process. It should be noted that when there are multiple substrate devices, the parameters of the multiple substrate devices can be the same or different. Among them, the parameters of the substrate device may include: coil width, the distance between adjacent coils in the coil stacking direction, coil winding area, etc.

[0046] In some embodiments, the substrate device 100 is formed by a substrate process. First, a substrate is provided, and an adhesive layer is formed on the substrate. The substrate can be a glass substrate, a ceramic substrate, etc. The adhesive layer can be removed together with the substrate from the substrate device to be formed in subsequent steps. Among them, the adhesive layer is any suitable adhesive, epoxy resin, die attach film (DAF), etc., and the adhesive layer is applied on the surface of the substrate. In some embodiments, the adhesive layer is an epoxy-based thermally releasable material that loses its adhesive property when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the adhesive layer can be a UV glue that loses its adhesive property when exposed to ultraviolet (UV) light. Then, the substrate device 100 is formed on the substrate by a substrate process.

[0047] In some embodiments, the first insulating layer 110 can be formed by laminating a prepreg material on the adhesive layer. The first functional layer 120 includes a metal pattern and a dielectric material. The dielectric material includes a prepreg material with an etching selectivity different from that of the first insulating layer. The dielectric material and the patterned first mask layer can be sequentially formed on the first insulating layer 110, and the dielectric material can be etched using the patterned first mask layer, with the first insulating layer 110 as the stop layer, to form a groove for forming the metal pattern, and a conductive material can be deposited in the groove to form the first functional layer 120 with the metal pattern. Then, the first insulating layer 110 and the first functional layer 120 are alternately formed on the first functional layer 120 to constitute the substrate device 100.

[0048] In some embodiments, the dielectric material (including a prepreg material with an etching selectivity different from that of the first insulating layer 110) and the patterned second mask layer can be sequentially formed on the adhesive layer, and the dielectric material can be etched using the patterned second mask layer, with the adhesive layer as the stop layer, to form a groove for forming the metal pattern, and a conductive material can be deposited in the groove to form the first functional layer with the metal pattern. Then, the first functional layer 120 and the first insulating layer 110 are alternately formed on the first functional layer 120 to constitute the substrate device 100.

[0049] It should be noted that the present disclosure does not limit whether the bottom surface or the top surface of the substrate device is specifically the first functional layer or the first insulating layer.

[0050] In some embodiments, a metal layer can be formed on the surface of the first insulating layer 110 (or the adhesive layer) through a plating process, a patterned third mask layer can be formed on the metal layer, and the metal layer can be etched using the patterned third mask layer to form a metal pattern. Then, the prepreg material is laminated on the metal pattern to form the dielectric material (including the same prepreg material as the first insulating layer 110) of the first functional layer 120 and the next layer of the first insulating layer 110.

[0051] In some embodiments, compared with devices with inductors formed by other IC processes, the substrate device formed by the substrate process can reduce production costs and enable the substrate device to have better performance.

[0052] It should be noted that the specific number of layers of the first insulating layer 110 and the first functional layer 120 in the present disclosure is not limited to the number of layers shown in the figure, and the number of layers of the first insulating layer 110 and the first functional layer 120 can be set according to the required inductance value.

[0053] In some embodiments, the substrate device 100 further includes a first connection hole 130, and the first connection hole 130 is used to connect the inductor coils 121 on adjacent first functional layers 120.

[0054] In some embodiments, the first connection hole 130 is located in the first insulating layer 110. The first connection hole 130 is used to connect the inductance coils 121 located in different first functional layers 120 to form an inductor. A via hole can be formed in the first insulating layer 110 by chemical etching using a mask, and copper plating is performed on the inner wall of the via hole to connect the inductance coils 121 of the upper and lower layers. After copper plating, the via hole can be filled with a prepreg material to fill the via hole to form the first connection hole 130. Filling the via hole with a prepreg material after copper plating can not only exclude air, prevent the via hole from expanding and breaking due to the large gas expansion coefficient when heated, but also make the surface of the first insulating layer 110 flat. A via hole can also be formed in the first insulating layer 110 by chemical etching using a mask, and a conductive material is deposited in the via hole to form the first connection hole 130 connecting the inductance coils 121 of the upper and lower layers. In addition, the first connection holes (not shown in the figure) located at the top and bottom of the substrate device can also be used for electrical connection to pins or solder balls to achieve electrical connection between the inductor and other devices.

[0055] Compared with arranging the inductor in the substrate, the substrate device formed by the substrate process can effectively reduce the size of the first connection hole located in the first insulating layer and the thickness of the inductance coil located in the first functional layer. In this way, the inductance coil of the inductor in the substrate device can be formed into a more compact structure.

[0056] In some embodiments, a plurality of solder balls are arranged on the first surface of the substrate device along the Z direction; the Z direction is the stacking direction of the first insulating layer and the first functional layer.

[0057] Figure 2 Schematic structure of a substrate device provided by an embodiment of the present disclosure Figure 2 ; Figure 3 Schematic bottom view of a substrate device provided by an embodiment of the present disclosure, where Figure 2 can be regarded as Figure 3 a partial cross-sectional view. As shown in Figure 2 and Figure 3 , along the Z direction, the substrate device 100 includes opposite first surface 101 and second surface 102. The first surface 101 is the bottom surface of the substrate device. Four solder balls 104 are arranged on the first surface 101. The four solder balls 104 can electrically connect the substrate device 100 to the substrate. Among them, the material of the solder balls 104 can include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), Cu, silver (Ag), zinc (Zn), lead (Pb) and / or their alloys.

[0058] It should be noted that Figure 2 and Figure 3The number of solder balls shown is only for illustrative purposes and is not a limitation on the number of solder balls. The solder balls can also be other numbers, for example, one, two, three, etc. The present disclosure does not limit the number of solder balls 104.

[0059] In other embodiments, the substrate device can also be disposed on the substrate by other means, such as SMT or by lead arrangement, etc. The present disclosure does not limit this.

[0060] As Figure 1 , Figure 2 and Figure 3 shown, a solder mask layer 103 is coated on the first surface 101 and the second surface 102 of the substrate device 100 to prevent the flow of solder.

[0061] In some embodiments, the metal pattern includes a plurality of inductor coils 121, that is, a substrate device incorporates a plurality of inductors. Among them, the metal pattern in at least one layer of the first functional layer 120 may include the inductor coils 121 of a plurality of inductors. Compared with separately disposing a plurality of inductors on the substrate, the pitch between the plurality of inductors in the XOY plane can be reduced in this way.

[0062] By mounting the substrate device integrated with a plurality of inductors on the substrate, the cost of mounting a plurality of inductors on the substrate is reduced, the surface area of the substrate wasted by the pitch between the inductors is reduced, which is beneficial to reducing the size of the RF front-end chip, promoting the large-scale application of the RF front-end chip, and at the same time having performance comparable to that of a traditional RF front-end chip.

[0063] In some embodiments, the substrate device 100 includes a plurality of layers of the first functional layer 120. Among them, the number of inductor coils in each layer of the first functional layer can be the same or different. The present disclosure does not limit the number of inductor coils in each layer of the first functional layer.

[0064] Figure 4 This is a schematic structure of a substrate device provided by an embodiment of the present disclosure Figure 3 . As Figure 4 shown, the first functional layer 120a includes inductor coils 121a and 121b of two inductors, and the first functional layer 120b includes an inductor coil 121a. The inductor coil 121a is connected by the first connection hole 130a, and the inductor coil 121b is connected by the first connection hole 130b, so that the substrate device 100 includes inductors with different inductance values. It should be noted that, among them, the diameter of the region of the first functional layer penetrated by the first connection hole 130b can be larger than the diameter of the region of the insulating layer penetrated; the number of layers of the first insulating layer and the first functional layer penetrated by the first connection hole can be set according to requirements. The present disclosure does not limit this.

[0065] Figure 5For the present disclosure's embodiments provided Figure 4 a top view schematic diagram of the substrate device in Figure 5 As shown in

[0066] Figure 5 , the substrate device 100 includes two inductors. A Pin 105 may be provided on the second surface 102 of the substrate device 100. The Pin 105 is an area on the second surface 102 of the substrate device without a solder mask layer, and is used to expose the metal material under the solder mask layer. Metal pins may be provided on the Pin 105, and the metal pins are used to realize the electrical connection between the inductor and other devices. It should be noted that multiple Pins may be provided on the second surface of the substrate device 100 to lead out different inductors from different positions of the substrate device, so as to obtain inductors with different inductance values. The present disclosure does not limit the number of Pins. In addition, the Pin can also be used to indicate the position of the top surface of the substrate device.

[0067] In some embodiments, at least two of the multiple inductance coils have different areas.

[0068] In some embodiments, the areas of the inductance coils of two adjacent inductors may be the same or different, and the present disclosure does not limit this.

[0069] As shown in Figure 4 and Figure 5 Figure 5 , the substrate device 100 includes two inductors, and the number of turns of the inductance coils of the two inductors, the distance between the coils in the Z direction, the coil width, and the coil winding area are all different. It should be noted that when the substrate device includes multiple inductors, parameters such as the number of turns of the inductance coils of the multiple inductors, the distance between adjacent coils in the Z direction, the coil width, and the coil winding area may be the same or different, and the present disclosure does not limit this.

[0070] In some embodiments, the metal pattern further includes capacitor plates and / or baluns.

[0071] In some embodiments, the metal pattern in at least two first functional layers further includes capacitor plates. Among them, two capacitor plates opposite to each other in the XOY plane can form a capacitor, so that inductors and capacitors can be integrated in the substrate device. In some embodiments, the metal layer of the first functional layer can also be used as the capacitor plate of the capacitor, that is, the first functional layer does not include a dielectric material, but only includes a metal material used as the capacitor plate.

[0072] In some embodiments, the metal pattern in at least one layer of the first functional layer further includes a balun, so that an inductor and a balun device can be integrated in the substrate device.

[0073] In some embodiments, the metal pattern in at least two layers of the first functional layer further includes capacitor plates, and the metal pattern in at least one layer of the first functional layer further includes a balun, so that an inductor, a capacitor and a balun device can be integrated in the substrate device.

[0074] In some embodiments, the substrate device only embeds an inductor, that is, the metal pattern only includes an inductor coil.

[0075] Figure 6 Schematic diagram of the structure of a substrate device provided by an embodiment of the present disclosure Figure 4 As Figure 6 shown, the metal pattern in the two layers of the first functional layer 120 further includes a capacitor plate 122a and a capacitor plate 122b. The capacitor plate 122a and the capacitor plate 122b can form a capacitor, and the projections of the capacitor plate 122a and the capacitor plate 122b on the XOY plane overlap.

[0076] It should be noted that the projected areas of the two capacitor plates in the capacitor on the XOY plane can be the same or different; the capacitor plates can be multiple layers, and the present disclosure does not limit the area and number of layers of the capacitor plates.

[0077] In some embodiments, when the device substrate 100 includes a capacitor and / or a balun, a plurality of Pins can be provided on the second surface of the device substrate 100 to lead out the capacitor and / or the balun from different positions on the second surface of the device substrate. Among them, different Pins are used for the inductor, the capacitor and the balun.

[0078] In some embodiments, when the substrate device 100 includes a capacitor and the projections of the capacitor and the inductor on the XOY plane overlap, the substrate device 100 may further include a third connection hole, and the third connection hole can be used to realize the electrical connection between the inductor and the capacitor.

[0079] In some embodiments, the substrate device may further include other connection holes for leading the capacitor and / or the balun to the first surface and / or the second surface of the substrate device.

[0080] It should be noted that the metal pattern in some of the first functional layers may only include capacitor plates and / or baluns.

[0081] Figure 7 Schematic diagram of the structure of a substrate provided by an embodiment of the present disclosure. As Figure 7 shown, the substrate 200 is used to set electronic devices to realize the interconnection between electronic devices.

[0082] In some embodiments, the substrate 200 includes multiple layers of second functional layers, and the second functional layers include a wiring pattern 221. Refer to Figure 1 and Figure 7 , in the Z direction, the spacing between adjacent first functional layers 120 on the substrate device 100 is smaller than the spacing between adjacent second functional layers 220 on the substrate 200, and the Z direction is the stacking direction of the first insulating layer 110 and the first functional layer 120.

[0083] In some embodiments, the number of layers of the first functional layer 120 in the substrate device 100 is greater than the number of layers of the second functional layer 220 in the substrate 200.

[0084] In some embodiments, the spacing between adjacent first functional layers 120 on the substrate device 100 is smaller than the spacing between adjacent second functional layers 220 on the substrate 200, and the number of layers of the first functional layer 120 in the substrate device 100 is greater than the number of layers of the second functional layer 220 in the substrate 200.

[0085] In some embodiments, the substrate 200 further includes an inductor coil 222 located in the second functional layer. Since the spacing between adjacent first functional layers 120 on the substrate device 100 is smaller than the spacing between adjacent second functional layers 220 on the substrate 200, the spacing between adjacent inductor coils 121 on the substrate device 100 is smaller than the spacing between adjacent inductor coils 222 on the substrate 200.

[0086] It should be noted that in some embodiments, the inductor coil 222 in the second functional layer can also be omitted, and the inductor in the substrate is replaced by an inductor in the substrate device to reduce the area of the substrate.

[0087] In some embodiments, the substrate 200 includes alternately stacked second insulating layers 210 and second functional layers 220. In the Z direction, the spacing between adjacent first functional layers 120 on the substrate device 100 is smaller than the spacing between adjacent second functional layers 220 on the substrate 200, that is, the thickness of the first insulating layer 110 is smaller than the thickness of the second insulating layer 210.

[0088] It should be noted that when there is more than one layer of the first insulating layer between adjacent inductor coils on the substrate device in the Z direction (for example, there are multiple layers of the first insulating layer and the first functional layer between adjacent inductor coils on the substrate device), the spacing between adjacent inductor coils on the substrate device in the Z direction can also be equal to, or even greater than, the spacing between adjacent inductor coils on the substrate.

[0089] The substrate and the substrate device can either select the same substrate parameters or different substrate parameters.

[0090] In some embodiments, to meet the requirements of the inductance value of the inductor, since the number of layers of the second functional layer in the substrate is limited, the substrate usually increases the substrate area to set an inductor with a larger winding area in the substrate, so as to meet the requirements of the inductance value of the inductor, but this will cause the problem of the overall area of the radio frequency front-end chip becoming larger. In the substrate device provided by the present disclosure, the number of layers of the first insulating layer 110 and the first functional layer 120 can be flexibly set without being limited by the number of layers of the substrate, so as to meet the inductors with various inductance values required by the radio frequency front-end chip.

[0091] Figure 8 FIG. is a schematic structural diagram of a semiconductor package provided by an embodiment of the present disclosure. As Figure 8 shown, the semiconductor package includes the substrate device 100 in any of the above embodiments; and, a substrate 200; the substrate device 100 is disposed on the substrate 200.

[0092] In some embodiments, the substrate 200 includes opposite first surface 201 and second surface 202, and pads (Pad) 204 exposed through a solder mask layer 203 are included on the first surface 201 and the second surface 202. The semiconductor package further includes solder balls 104 and solder balls 205 attached to the pads 204. The solder balls 104 can mount the substrate devices 100a and 100b on the substrate 200, and the solder balls 205 can realize electrical connection between the substrate 200 and other devices. Among them, the solder balls 104 and the solder balls 205 can also be replaced by other connection structures, such as connecting wires, etc.

[0093] It should be noted that the pads 204 are exposed through the solder mask layer 203 on the surface of the substrate 200. The material of the pads 204 can include copper, nickel, stainless steel or beryllium copper. The materials of the solder balls 104 and the solder balls 205 can include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), Cu, silver (Ag), zinc (Zn), lead (Pb) and / or their alloys. It should be noted that the materials of the solder balls 104 and the solder balls 205 can be the same or different.

[0094] In some embodiments, the semiconductor package includes a plurality of substrate devices 100.

[0095] As Figure 8 shown, the substrate devices 100a and 100b are disposed on the first surface 201 of the substrate 200 according to the area of the substrate and the layout of other devices on the substrate.

[0096] In some embodiments, at least two of the plurality of substrate devices have different thicknesses; and / or at least two of the plurality of substrate devices have different numbers of layers of the first functional layer.

[0097] In some embodiments, the thickness of substrate device 100a is different from that of substrate device 100b. When the process parameters of the two substrate devices are the same, the number of stacked layers of substrate device 100a is different from that of substrate device 100b. In this way, substrate devices with different inductance values can be provided on the substrate as needed. In some embodiments, the number of layers of multiple substrate devices is different to form inductors with different numbers of inductance coils in the multiple substrate devices, so as to form substrate devices with different inductance values.

[0098] In some embodiments, the thickness of substrate device 100a is different from that of substrate device 100b. When the process parameters of the two substrate devices are different, the number of layers of the first functional layer of substrate device 100a may be the same as or different from that of the first functional layer of substrate device 100b.

[0099] In some embodiments, the number of layers of the first functional layer of substrate device 100a is different from that of the first functional layer of substrate device 100b. When the process parameters of the two substrate devices are different, the thickness of substrate device 100a may be the same as or different from that of substrate device 100b.

[0100] In some embodiments, the number of layers of the first functional layer of substrate device 100a is different from that of the first functional layer of substrate device 100b. When the process parameters of the two substrate devices are the same, the thickness of substrate device 100a may be the same as that of substrate device 100b.

[0101] It should be noted that the thicknesses of the first functional layer and / or the first insulating layer of different substrate devices may also be different; in addition, the areas of the inductance coils of the inductors embedded in different substrate devices may be the same or different. When the coil areas are different, the inductors in the substrate devices can have the same inductance value by different numbers of coil layers.

[0102] In some embodiments, substrate 200 includes a second insulating layer 210 and a second functional layer 220 that are alternately stacked; the thickness of substrate device 100 is greater than the thickness of substrate 200, and / or the number of layers of the first functional layer 120 of substrate device 100 is greater than the number of layers of the second functional layer 220 of substrate 200.

[0103] The number of stacked layers of the substrate 200 is often set according to the circuit complexity, and the number of its stacked layers is limited. The substrate device 100, as a device structure, is disposed on the substrate 200, and the number of its stacked layers can be more than that of the substrate 200 and can be set more flexibly. In this way, a structure thicker than the substrate 200 can be formed, enabling the inductor in the substrate device 100 to have a larger inductance value. In addition, the position of the substrate device can also be set as needed, and the spacing between multiple substrate devices having inductors can be increased to reduce coupling.

[0104] In some embodiments, the number of layers of the first functional layer 120 of the substrate device 100 is greater than the number of layers of the second functional layer 220 of the substrate 200. Since the thickness of the first insulating layer 110 in the substrate device 100 can be less than the thickness of the second insulating layer 210 in the substrate 200, and since the thickness of the first functional layer 120 in the substrate device 100 can be less than the thickness of the second functional layer 220 in the substrate 200, the thickness of the substrate device 100 can be less than or equal to the thickness of the substrate 200.

[0105] In some embodiments, on the XOY plane, the area of the substrate device 100 is smaller than the area of the substrate 200. The inductance value of the inductor in the substrate device can be increased by increasing the number of layers of the inductor coil or changing the process parameters of the substrate device. Therefore, the area of the inductor coil can be within a smaller range, making the area of the substrate device smaller than the area of the substrate.

[0106] In some embodiments, the substrate 200 includes alternately stacked second insulating layers 210 and second functional layers 220; the thickness of the first insulating layer 110 is less than the thickness of the second insulating layer 210, and / or the thickness of the first functional layer 120 is less than the thickness of the second functional layer 220.

[0107] In other embodiments, the thickness of the first insulating layer can also be equal to or greater than the thickness of the second insulating layer, and / or the thickness of the first functional layer is equal to or greater than the thickness of the second functional layer.

[0108] In some embodiments, the substrate device 100 further includes a first connection hole for connecting the inductor coils on adjacent first functional layers; the substrate 200 further includes a second connection hole 230 for connecting the wiring patterns 221 on adjacent second functional layers; the size of the first connection hole is smaller than the size of the second connection hole 230.

[0109] In other embodiments, the second connection hole is also used to connect the inductor coils on adjacent second functional layers.

[0110] In some embodiments, since the first connection hole and the second connection hole are through holes with a larger upper part and a smaller lower part formed by chemical etching using a mask, and the thickness of the first insulating layer is less than that of the second insulating layer, the opening size of the first connection hole is smaller than that of the second connection hole.

[0111] In some embodiments, it further includes a semiconductor chip, and the semiconductor chip and / or the substrate device are arranged side by side on the substrate; and / or, the semiconductor chip and / or the substrate device are stacked on the substrate.

[0112] In some embodiments, the semiconductor chip and / or the substrate device are arranged side by side on the substrate, that is, at least two devices arranged on the substrate are arranged side by side. For example, two semiconductor chips, or two substrate devices, or one semiconductor chip and one substrate device are arranged side by side on the substrate.

[0113] In some embodiments, the semiconductor chip and / or the substrate device are stacked on the substrate, that is, at least two devices arranged on the substrate are stacked. For example, two semiconductor chips, or two substrate devices, or one semiconductor chip and one substrate device are stacked on the substrate.

[0114] In some embodiments, the semiconductor chip and / or the substrate device are arranged side by side on the substrate, and the semiconductor chip and / or the substrate device are stacked on the substrate, that is, the devices arranged on the substrate can be arranged side by side or stacked.

[0115] Any two of the semiconductor chip, the substrate device, and the substrate can be electrically connected through solder balls. For example, the semiconductor chip is arranged on the substrate device or the substrate using solder balls, or the substrate device is arranged on the semiconductor chip or the substrate using solder balls. In other embodiments, connection can also be made through methods such as SMT or connecting wires.

[0116] In some embodiments, there is a first cavity 302 between the semiconductor chip 300 and the substrate 200; there is a second cavity 106 between the substrate device 100 and the substrate 200.

[0117] In some embodiments, the semiconductor package further includes a molding layer 400. The molding layer 400 is used to encapsulate the substrate device 100 and the semiconductor chip 300. The molding layer 400 does not cover at least one electrical connection area between the semiconductor chip 300 and the substrate 200, so as to form a first cavity 302 between the semiconductor chip 300 and the substrate 200.

[0118] In some embodiments, the semiconductor chip is a chip with a cavity, such as a bulk acoustic wave resonator chip, a surface acoustic wave resonator chip, or one or more of bulk acoustic wave filter chips. When packaging a chip with a cavity, it is necessary to retain its cavity to avoid the molding layer 400 affecting the performance of the chip with a cavity. Therefore, in some embodiments, the first cavity 302 formed by the solder ball 301 can retain the cavity structure in the chip. In other embodiments, the first cavity can also be formed by other connection structures, and the present disclosure does not limit this. The material of the solder ball 301 may include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), Cu, silver (Ag), zinc (Zn), lead (Pb), and / or their alloys. It should be noted that the materials of the solder ball 301, the solder ball 104, and the solder ball 205 may be the same or different.

[0119] In some embodiments, it further includes: a conductive post 303 located between the semiconductor chip 300 and the substrate 200, and the conductive post 303 is used to control the height of the first cavity 302 in the stacking direction; the stacking direction is the stacking direction of the first insulating layer and the first functional layer.

[0120] In some embodiments, the semiconductor chip 300 is connected to the substrate 200 through the conductive post 303. Since the height of the conductive post 303 is controllable, it is beneficial to control the height of the first cavity 302 and can further avoid the semiconductor chip from being contaminated.

[0121] In some embodiments, the molding layer 400 does not cover at least one electrical connection area between the substrate device 100 and the substrate 200, so as to form a second cavity 106 between the substrate device 100 and the substrate 200.

[0122] Through the solder ball 104 between the substrate device and the substrate, the molding layer 400 is made not to cover the area where the substrate device 100 is electrically connected to the substrate 200, so as to form the second cavity 106. Since the substrate device has a second cavity and its first surface is not entirely mounted on the substrate, its welding area is small, and it can avoid contaminating the semiconductor chip with a cavity. Among them, the connection structure can be a solder ball or other connection structures, such as connecting wires, conductive posts, etc.

[0123] It should be noted that Figures 1 to 8 the unmarked parts in the present disclosure can be shared with each other.

[0124] It should be pointed out here that: the description of the above semiconductor package is similar to the description of the above substrate device embodiment and has similar beneficial effects to the substrate device embodiment. For the technical details not disclosed in the semiconductor package embodiment of the present disclosure, please refer to the description of the substrate device embodiment of the present disclosure for understanding.

[0125] Embodiments of the present disclosure provide a substrate device and a semiconductor package. The substrate device includes: a first insulating layer and a first functional layer with a metal pattern that are alternately stacked; the metal pattern includes an inductor coil, and the substrate device is configured to be disposed on a substrate. The substrate device in the embodiments of the present disclosure includes a first functional layer with a metal pattern, wherein the metal pattern includes an inductor coil. By alternately stacking the first insulating layer and the first functional layer with a metal pattern, a substrate device with a large inductance value is provided, so that embedding the inductor inside the substrate can be avoided from affecting the thickness or area of the substrate.

[0126] It should be understood that the phrase "one embodiment" or "an embodiment" mentioned throughout the specification means that a particular feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present disclosure. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the order numbers of the above processes do not mean the order of execution is prior or posterior. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0127] The above are only the preferred embodiments of the present disclosure, and do not limit the patent scope of the present disclosure accordingly. Any equivalent structural transformation made by using the content of the specification and drawings of the present disclosure under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields, is included in the patent protection scope of the present disclosure.

Claims

1. A substrate device, characterized in that: include: A first insulating layer and a first functional layer having a metal pattern are alternately stacked; the metal pattern comprises an inductor coil, and the substrate device is used to be arranged on a substrate.

2. The substrate device according to claim 1, characterized in that: The substrate includes a plurality of second functional layers, wherein the second functional layers include wiring patterns; Along the stacking direction, a distance between adjacent first functional layers on the substrate device is smaller than a distance between adjacent second functional layers on the substrate, and the stacking direction is the stacking direction of the first insulating layer and the first functional layer.

3. The substrate device according to claim 1, characterized in that: The substrate device is formed by a substrate process.

4. The substrate device according to claim 1, characterized in that: The metal pattern includes a plurality of inductor coils.

5. The substrate device according to claim 4, characterized in that: At least two of the plurality of inductor coils have different areas.

6. The substrate device according to claim 1, characterized in that: The metal pattern also includes a capacitor plate and / or a balun.

7. The substrate device according to claim 1, characterized in that: A plurality of solder balls are disposed on the first surface of the substrate device along a stacking direction, and the stacking direction is a stacking direction of the first insulating layer and the first functional layer.

8. A semiconductor package, characterized in that: A substrate device comprising any one of claims 1 to 7; and a substrate; The substrate device is arranged on the substrate.

9. The semiconductor package according to claim 8, wherein: The invention comprises a plurality of the substrate devices.

10. The semiconductor package according to claim 8, wherein The substrate comprises a second insulating layer and a second functional layer which are alternately stacked; The thickness of the substrate component is greater than the thickness of the substrate, and / or the number of layers of the first functional layer of the substrate component is greater than the number of layers of the second functional layer of the substrate.

11. The semiconductor package according to claim 9, wherein: At least two of the plurality of substrate devices have different thicknesses; And / or at least two of the plurality of substrate devices have different numbers of layers of the first functional layer.

12. The semiconductor package according to claim 8, wherein: The substrate comprises a second insulating layer and a second functional layer which are alternately stacked; The thickness of the first insulating layer is smaller than the thickness of the second insulating layer, and / or the thickness of the first functional layer is smaller than the thickness of the second functional layer.

13. The semiconductor package according to claim 8, wherein: The substrate device further comprises a first connection hole, wherein the first connection hole is used to connect the inductor coil on the adjacent first functional layer; The substrate includes second insulating layers and second functional layers alternately stacked, and second connecting holes, wherein the second connecting holes are used to connect wiring patterns on adjacent second functional layers; and the size of the first connecting holes is smaller than that of the second connecting holes.

14. The semiconductor package according to claim 8, wherein: It also includes a semiconductor chip, wherein the semiconductor chip and / or the substrate device are arranged in parallel on the substrate; And / or, the semiconductor chip and / or the substrate device are stacked and arranged on the substrate.

15. The semiconductor package according to claim 14, wherein: A first cavity is provided between the semiconductor chip and the substrate; a second cavity is provided between the substrate device and the substrate.

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