Practical pacing pulse detection circuit

Abstract

The utility model discloses a practical pacing pulse detection circuit which comprises an electrocardio pre-amplifier circuit, a high-pass filter circuit, an amplifier circuit, a programmable window comparator circuit, an OR operation logic gate circuit and a single-chip microcomputer which are connected in sequence, and the single-chip microcomputer is connected with the programmable window comparator circuit. The electrocardio pre-amplifier comprises a differential input amplification circuit, an instrument amplifier circuit and an input filter circuit, the differential input amplification circuit is connected with the input filter circuit, and the instrument amplifier circuit is connected with the differential input amplification circuit. The utility model has the beneficial effects that the problem of missing detection is effectively avoided, the reliability is improved, the problem that the resources are occupied when the pace-making pulse is detected by software is solved, the occupied resources are less, and the additional resources of the single chip microcomputer are not occupied.

Description

Technical Field

[0001] The utility model relates to the technical field of medical detection instruments, and particularly relates to a practical pacing pulse detection circuit. Background Art

[0002] A cardiac pacemaker is an electronic therapeutic instrument implanted in the body. The cardiac pacemaker generates electrical pulses through a pulse generator to stimulate the myocardium contacted by the electrodes, so that the heart is excited and contracts, thereby treating heart diseases caused by arrhythmia.

[0003] Since the first cardiac pacemaker was implanted in the human body in 1958, the manufacturing technology and process of cardiac pacemakers have developed rapidly, and the functions have become increasingly perfect, successfully treating bradyarrhythmia and saving the lives of thousands of patients. When a patient implanted with an electrocardiogram pacemaker needs to check the electrocardiogram, an electrocardiograph with the ability to display pacing pulses is required for the examination. The electrocardiogram of a patient implanted with an electrocardiogram pacemaker is medically called a pacing electrocardiogram. For an electrocardiograph to have the ability to display pacing pulses, it needs to have the ability to detect pacing pulses. Pacing pulse detection generally has software and hardware detection methods. The software detection method is generally achieved through high sampling rates and algorithms. For pacing pulses with a pulse width of 0.1 - 2 mS, the sampling rate needs to reach more than 10 ksps, that is, more than 10,000 samples per second. The high sampling rate generates a large amount of data that needs to be processed, so the software detection of pacing pulses has relatively high requirements for the processor. It is very difficult to detect pacing pulses through software for a dynamic electrocardiograph with a small volume and a long acquisition time of 24 hours. The main reasons are as follows:

[0004] 1. Most dynamic electrocardiographs are powered by a single AA alkaline battery. To continuously collect the electrocardiogram of a patient for 24 hours without interruption, low power consumption is required. However, the higher the sampling rate, the higher the power consumption.

[0005] 2. In order to reduce power consumption, the single-chip microcomputers used in dynamic electrocardiographs are mostly low-power single-chip microcomputers with weak performance. It is generally difficult for ordinary low-power single-chip microcomputers to perform filtering and calculation processing on data with a high sampling rate of >10 ksps.

[0006] 3. With a sampling rate as high as >10 ksps, a large amount of data will be generated, making it difficult to achieve storage and reading.

[0007] Therefore, it can be seen that the existing pacing pulse detection circuit has the following deficiencies:

[0008] 1. The method of software detection of pacing pulses mostly uses a high sampling rate of 16 ksps and algorithms to achieve, which has relatively high requirements for the performance of the processor, high power consumption, and a large amount of data, and it is difficult to meet the requirements of low-power dynamic electrocardiographs.

[0009] 2. Ordinary hardware pacing detection circuits are complex in circuit, poor in flexibility, difficult to adapt to constantly changing pacing pulse signals, and have poor reliability. Summary of the Invention

[0010] The purpose of the present utility model is to provide a practical pacing pulse detection circuit to solve the problems raised in the above-mentioned background technology.

[0011] To achieve the above purpose, the present utility model provides the following technical solution: A practical pacing pulse detection circuit includes an electrocardiogram preamplifier circuit, a high-pass filter circuit, an amplifier circuit, a programmable window comparator circuit, an OR operation logic gate circuit, and a single-chip microcomputer connected in sequence, and the single-chip microcomputer is connected to the programmable window comparator circuit;

[0012] The electrocardiogram preamplifier includes a differential input amplifier circuit, an instrumentation amplifier circuit, and an input filter circuit. The differential input amplifier circuit is connected to the input filter circuit, and the instrumentation amplifier circuit is connected to the differential input amplifier circuit.

[0013] Preferably, the differential input amplifier circuit includes amplifier U6A, amplifier U6B, resistor R28, resistor R33, and resistor R34. Resistor R34 is connected to the inverting input terminals of amplifier U6A and amplifier U6B. Resistor R28 is connected to the inverting input terminal and the output terminal of amplifier U6B. Resistor R33 is connected to the inverting input terminal and the output terminal of amplifier U6A.

[0014] Preferably, the input filter circuit includes resistor R24, resistor R25, capacitor C33, capacitor C34, and capacitor C35. Resistor R24 is connected to the non-inverting input terminal of amplifier U6A. Resistor R25 is connected to the non-inverting input terminal of amplifier U6B. One end of capacitor C33 and capacitor C34 are connected together, and the other ends of capacitor C33 and capacitor C34 are respectively connected to the non-inverting input terminals of amplifier U6A and amplifier U6B. Both ends of capacitor C35 are respectively connected to the non-inverting input terminals of amplifier U6A and amplifier U6B.

[0015] Preferably, the instrumentation amplifier circuit includes amplifier U9, resistor R17, and resistor R18. The inverting input terminal of amplifier U9 is connected to the output terminal of amplifier U6A. The non-inverting input terminal of amplifier U9 is connected to the output terminal of amplifier U6B. Resistor R17 and resistor R18 are connected in series with the first pin and the eighth pin of amplifier U9.

[0016] Preferably, the high-pass filter circuit includes resistor R19 and capacitor C29. One end of resistor R19 is connected to one end of capacitor C29.

[0017] Preferably, the amplifier circuit includes an amplifier U10A, a resistor R21, and a resistor R22. The resistor R21 is connected to the inverting input terminal of the amplifier U10A, and the resistor R22 is connected to the inverting input terminal and the output terminal of the amplifier U10A.

[0018] Preferably, the programmable window comparator circuit includes an amplifier U10B, an amplifier U10C, a capacitor C31, and a capacitor C32. The non-inverting input terminal of the amplifier U10B is connected to the DAC1 port of the single-chip microcomputer. The inverting input terminal of the amplifier U10C is connected to the DAC2 port of the single-chip microcomputer. The capacitor C31 is connected to the non-inverting input terminal of the amplifier U10B, and the capacitor C32 is connected to the inverting input terminal of the amplifier U10C.

[0019] Preferably, the OR logic gate circuit includes a diode D1, a diode D2, and a resistor R28. The anode of the diode D1 is connected to the output terminal of the amplifier U10B, the anode of the diode D2 is connected to the output terminal of the amplifier U10C, and the cathodes of the diode D1 and the diode D2 are commonly grounded through the resistor R28.

[0020] Preferably, the single-chip microcomputer selects a 32-bit Cortex-M0+ microcontroller with the model number APM32F072C8T6.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0022] 1. In the present invention, the detected pacing pulse signal is connected to the interrupt input pin or the capture pin of the single-chip microcomputer and processed by the external interrupt peripheral or the capture peripheral of the single-chip microcomputer, effectively avoiding the problem of missed detection. It does not occupy additional resources of the single-chip microcomputer and improves reliability.

[0023] 2. Since the pacing pulse range of the present invention is 0.1mS to 2mS, which is relatively narrow, it is more appropriate to use interrupt edge triggering. After triggering, an interrupt signal is generated, and the single-chip microcomputer processes it after the interrupt is generated. In this way, less storage resources are occupied. Or use the capture peripheral. The capture peripheral can automatically capture a pulse signal and generate an interrupt, and then the single-chip microcomputer processes it. Similarly, less resources are occupied.

[0024] 3. The structural design of the present invention is simple, and both the production and use costs can be effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the circuit module of the present invention;

[0026] Figure 2 It is a schematic circuit diagram of the ECG preamplifier of the present invention;

[0027] Figure 3The circuit schematic diagram in some embodiments of the present utility model. Detailed implementation manners

[0028] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the protection scope of the present utility model.

[0029] Please refer to Figures 1 to 3 , the present utility model provides a technical solution: a practical pacing pulse detection circuit, including an electrocardiogram preamplifier circuit 100, a high-pass filter circuit 200, an amplifier circuit 300, a programmable window comparator circuit 400, an OR operation logic gate circuit 500, and a single-chip microcomputer 600 connected in sequence. The single-chip microcomputer 600 is connected to the programmable window comparator circuit 500;

[0030] Please refer to Figure 2 , in some embodiments of the present utility model, the electrocardiogram preamplifier circuit 100 includes a differential input amplifier circuit 101, an instrumentation amplifier circuit 102, and an input filter circuit 103. The differential input amplifier circuit 101 is connected to the input filter circuit 103, and the instrumentation amplifier circuit 102 is connected to the differential input amplifier circuit 101.

[0031] Specifically, the differential input amplifier circuit 101 includes an amplifier U6A, an amplifier U6B, a resistor R28, a resistor R33, and a resistor R34. The resistor R34 is connected to the inverting input terminals of the amplifier U6A and the amplifier U6B. The resistor R28 is connected to the inverting input terminal and the output terminal of the amplifier U6B. The resistor R33 is connected to the inverting input terminal and the output terminal of the amplifier U6A.

[0032] Specifically, the input filter circuit includes a resistor R24, a resistor R25, a capacitor C33, a capacitor C34, and a capacitor C35. The resistor R24 is connected to the non-inverting input terminal of the amplifier U6A. The resistor R25 is connected to the non-inverting input terminal of the amplifier U6B. One ends of the capacitor C33 and the capacitor C34 are connected together. The other ends of the capacitor C33 and the capacitor C34 are respectively connected to the non-inverting input terminals of the amplifier U6A and the amplifier U6B. Both ends of the capacitor C35 are respectively connected to the non-inverting input terminals of the amplifier U6A and the amplifier U6B.

[0033] Specifically, the instrumentation amplifier circuit includes amplifier U9, resistor R17, and resistor R18. The inverting input terminal of amplifier U9 is connected to the output terminal of amplifier U6A, and the non-inverting input terminal of amplifier U9 is connected to the output terminal of amplifier U6B. Resistor R17 and resistor R18 are connected in series with the first pin and the eighth pin of amplifier U9 to form a gain circuit.

[0034] In this embodiment, since the ECG acquisition circuit requires a high common-mode rejection ratio, and the common-mode rejection ratio is related to the gain of the circuit, the higher the gain, the higher the circuit rejection ratio. However, the ECG acquisition circuit needs to consider the influence of the ±300mV polarization voltage. The gain of the input stage cannot be too high, otherwise the polarization voltage will saturate the input stage. Therefore, the gain of the input differential stage of the differential input amplifier circuit 101 in this embodiment is set to 8 times, and the gain of the amplification stage composed of the instrumentation amplifier circuit 102 is set to 50 times, which not only overcomes the influence of the polarization voltage but also ensures a common-mode rejection ratio of >90dB.

[0035] In some embodiments of the present invention, the high-pass filter circuit 200 includes resistor R19 and capacitor C29. One end of resistor R19 is connected to one end of capacitor C19.

[0036] In this embodiment, the ECG waveform can be effectively filtered out by resistor R19 and capacitor C29.

[0037] In some embodiments of the present invention, the amplifier circuit 300 includes amplifier U10A, resistor R21, and resistor R22. Resistor R21 is connected to the inverting input terminal of amplifier U10A, and resistor R22 is connected to the inverting input terminal and the output terminal of amplifier U10A.

[0038] Specifically, the non-inverting input terminal of amplifier U10A is connected to the high-pass filter circuit 200 through resistor R20.

[0039] Specifically, the 11th pin of amplifier U10A is connected to the power supply and connected to filter capacitor C28, and a capacitor C30 is also connected between the inverting input terminal and the output terminal of amplifier U10A.

[0040] In this embodiment, amplifier U10A, resistor R21, and resistor R22 form an amplifier circuit to amplify the ECG pacing pulse. The ECG preamplifier circuit 100 plus the amplifier circuit 300 amplify the ECG pacing pulse by about 12 times, ensuring that a 2mV pacing pulse can be effectively recognized by the programmable window comparator circuit 400 and that a 250mV pacing pulse signal is not saturated.

[0041] In some embodiments of the present utility model, the programmable window comparator circuit 400 includes an amplifier U10B, an amplifier U10C, a capacitor C31, and a capacitor C32. The capacitor C31 and the capacitor C32 form a filtering circuit. The non-inverting input terminal of the amplifier U10B is connected to the DAC1 port of the single-chip microcomputer, the inverting input terminal of the amplifier U10C is connected to the DAC2 port of the single-chip microcomputer, the capacitor C31 is connected to the non-inverting input terminal of the amplifier U10B, and the capacitor C32 is connected to the inverting input terminal of the amplifier U10C.

[0042] In this embodiment, the amplifier U10B, the amplifier U10C, the two-way DAC outputs DAC1 and DAC2 of the single-chip microcomputer 600, and the filtering circuit composed of the capacitor C31 and the capacitor C32 together form an adjustable window comparator circuit 400. The signal within the comparison window VBIS - Vadj, VBIS + Vadj is not a pacing pulse signal. The signal exceeding VBIS + Vadj or lower than BIS - Vadj will be considered as a pacing pulse signal, and a high level is output after being compared by the comparator. VBIS - Vadj and VBIS + Vadj are generated by the DAC of the single-chip microcomputer, and the single-chip microcomputer 600 can adjust the comparison window to adapt to various forms of pacing pulses.

[0043] In some embodiments of the present utility model, the OR logic gate circuit 500 includes a diode D1, a diode D2, and a resistor R28. The anode of the diode D1 is connected to the output terminal of the amplifier U10B, the anode of the diode D2 is connected to the output terminal of the amplifier U10C, and the cathodes of the diode D1 and the diode D2 are commonly grounded through the resistor R28.

[0044] In this embodiment, the diode D1, the diode D2, and the circuit R28 form an OR logic gate circuit. The output signal of the previous-stage programmable window comparator is output to the interrupt or capture input pin of the single-chip microcomputer after passing through the OR gate, and the pacing pulse is detected by the hardware interrupt peripheral or capture peripheral of the single-chip microcomputer, effectively avoiding the problem of losing the pacing pulse.

[0045] In some embodiments of the present utility model, the single-chip microcomputer 600 selects a microcontroller with the model APM32F072C8T6.

[0046] Although the embodiments of the present utility model have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirits of the present utility model. The scope of the present utility model is defined by the appended claims and their equivalents.

Claims

1. A practical pacing pulse detection circuit, characterized in that: It includes an ECG preamplifier circuit, a high-pass filter circuit, an amplifier circuit, a programmable window comparator circuit, an OR operation logic gate circuit and a single-chip microcomputer which are connected in sequence, and the single-chip microcomputer is connected to the programmable window comparator circuit; The ECG preamplifier comprises a differential input amplifier circuit, an instrument amplifier circuit and an input filter circuit, wherein the differential input amplifier circuit is connected to the input filter circuit, and the instrument amplifier circuit is connected to the differential input amplifier circuit; The programmable window comparator circuit includes an amplifier U10B, an amplifier U10C, a capacitor C31 and a capacitor C32. The positive input end of the amplifier U10B is connected to the DAC1 port of the single-chip microcomputer, the negative input end of the amplifier U10C is connected to the DAC2 port of the single-chip microcomputer, the capacitor C31 is connected to the positive input end of the amplifier U10B, and the capacitor C32 is connected to the negative input end of the amplifier U10C.

2. A practical pacing pulse detection circuit according to claim 1, characterized in that: The differential input amplifier circuit includes an amplifier U6A, an amplifier U6B, a resistor R28, a resistor R33 and a resistor R34, wherein the resistor R34 is connected to the reverse input terminals of the amplifier U6A and the amplifier U6B, the resistor R28 is connected to the reverse input terminal and the output terminal of the amplifier U6B, and the resistor R33 is connected to the reverse input terminal and the output terminal of the amplifier U6A.

3. A practical pacing pulse detection circuit according to claim 2, characterized in that: The input filter circuit includes a resistor R24, a resistor R25, a capacitor C33, a capacitor C34 and a capacitor C35. The resistor R24 ​​is connected to the non-inverting input terminal of the amplifier U6A, the resistor R25 is connected to the non-inverting input terminal of the amplifier U6B, one end of the capacitor C33 and the capacitor C34 are connected, and the other ends of the capacitor C33 and the capacitor C34 are respectively connected to the non-inverting input terminals of the amplifier U6A and the amplifier U6B, and the two ends of the capacitor C35 are respectively connected to the non-inverting input terminals of the amplifier U6A and the amplifier U6B.

4. A practical pacing pulse detection circuit according to claim 3, characterized in that: The instrument amplifier circuit includes an amplifier U9, a resistor R17 and a resistor R18, the reverse input end of the amplifier U9 is connected to the output end of the amplifier U6A, the forward input end of the amplifier U9 is connected to the output end of the amplifier U6B, and the resistor R17 and the resistor R18 are connected in series with the 1st pin and the 8th pin of the amplifier U9.

5. A practical pacing pulse detection circuit according to claim 4, characterized in that: The high-pass filter circuit includes a resistor R19 and a capacitor C29, and one end of the resistor R19 is connected to one end of the capacitor C29.

6. A practical pacing pulse detection circuit according to claim 5, characterized in that: The amplifying circuit includes an amplifier U10A, a resistor R21 and a resistor R22. The resistor R21 is connected to the inverting input terminal of the amplifier U10A, and the resistor R22 is connected to the inverting input terminal and the output terminal of the amplifier U10A.

7. A practical pacing pulse detection circuit according to claim 6, characterized in that: The OR operation logic gate circuit includes a diode D1, a diode D2 and a resistor R28, the anode of the diode D1 is connected to the output end of the amplifier U10B, the anode of the diode D2 is connected to the output end of the amplifier U10C, and the cathodes of the diode D1 and the diode D2 are grounded together through the resistor R28.

8. A practical pacing pulse detection circuit according to claim 7, characterized in that: The single chip microcomputer uses a 32-bit Cortex-M0+ microcontroller of model APM32F072C8T6.

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