Application circuit and application system of LED video processor clock
By sharing one external crystal oscillator with two PHY chips and using the PLL clock output characteristics, the problems of large consumption and high cost of FPGA resources in the prior art are solved, and the stable clock source supply and cost reduction are achieved.
Patent Information
- Application Number
- CN202421666448.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-12
- Publication Date
- 2025-06-10
- Estimated Expiration
- 2034-07-12
AI Technical Summary
The PHY chip clock source of the existing LED video processor consumes too much FPGA resources, affecting system stability. At the same time, LED video processors above 8 network ports require a large number of external crystal oscillators, resulting in excessive cost.
The two PHY chips share one external crystal oscillator, and use the PLL clock output characteristics of the PHY chip itself to provide different clock sources to the second PHY chip, reducing the usage of external crystal oscillator and reducing costs.
It has achieved the reduction of the usage of plug-in crystal oscillator by half, reducing costs, and at the same time, it provides a stable external clock source for the PHY chip, reducing the logic consumption brought by the PHY chip PLL output clock, and improving system stability.
Smart Images
Figure CN222967012U_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present utility model relate to the technical field of LED video processors, and particularly to an application circuit and an application system for the clock of an LED video processor. Background Art
[0002] At present, the clock source of the PHY chip in the LED video processor is mainly provided by the PLL frequency division of the FPGA chip or each PHY is externally equipped with a 25M crystal oscillator. The clock source provided by the PLL frequency division of the FPGA chip is affected by the wiring, resulting in poor accuracy consistency and large consumption of the FPGA's own logic, which is not conducive to the stability of the FPGA minimum system. In addition, in the application of multi-network port processors, the number of PHY chips is generally more than 4, and some even up to 20. Each PHY chip needs to input an external clock source to operate, and generally, the FPGA chip can output at most 8 paths of clocks for the PHY chips. If there are more than 8 network ports, 20 external crystal oscillators are required to provide the clock source, and the required number of crystal oscillators is large and the cost is high. Summary of the Utility Model
[0003] The present utility model provides an application circuit and an application system for the clock of an LED video processor, which reduces the usage of external crystal oscillators by half, reduces the cost, and at the same time provides a stable clock source for external input to the PHY chip, reducing the logic consumption brought by the PLL output clock of the PHY chip.
[0004] According to one aspect of the present utility model, an application circuit for the clock of an LED video processor is provided. The application circuit for the clock of an LED video processor includes: a first PHY chip, a second PHY chip, and a first crystal oscillator;
[0005] The first PHY chip is connected to the first crystal oscillator, and the first crystal oscillator is used to provide a clock source for the first PHY chip;
[0006] The second PHY chip is connected between the first crystal oscillator and the first PHY chip. The first crystal oscillator or the first PHY chip is used to provide a clock source for the second PHY chip, and the first PHY chip and the second PHY chip are used to communicate with an external multi-network port processor.
[0007] Optionally, the application circuit for the clock of an LED video processor further includes a second crystal oscillator. The second crystal oscillator is connected between the first crystal oscillator and the second PHY chip, and the second crystal oscillator is used to provide a clock source for the second PHY chip.
[0008] Optionally, the application circuit for the clock of an LED video processor further includes a twenty-seventh resistor and a twenty-eighth resistor;
[0009] The first end of the twenty-seventh resistor is connected to the third end of the first crystal oscillator. The first end of the twenty-eighth resistor is connected to the thirty-fifth pin of the first PHY chip. The second end of the twenty-seventh resistor and the second end of the twenty-eighth resistor are connected and then connected to the third end of the second crystal oscillator.
[0010] Optionally, the application circuit of the LED video processor clock further includes a twenty-fifth resistor and a twenty-sixth resistor;
[0011] The first end of the twenty-fifth resistor is grounded. The second end of the twenty-fifth resistor is connected to the first end of the second crystal oscillator. The first end of the twenty-sixth resistor is connected to the third end of the second crystal oscillator. The second end of the twenty-sixth resistor is connected to the third end of the first crystal oscillator.
[0012] Optionally, the application circuit of the LED video processor clock further includes a seventeenth capacitor and an eighteenth capacitor;
[0013] The first end of the seventeenth capacitor is connected to the first end of the first crystal oscillator. The second end of the seventeenth capacitor is grounded. The first end of the eighteenth capacitor is connected to the third end of the first crystal oscillator. The second end of the eighteenth capacitor is grounded.
[0014] Optionally, the application circuit of the LED video processor clock further includes a first capacitor and a second capacitor; the first end of the first capacitor is connected to the first end of the second crystal oscillator. The second end of the first capacitor is grounded. The first end of the second capacitor is connected to the third end of the second crystal oscillator. The second end of the second capacitor is grounded.
[0015] Optionally, the operating frequency of the first crystal oscillator includes 25 MHz.
[0016] Optionally, the operating frequency of the second crystal oscillator includes 25 MHz.
[0017] Optionally, the models of the first PHY chip and the second PHY chip include at least one of RTL8211FD, RTL8211FP, and YT8531P.
[0018] According to another aspect of the present invention, there is provided an application system of an LED video processor clock. The application system of the LED video processor clock includes the application circuit of the LED video processor clock according to any one of the above aspects.
[0019] The technical solution of the embodiment of the present utility model utilizes the characteristics that 2 PHY chips share an external crystal oscillator and the PLL clock output of the PHY chips themselves. By changing the attachment method of the crystal oscillator, different clock source inputs are provided to the second PHY chip, reducing the usage of external crystal oscillators by half, reducing costs, and at the same time providing a stable clock source for external input to the PHY chip, reducing the logic consumption caused by the PLL output clock of the PHY chip. In summary, the present utility model solves the problems that the clock source of the existing PHY chip consumes too much FPGA resources and affects the system stability, and that each PHY chip of an LED video processor with more than 8 network ports needs an external independent crystal oscillator, resulting in too high costs.
[0020] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present utility model, nor is it used to limit the scope of the present utility model. Other features of the present utility model will become easily understood through the following description. Brief Description of the Drawings
[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0022] Figure 1 is a schematic structural diagram of an application circuit of an LED video processor clock according to an embodiment of the present utility model;
[0023] Figure 2 is a schematic structural diagram of another application circuit of an LED video processor clock according to an embodiment of the present utility model;
[0024] Figure 3 is an overall circuit schematic diagram of an application circuit of an LED video processor clock according to an embodiment of the present utility model. Detailed Embodiments
[0025] In order to enable those skilled in the art to better understand the solution of the present utility model, the following will clearly and completely describe the technical solutions in the embodiments of the present utility model with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only some of the embodiments of the present utility model, rather than all of them. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.
[0026] It should be noted that the terms "first", "second", etc. in the description, claims and above-mentioned drawings of the present utility model are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present utility model described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.
[0027] Figure 1 is a schematic structural diagram of an application circuit of an LED video processor clock according to an embodiment of the present utility model. Refer to Figure 1 According to an embodiment of the present utility model, an application circuit of an LED video processor clock is provided. The application circuit of the LED video processor clock includes: a first PHY chip 10, a second PHY chip 20, and a first crystal oscillator 30; the first PHY chip 10 is connected to the first crystal oscillator 30, and the first crystal oscillator 30 is used to provide a clock source for the first PHY chip 10; the second PHY chip 20 is connected between the first crystal oscillator 30 and the first PHY chip 10, and the first crystal oscillator 30 or the first PHY chip 10 is used to provide a clock source for the second PHY chip 20. The first PHY chip 10 and the second PHY chip 20 are used to communicate with an external multi-network interface processor. Optionally, the models of the first PHY chip 10 and the second PHY chip 20 include at least one of RTL8211FD, RTL8211FP, and YT8531P.
[0028] Specifically, the first PHY chip 10 and the second PHY chip 20 mainly implement the network interface communication function, and the first crystal oscillator 30 is responsible for providing a clock source for the first PHY chip 10 and the second PHY chip 20. The first PHY chip 10 uses the clock source from the first crystal oscillator 30, and the second PHY chip 20 uses the clock source from the first crystal oscillator 30. This solution is only applicable to PHY chips of the first PHY chip 10 and the second PHY chip 20 with models RTL8211FD and RTL8211FP.
[0029] The first PHY chip 10 uses the clock of the first crystal oscillator 30, and the second PHY chip 20 uses the clock output from the PLL of the 35PIN CLKOUT pin of the first PHY chip 10. This solution is applicable to the PHY chips of model YT8531PP for both the first PHY chip 10 and the second PHY chip 20, and also applicable to the PHY chips of models RTL8211FD and RTL8211FP for both the first PHY chip 10 and the second PHY chip 20.
[0030] Based on the consideration of the working stability of the PHY chip, generally two PHY chips share one clock source. The second PHY chip 20 uses the PLL output clock of the first PHY chip 10 or an externally connected clock. The PLL clock output of the first PHY chip 10 can be used not only as the clock input for the second PHY chip 20, but also as the clock input for an FPGA chip or other chips with lower requirements.
[0031] The technical solution of the embodiment of the present utility model, by utilizing the characteristics of sharing one externally connected crystal oscillator by two PHY chips and the PLL clock output of the PHY chip itself, provides different clock source inputs to the second PHY chip by changing the pasting method of the crystal oscillator, reduces the usage of externally connected crystal oscillators by half, reduces costs, and at the same time provides a stable clock source for external input to the PHY chip, reducing the logic consumption brought by the PLL output clock of the PHY chip. In summary, the present utility model solves the problems that the clock source of the existing PHY chip consumes too much FPGA resources and affects the system stability, and that each PHY chip of an LED video processor with more than 8 network ports needs to be externally connected with an independent crystal oscillator, resulting in too high costs.
[0032] Figure 2 It is a schematic structural diagram of an application circuit of the LED video processor clock provided according to an embodiment of the present utility model. Refer to Figure 2 , optionally, the application circuit of the LED video processor clock further includes a second crystal oscillator 40. The second crystal oscillator 40 is connected between the first crystal oscillator 30 and the second PHY chip 20, and the second crystal oscillator 40 is used to provide a clock source for the second PHY chip 20.
[0033] Continue to refer to Figure 2 , optionally, the operating frequency of the first crystal oscillator 30 includes 25 MHz.
[0034] Continue to refer to Figure 2 , optionally, the operating frequency of the second crystal oscillator 40 includes 25 MHz.
[0035] Specifically, the first crystal oscillator 30 and the second crystal oscillator 40 can be 25 MHz standard clock oscillators. The first PHY chip 10 uses the 25M clock source from the first crystal oscillator 30, and the second PHY chip 20 uses the 25M clock source from the second crystal oscillator 40. This method is the clock circuit currently applied in LED video processors, and the second crystal oscillator 40 is reserved for use.
[0036] Figure 3 is the overall circuit schematic diagram of an application circuit for the clock of an LED video processor provided according to an embodiment of the present invention. Refer to Figure 3 , optionally, the application circuit for the clock of the LED video processor further includes a twenty-seventh resistor R27 and a twenty-eighth resistor R28; the first end of the twenty-seventh resistor R27 is connected to the third terminal 3 of the first crystal oscillator 30, the first end of the twenty-eighth resistor R28 is connected to the thirty-fifth pin 35 of the first PHY chip 10, and the second end of the twenty-seventh resistor R27 is connected to the second end of the twenty-eighth resistor R28 and then connected to the third terminal 3 of the second crystal oscillator 40.
[0037] Continue to refer to Figure 3 , optionally, the application circuit for the clock of the LED video processor further includes a twenty-fifth resistor R25 and a twenty-sixth resistor R26; the first end of the twenty-fifth resistor R25 is grounded, the second end of the twenty-fifth resistor R25 is connected to the first terminal 1 of the second crystal oscillator 40, the first end of the twenty-sixth resistor R26 is connected to the third terminal 3 of the second crystal oscillator 40, and the second end of the twenty-sixth resistor R26 is connected to the third terminal 3 of the first crystal oscillator 30.
[0038] Specifically, the twenty-seventh resistor R27, the twenty-eighth resistor R28, the twenty-fifth resistor R25, and the twenty-sixth resistor R26 are compatible resistors. The compatible resistors are mainly used to select different 25M clock sources when using different PHY chips. The twenty-seventh resistor R27 and the twenty-eighth resistor R28 can be empty-mounted resistors (optional-mounted resistors), and the second crystal oscillator 40 is an empty-mounted crystal oscillator (optional-mounted crystal oscillator). By utilizing the characteristics of sharing one external crystal oscillator by two PHY chips and the PLL clock output of the PHY chip itself, different clock source inputs are provided to the second PHY chip by changing the mounting methods of the first crystal oscillator, the second crystal oscillator, and the compatible resistors. While reducing the usage of external crystal oscillators by half, a stable external input clock source is provided to the PHY chip, reducing the logic consumption brought by the PLL output clock to the FPGA. In addition, by selectively mounting devices, multiple PHY chips such as RTL8211FD, RTL8211FP, and YT8531P can be compatible, and the above PHY chips can be used flexibly without modifying the design.
[0039] The working principle of the application circuit for the clock of the LED video processor:
[0040] Clock Solution 1: The first PHY chip 10 uses the 25M clock source from the first crystal oscillator 30, and the second PHY chip 20 uses the 25M clock source from the second crystal oscillator 40. This method is the clock circuit for the current LED video processor application, and the second crystal oscillator 40 is reserved for use.
[0041] Clock Solution 2: The first PHY chip 10 uses the 25M clock source from the first crystal oscillator 30. R27 and R26 are 0R resistors, R28 is a 0R resistor NC (optional resistor), the second crystal oscillator 40 is NC (optional crystal oscillator), and the second PHY chip 20 uses the 25M clock source from the first crystal oscillator 30. This solution is only applicable to PHY chips of models RTL8211FD and RTL8211FP for the first PHY chip 10 and the second PHY chip 20.
[0042] Clock Solution 3: The first PHY chip 10 uses the 25M clock of the first crystal oscillator 30. R28 and R26 are 0R resistors, R27 is a 0R resistor NC (optional resistor), the second crystal oscillator 40 is NC (optional crystal oscillator), and the second PHY chip 20 uses the 25M clock output from the PLL of the 35PIN CLKOUT pin of the first PHY chip 10. This solution is applicable to PHY chips of model YT8531PP for both the first PHY chip 10 and the second PHY chip 20, and is also applicable to PHY chips of models RTL8211FD and RTL8211FP for the first PHY chip 10 and the second PHY chip 20.
[0043] Other Instructions: Considering the working stability of the PHY chip, generally two PHY chips share one clock source. The second PHY chip 20 uses the PLL output clock of the first PHY chip 10 or an external 25M clock. The PLL clock output of the first PHY chip 10 can be used not only as the clock input for the second PHY chip 20, but also as the clock input for FPGA chips or other chips with lower requirements.
[0044] Continue to refer to Figure 3 , optionally, the application circuit of the LED video processor clock further includes a seventeenth capacitor C17 and an eighteenth capacitor C18; the first end of the seventeenth capacitor C17 is connected to the first end 1 of the first crystal oscillator 30, the second end of the seventeenth capacitor C17 is grounded, the first end of the eighteenth capacitor C18 is connected to the third end 3 of the first crystal oscillator 30, and the second end of the eighteenth capacitor C18 is grounded.
[0045] Continue to refer to Figure 3, optionally, the application circuit of the LED video processor clock further includes a first capacitor C1 and a second capacitor C2; the first end of the first capacitor C1 is connected to the first end 1 of the second crystal oscillator 40, the second end of the first capacitor C1 is grounded, the first end of the second capacitor C2 is connected to the third end 3 of the second crystal oscillator 40, and the second end of the second capacitor C2 is grounded.
[0046] Specifically, the functions of the seventeenth capacitor C17, the eighteenth capacitor C18, the first capacitor C1 and the second capacitor C2: In order to improve the working accuracy and stability of the crystal oscillator, two parallel capacitors are usually connected to both ends of the crystal oscillator chip. One of these two capacitors is connected to the output end of the crystal oscillator chip, and the other is connected to the input end of the crystal oscillator chip to achieve the following functions: Filtering effect: Connecting capacitors can effectively filter out high-frequency clutter and noise signals in the circuit, thereby filtering and smoothing the signals generated by the crystal oscillator. This can improve the stability and accuracy of the signals. Adjusting frequency: By selecting capacitors with different capacitance values, the resonant frequency of the crystal oscillator can be changed, thereby adjusting the output frequency. Energy storage and discharge: The working principle of the crystal oscillator requires that a certain working charge must be provided to the wafer when the crystal vibrates, and at the same time, a certain amount of charge storage will also occur when the crystal oscillates. Connecting capacitors can store and release charges between the crystal oscillation and stop, thereby ensuring the continuous operation of the crystal oscillator.
[0047] It should be noted that Figure 3 the electrical nodes with the same labels in [the figure] are electrically connected, such as BXTALI, BXTALO, BCLKOUT, BCLKOUTB, AXTALI, AXTALO, etc. The network labels with the same text characters in the figure are electrically connected to each other, and this is done to make the drawing clear.
[0048] The embodiment of the present invention provides an application system of an LED video processor clock, and the application system of the LED video processor clock includes the application circuit of the LED video processor clock provided by any embodiment of the present invention.
[0049] Since the application system of the LED video processor clock includes the application circuit of the LED video processor clock provided by any embodiment of the present invention, therefore, the above-mentioned application system of the LED video processor clock has the same beneficial effects as the application circuit of the LED video processor clock, and will not be elaborated here.
[0050] The above specific implementation manners do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.
Claims
1. An application circuit of an LED video processor clock, characterized in that: include: A first PHY chip, a second PHY chip, and a first crystal oscillator; The first PHY chip is connected to the first crystal oscillator, and the first crystal oscillator is used to provide a clock source for the first PHY chip; The second PHY chip is connected between the first crystal oscillator and the first PHY chip. The first crystal oscillator or the first PHY chip is used to provide a clock source for the second PHY chip. The first PHY chip and the second PHY chip are used to communicate with an external multi-network port processor.
2. The circuit according to claim 1, characterized in that It also includes a second crystal oscillator, which is connected between the first crystal oscillator and the second PHY chip, and is used to provide a clock source for the second PHY chip.
3. The circuit according to claim 2, characterized in that Also includes a twenty-seventh resistor and a twenty-eighth resistor; The first end of the twenty-seventh resistor is connected to the third end of the first crystal oscillator, the first end of the twenty-eighth resistor is connected to the thirty-fifth pin of the first PHY chip, and the second end of the twenty-seventh resistor is connected to the second end of the twenty-eighth resistor and then to the third end of the second crystal oscillator.
4. The circuit according to claim 2, characterized in that Also includes a twenty-fifth resistor and a twenty-sixth resistor; The first end of the twenty-fifth resistor is grounded, the second end of the twenty-fifth resistor is connected to the first end of the second crystal oscillator, the first end of the twenty-sixth resistor is connected to the third end of the second crystal oscillator, and the second end of the twenty-sixth resistor is connected to the third end of the first crystal oscillator.
5. The circuit according to claim 1, characterized in that Also included is a seventeenth capacitor and an eighteenth capacitor; The first end of the seventeenth capacitor is connected to the first end of the first crystal oscillator, the second end of the seventeenth capacitor is grounded, the first end of the eighteenth capacitor is connected to the third end of the first crystal oscillator, and the second end of the eighteenth capacitor is grounded.
6. The circuit according to claim 2, characterized in that It also includes a first capacitor and a second capacitor; the first end of the first capacitor is connected to the first end of the second crystal oscillator, the second end of the first capacitor is grounded, the first end of the second capacitor is connected to the third end of the second crystal oscillator, and the second end of the second capacitor is grounded.
7. The circuit according to claim 1, characterized in that The operating frequency of the first crystal oscillator is 25 MHz.
8. The circuit according to claim 2, characterized in that The operating frequency of the second crystal oscillator is 25 MHz.
9. The circuit according to claim 1, characterized in that Models of the first PHY chip and the second PHY chip include at least one of RTL8211FD, RTL8211FP, and YT8531P.
10. An application system of LED video processor clock, characterized in that: An application circuit comprising the LED video processor clock according to any one of claims 1 to 9.