Semiconductor structure

Abstract

The utility model provides a semiconductor structure. The semiconductor structure comprises a semiconductor substrate, a groove, a field oxide layer, source polycrystalline silicon, a gate oxide layer and a polycrystalline silicon gate, the top surface of the source polycrystalline silicon is a smooth surface, and the area of an overlapping region of the polycrystalline silicon gate and the source polycrystalline silicon is smaller than a preset threshold value. A smooth surface is formed on the top surface of the source polycrystalline silicon, the overlapping area of the polycrystalline silicon gate in the active area of the device and the source polycrystalline silicon is reduced, the fracture defect of the source polycrystalline silicon can be improved, the problem of low IGSS is avoided, the G-S overlapping coupling area of the device is reduced at low cost, the gate-source capacitance and the gate charging time are reduced, and the device reliability is improved. Therefore, the device switching loss is reduced, and the switching driving efficiency is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a semiconductor structure. Background Art

[0002] Metal oxide semiconductor field effect transistors (MOSFETs) can be roughly divided into the following categories: planar type; trench type (Trench), mainly used in low-voltage fields; shielded gate trench type (Shielded Gate Transistor, abbreviated as SGT), mainly used in medium-voltage and low-voltage fields; superjunction type (Super Junction, abbreviated as SJ), mainly applied in high-voltage fields. Among them, SGT-MOSFET devices have a charge coupling effect, introducing horizontal depletion on the basis of the vertical depletion of the PN junction of traditional trench MOSFET devices. Under the condition of using the same doping concentration of epitaxial material specifications, a higher breakdown voltage can be obtained.

[0003] In the preparation process of existing SGT-MOSFET devices, after the process of partially removing the polysilicon in the trench extending into the substrate, a V-shaped defect morphology exists at the top of the source polysilicon. This defect morphology will form a source polysilicon break defect problem after fluctuations in the previous process flow and the subsequent thermal growth process of the gate oxide layer. This defect problem will lead to a low IGSS yield problem. At the same time, after the process of removing the mask layer on the substrate and the field oxide layer in the trench, the height of the top surface of the source polysilicon protruding from the remaining field oxide layer is relatively high (about 0.7um), resulting in a large overlap area between the polysilicon gate and the source polysilicon in the active area of the device; the large overlap area makes the G-S overlap coupling area of the device too large, increasing the gate-source capacitance Cgs, making the input capacitance Ciss and the gate charging time (t = Cgs * Rg) larger, resulting in a relatively large switching loss of the device (especially in the field of high-frequency switching applications). Summary of the Invention

[0004] The technical problem to be solved by the utility model is to provide a semiconductor structure, improve the process flow, so that the formed device can improve the source polysilicon break defect, and at the same time reduce the G-S overlap coupling area of the device at low cost, reduce the gate-source capacitance and the gate charging time, thereby reducing the switching loss of the device and improving the switching drive efficiency.

[0005] To solve the above problems, the present utility model provides a semiconductor structure, which includes: a semiconductor substrate; a trench extending from the surface of the semiconductor substrate into the semiconductor substrate; a field oxide layer formed on the inner wall of the trench, the height difference between the top surface of the field oxide layer and the surface of the semiconductor substrate being equal to a target height; a source polysilicon formed on the surface of the field oxide layer within the trench, the top surface of the source polysilicon being a smooth surface and lower than the surface of the semiconductor substrate, and there being no defective morphology at the top of the source polysilicon; a gate oxide layer at least continuously distributed on the surface of the semiconductor substrate on the sidewall of the trench and on the surface of the source polysilicon; and a polysilicon gate covering the gate oxide layer within the trench and filling the trench, the area of the overlapping region between the polysilicon gate and the source polysilicon being less than a preset threshold.

[0006] In the above technical solution, a smooth surface is formed on the top surface of the source polysilicon, and the overlapping region between the polysilicon gate and the source polysilicon in the active region of the device becomes smaller, which can improve the fracture defect of the source polysilicon and avoid causing the problem of low yield of IGSS. At the same time, the G-S overlapping coupling area of the device is reduced at low cost, the gate-source capacitance and the gate charging time are reduced, thereby reducing the switching loss of the device and improving the switching drive efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following will briefly introduce the drawings required to be used in the embodiments of the present utility model. Obviously, the drawings described below are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0008] Figure 1 It is a schematic diagram of the partial morphology of an existing SGT-MOSFET device;

[0009] Figure 2 It is a schematic diagram of the steps of the preparation method of the semiconductor structure in an embodiment of the present utility model;

[0010] Figures 3A to 3B It is a schematic diagram of the partial morphology of forming a substrate in an embodiment of the present utility model;

[0011] Figure 4 It is a schematic diagram of the partial morphology of forming a re-oxidation layer in an embodiment of the present utility model;

[0012] Figures 5A to 5D It is a schematic diagram of the partial morphology of removing the re-oxidation layer, the mask layer and part of the field oxide layer by a multi-step method in an embodiment of the present utility model;

[0013] Figure 6Schematic diagram of the local topography of forming a gate oxide layer and a polysilicon gate according to an embodiment of the present invention;

[0014] Figure 7 Schematic diagram of the local topography of a semiconductor structure formed according to an embodiment of the present invention. Detailed implementation manners

[0015] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0016] The SGT-MOSFET device has a charge coupling effect. Based on the vertical depletion of the PN junction of the traditional trench MOSFET device, horizontal depletion is introduced. Under the condition of using the same doping concentration of epitaxial material specifications, a higher breakdown voltage can be obtained. In the existing preparation process of the SGT-MOSFET device, after the polysilicon part in the trench 109 extending into the substrate 10 is partially removed (Poly Recess Etch) as the source polysilicon (Source Poly) 13, the mask layer is directly removed (ONORemove) and the field oxide layer 12 on the sidewall of the trench is removed (FOX Dip); then a thinner sacrificial oxide layer (SACOX) is formed to repair the topography of the source polysilicon 13, and the sacrificial oxide layer is removed by wet etching; subsequently, the gate oxide layer (GOX) 14 is thermally grown and the polysilicon gate (Gate Poly) 15 is deposited. The local topography of the formed SGT-MOSFET device is as Figure 1 shown.

[0017] In the preparation process of the existing SGT-MOSFET device, after the partial removal process of the polysilicon in the trench, there is a V-shaped defect morphology 131 at the top of the source polysilicon 13. After fluctuations in the previous process flow and the subsequent thermal growth process of the gate oxide layer, a source polysilicon break defect problem will be formed, which will lead to a low IGSS yield problem. IGSS is the leakage current that appears between the gate and the source when the source and drain are short-circuited. At the same time, after the mask layer removal and the field oxide layer removal process, the height h1 of the top surface of the source polysilicon 13 protruding from the remaining field oxide layer 12 is relatively high (about 0.7um), resulting in a large overlap area 161 between the polysilicon gate 15 and the source polysilicon 13 in the active region of the device. The large overlap area 161 makes the G-S overlap coupling area of the device too large, increasing the gate-source capacitance Cgs, making the input capacitance Ciss and the gate charging time (t = Cgs * Rg) larger, resulting in a large switching loss of the device (especially in the field of high-frequency switching applications).

[0018] In order to enable the formed device to improve the source polysilicon break defect, and at the same time reduce the G-S overlap coupling area of the device at low cost, reduce the gate-source capacitance and the gate charging time, thereby reducing the switching loss of the device and improving the switching drive efficiency, an embodiment of the present invention provides a method for preparing a semiconductor structure.

[0019] Please refer to Figures 2 to 7 at the same time, where Figure 2 is a schematic diagram of the steps of the method for preparing a semiconductor structure according to an embodiment of the present invention; Figures 3A to 3B is a partial morphology schematic diagram of forming a substrate according to an embodiment of the present invention; Figure 4 is a partial morphology schematic diagram of forming a re-oxidation layer according to an embodiment of the present invention; Figures 5A to 5D is a partial morphology schematic diagram of the multi-step method for removing the re-oxidation layer, the mask layer and a part of the field oxide layer according to an embodiment of the present invention; Figure 6 is a partial morphology schematic diagram of forming a gate oxide layer and a polysilicon gate according to an embodiment of the present invention; Figure 7 is a partial morphology schematic diagram of the semiconductor structure formed according to an embodiment of the present invention.

[0020] As shown in Figure 2As shown in the figure, the method for preparing the semiconductor structure according to this embodiment includes the following steps: S1. Form a substrate, where the substrate includes a semiconductor substrate, a trench extending from the surface of the semiconductor substrate into the semiconductor substrate, a patterned mask layer covering the surface of the semiconductor substrate and exposing the trench, a field oxide layer formed on the inner wall of the trench, and source polysilicon formed on the surface of the field oxide layer in the trench. The top surface of the source polysilicon is lower than the surface of the semiconductor substrate, and there is a defective morphology at the top of the source polysilicon; S2. Form a re-oxidation layer on the top of the source polysilicon to repair the defective morphology; S3. Remove the re-oxidation layer, the patterned mask layer, and the field oxide layer with a target height by a multi-step method, and a smooth surface is formed on the top surface of the source polysilicon; and S4. Form a continuously distributed gate oxide layer on at least the surface of the semiconductor substrate and the surface of the source polysilicon on the sidewall of the trench, and form a polysilicon gate covering the gate oxide layer in the trench and filling the trench. The area of the overlapping region between the polysilicon gate and the source polysilicon is less than a preset threshold.

[0021] Please refer to step S1 and Figure 3B , form a substrate, where the substrate includes a semiconductor substrate 40, a trench 409 extending from the surface of the semiconductor substrate 40 into the semiconductor substrate 40, a patterned mask layer 49 covering the surface of the semiconductor substrate 40 and exposing the trench 409, a field oxide layer 42 formed on the inner wall of the trench 409, and source polysilicon 43 formed on the surface of the field oxide layer 42 in the trench 409. The top surface of the source polysilicon 43 is lower than the surface of the semiconductor substrate 40, and there is a defective morphology 431 at the top of the source polysilicon 43.

[0022] In this embodiment, the step of forming a substrate specifically includes: (1) Provide a semiconductor substrate 40, and a patterned mask layer 49 is formed on the surface of the semiconductor substrate 40; (2) Etch the semiconductor substrate 40 with the patterned mask layer 49 as a mask to form the trench 409 extending from the surface of the semiconductor substrate 40 into the semiconductor substrate 40; (3) Form a field oxide layer (FOX) 42 on the inner wall of the trench 409; (4) Deposit a polysilicon material in the trench 409 to form a polysilicon material layer 430 that at least covers the field oxide layer 42 in the trench 409 and fills the trench 409, as Figure 3A shown; (5) Back-etch the polysilicon material layer 430 (Poly Recess), and the remaining polysilicon material layer 430 in the trench 49 forms the source polysilicon (Source Poly) 43, and there is a defective morphology 431 at the top of the source polysilicon 43, as Figure 3B shown.

[0023] In this embodiment, the defect morphology 431 is a V-shaped defect morphology. After the partial removal process of the polysilicon in the trench, due to the process itself, a defect morphology 431 will be formed on the top of the source polysilicon 43. If this defect morphology 431 is not repaired, a source polysilicon break defect problem will occur after fluctuations in the previous process flow and the subsequent thermal growth process of the gate oxide layer, and this defect problem will lead to a low IGSS yield problem.

[0024] The semiconductor substrate 40 is used to support the device structure above it, and device structures can also be formed in the semiconductor substrate 40. In this embodiment, the semiconductor substrate 40 may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.; the substrate semiconductor substrate 40 can also be a stacked structure, such as a silicon / germanium-silicon stack, etc. This embodiment is described by taking the semiconductor substrate 40 including a silicon substrate 401 and an epitaxial layer 402 formed on the silicon substrate 401 as an example. The trench 409 extends from the surface of the epitaxial layer 402 into the epitaxial layer 402.

[0025] The patterned mask layer 49 is a stack including an oxide (OX) layer. Specifically, in this embodiment, the patterned mask layer 49 includes a first oxide layer 491, a nitride layer 492, and a second oxide layer 493 (ONO stack) formed in sequence on the surface of the semiconductor substrate 40. The thicknesses of the first oxide (such as silicon dioxide) layer 491 and the second oxide (such as silicon dioxide) layer 493 can both be less than the thickness of the nitride (such as silicon nitride) layer 492. The first oxide layer 491 covers the top surface of the semiconductor substrate 40 and can prevent subsequent processes from damaging the top surface of the semiconductor substrate 40. Silicon nitride is a commonly used and relatively good mask layer. In addition to etching the trench, it can also be used as a barrier layer for chemical mechanical polishing (CMP) and high density plasma (HDP) to protect the surface of the semiconductor substrate from being damaged. Since the SGT-MOSFET device needs to dig a relatively deep trench, in addition to the photoresist, a mask layer is also required as a barrier layer, and the mask layer is also removed during the subsequent wet etching of the sidewall field oxide layer.

[0026] Please refer to step S2 and Figure 4 , a re-oxidation layer 50 is formed on the top of the source polysilicon 43 to repair the defect morphology 431.

[0027] In this embodiment, the step of forming a re-oxidation layer 50 on the top of the source polysilicon 43 to repair the defective morphology 431 specifically includes: forming a re-oxidation layer 50 on the top of the source polysilicon 43 by a thermal oxidation process to repair the defective morphology. The film thickness h2 of the re-oxidation layer 50 is the thickness of the source polysilicon 43 consumed by the thermal oxidation process. That is, the film thickness h2 of the re-oxidation layer 50 is limited by the thermal oxidation process. Theoretically, with the development of the thermal oxidation process, the thickness of the source polysilicon 43 that can be consumed by the thermal oxidation process can make there be no overlap region between the source polysilicon 43 and the polysilicon gate formed subsequently, so that there is no G-S overlap coupling area in the device, greatly reducing the gate-source capacitance Cgs, thereby reducing the switching loss of the device.

[0028] In some embodiments, the sum of the film thickness h2 of the re-oxidation layer 50 and the distance value from the top surface of the re-oxidation layer 50 to the surface of the semiconductor substrate is less than or equal to the target height h (shown in Figure 5A ). When the sum of the film thickness h2 of the re-oxidation layer 50 and the distance value from the top surface of the re-oxidation layer 50 to the surface of the semiconductor substrate is equal to the target height h, it can make there be no overlap region between the source polysilicon 43 and the polysilicon gate formed subsequently.

[0029] In some embodiments, before the step of forming a re-oxidation layer 50 on the top of the source polysilicon 43 to repair the defective morphology 431, it further includes: performing ion implantation to improve the polysilicon lattice of the source polysilicon 43. The step of performing ion implantation specifically includes: performing arsenic (As) ion implantation doping in a photoresist-free mode. After the process of etching back the polysilicon material layer 430 (Poly Recess) to form the source polysilicon 43, an arsenic ion implantation process (general implantation without photoresist) can be performed, which can improve the polysilicon lattice of the source polysilicon 43 and serve for the subsequent formation of an oxide layer on the source polysilicon 43 (after arsenic ion implantation, it is convenient for the formation of the oxide layer, especially the oxide layer on polysilicon).

[0030] Please refer to step S3 and Figure 5D , and a multi-step method is used to remove the re-oxidation layer 50, the patterned mask layer 49, and the field oxide layer 42 with the target height h, so as to form a smooth surface on the top surface of the source polysilicon 43.

[0031] In some embodiments, the patterned mask layer 49 is a stack including an oxide layer; the step of removing the re-oxidation layer 50, the patterned mask layer 49 and the field oxide layer 42 with a target height h by a multi-step method specifically includes: (1) isotropically removing the oxide layer in the patterned mask layer 49, the re-oxidation layer 50 and a part of the field oxide layer 42 by a wet process, and the removal amount of the field oxide layer 42 is the target height h and the thickness t1 of the first sub-film layer; (2) removing other film layers in the patterned mask layer 49 by a wet process; and (3) removing a part of the field oxide layer 42 by a wet process, and the removal amount of the field oxide layer 42 is the target height h and the thickness t2 of the second sub-film layer, wherein the sum of the thickness t2 of the second sub-film layer and the thickness t1 of the first sub-film layer is the total film thickness t of the field oxide layer. Among them, the order of the above steps (1) and (2) can be adjusted: when the top layer of the patterned mask layer 49 stack is an oxide layer (i.e., the oxide layer is above other film layers), steps (1) and (2) are executed in sequence; when the top layer of the patterned mask layer 49 stack is other film layers (non-oxide layers), steps (1) and (2) are executed in reverse order; step (2) can be further divided into multiple steps according to the number of stacks. The thickness of the second sub-film layer is greater than the thickness of the first sub-film layer. For example, the thickness of the second sub-film layer is 4 / 5 of the total film thickness of the field oxide layer (t1 = t * 4 / 5), and the thickness of the first sub-film layer is 1 / 5 of the total film thickness of the field oxide layer (t1 = t * 1 / 5).

[0032] In this embodiment, the patterned mask layer 49 includes a first oxide layer 491, a nitride layer 492, and a second oxide layer 493 (ONO stack) formed in sequence on the surface of the semiconductor substrate 40; the step of removing the re-oxidation layer 50, the patterned mask layer 49 and the field oxide layer 42 with a target height h by a multi-step method specifically includes: (1) isotropically removing the second oxide layer 493, the re-oxidation layer 50 and a part of the field oxide layer 42 by a wet process, and the removal amount of the field oxide layer 42 is the target height h and the thickness t1 of the first sub-film layer, as Figure 5A shown; (2) removing the nitride layer 492 by a wet process, as Figure 5B shown; (3) removing the first oxide layer 491 by a wet process, as Figure 5Cas shown; and (4) removing a part of the field oxide layer 42 by a wet process, the removal amount of the field oxide layer 42 being the target height h and the thickness t2 of the second sub-film layer, where the sum of the thickness t2 of the second sub-film layer and the thickness t1 of the first sub-film layer is the total film thickness t of the field oxide layer. The thickness of the second sub-film layer is greater than the thickness of the first sub-film layer. For example, the thickness of the second sub-film layer is 4 / 5 of the total film thickness of the field oxide layer (t1 = t * 4 / 5), and the thickness of the first sub-film layer is 1 / 5 of the total film thickness of the field oxide layer (t1 = t * 1 / 5). That is, a part (e.g., 1 / 5) of the total wet process amount required to remove the field oxide layer 42 with the target height h can be used first to remove the re-oxidation layer 50 and a part of the field oxide layer 42 while removing the corresponding top oxide layer (the second oxide layer 493) of the patterned mask layer 49; subsequently, the remaining part (e.g., 4 / 5) of the total wet process amount required to remove the field oxide layer 42 with the target height h is used to remove another part of the field oxide layer 42 at the target height. Thus, without changing the total removal amount of the field oxide layer 42, the re-oxidation layer 50 generated to repair the defective morphology on the top surface of the source polysilicon 43 can be removed, so that a smooth surface is formed on the top surface of the source polysilicon 43, and at the same time, the height of the top surface of the source polysilicon 43 protruding from the remaining field oxide layer 42 is reduced.

[0033] Continuing from the above embodiment, after removing the re-oxidation layer 50, the patterned mask layer 49, and the field oxide layer 42 with the target height h by a multi-step method, the height h3 of the top surface of the source polysilicon 43 protruding from the remaining field oxide layer 42 is less than or equal to 0.4 um. Compared with Figure 1 as shown in the prior art, after the mask layer removal and the field oxide layer removal processes, the height h1 of the top surface of the source polysilicon 13 protruding from the remaining field oxide layer 12 is about 0.7 um. In this embodiment, the overlap area between the polysilicon gate and the source polysilicon in the active region of the device can be reduced, and the G-S overlap coupling area of the device can be reduced, thereby reducing the switching loss of the device.

[0034] Since a re-oxidation layer 50 is formed on the top of the source polysilicon 43 in this embodiment to repair the defective morphology 431, the process of forming a relatively thin sacrificial oxide layer (SAC OX) to repair the morphology of the source polysilicon and removing the sacrificial oxide layer by a wet process in the prior art can be omitted, which can simplify the process flow and save the process cost.

[0035] Please refer to step S4 and Figure 6, a gate oxide layer 44 is formed in a continuously distributed manner on at least the surface of the semiconductor substrate 40 on the sidewall of the trench 409 and the surface of the source polysilicon 43, and a polysilicon gate 45 is formed to cover the gate oxide layer 44 in the trench 409 and fill the trench 409, and the area of the overlapping region 461 between the polysilicon gate 45 and the source polysilicon 43 is less than a preset threshold.

[0036] Since the height h3 of the top surface of the source polysilicon 43 protruding above the remaining field oxide layer 42 becomes smaller (less than or equal to 0.4 μm). Compared with Figure 1 the existing technology device shown has a relatively large overlapping region 161 between the polysilicon gate 15 and the source polysilicon 13 in the active region. In this embodiment, the area of the overlapping region 461 between the polysilicon gate 45 and the source polysilicon 43 is less than a preset threshold (the preset threshold can be set to be less than or equal to the area of the existing overlapping region 161). This embodiment effectively reduces the overlapping region between the polysilicon gate and the source polysilicon in the active region of the device, reduces the G-S overlapping coupling area of the device, and thus reduces the switching loss of the device.

[0037] In this embodiment, the cross-sectional shape of the overlapping region between the source polysilicon 43 and the polysilicon gate 45 is trapezoidal. The growth of the gate oxide layer 44 will oxidize and consume part of the source polysilicon 43, forming a trapezoidal cross-sectional morphology at its top, but the top surface of the source polysilicon 43 is still a smooth surface without defect morphology.

[0038] In this embodiment, the maximum thickness of the film layer of the polysilicon gate 45 is equal to the target height h. That is, the removal amount of the field oxide layer 42 can ensure that the height (Gate Length) of the polysilicon gate 45 in the active region of the device is consistent with the height of the polysilicon gate of the existing device, thereby reducing the G-S overlapping coupling area of the device while ensuring the device performance.

[0039] For the semiconductor structure formed in this embodiment, the overlapping region between the polysilicon gate 45 and the source polysilicon 43 in the active region of the device becomes smaller, which can reduce the G-S overlapping coupling area of the device and thus reduce the switching loss of the device; the top surface of the source polysilicon 43 is a smooth surface and there is no V-shaped defect morphology at its top, which can avoid the defect problem of source poly break and avoid causing the problem of low IGSS yield.

[0040] Please refer to Figure 7, in this embodiment, the method further includes: (1) forming a first conductivity type body region 81 in the semiconductor substrate 40 corresponding to the polysilicon gate 45 region around the trench 409; (2) forming a second conductivity type doped region 82 in the first conductivity type body region 81, wherein the top surface of the first conductivity type body region 81 and the top surface of the second conductivity type doped region 82 are substantially flush with the top surface of the polysilicon gate 45; (3) forming a gate dielectric layer 83 covering the top surface of the polysilicon gate 45 (in this embodiment, the top surface of the polysilicon gate 45 is covered with a gate oxide layer 44, and the gate dielectric layer 83 covers the gate oxide layer 44 on the top surface of the polysilicon gate 45); and (4) forming a source electrode 84 covering the gate dielectric layer 83 and covering the top surface of the first conductivity type body region 81 and the top surface of the second conductivity type doped region 82.

[0041] In some embodiments, the first conductivity type body region 81 is a P-type body region, and the second conductivity type doped region 82 is an N+-type doped region. The semiconductor structure is a shielded gate trench metal oxide semiconductor field effect transistor (SGT-MOSFET).

[0042] The preparation method of the semiconductor structure described in this embodiment can be applied to the SGT process platform. In the semiconductor structure prepared in this embodiment, the overlapping area of the polysilicon gate and the source polysilicon in the active region of the device becomes smaller, which can reduce the G-S overlapping coupling area of the device, thereby reducing the switching loss of the device; the top surface of the source polysilicon is a smooth surface and there is no V-shaped defect morphology at its top, which can avoid the problem of source polysilicon fracture defects and avoid causing low yield problems of IGSS. The semiconductor structure prepared by the preparation method of the semiconductor structure described in this embodiment can be used to produce chips such as SGT-MOSFET devices, and can serve a wide range of high-end application markets such as automotive electronics, industrial control, power management, intelligent terminals, and even rail transit and smart grids. It can be applied in terminal products such as intelligent driving, intelligent industry, smart home, and intelligent devices.

[0043] Among them, the SGT-MOSFET device has a charge coupling effect, introducing horizontal depletion on the basis of the vertical depletion of the PN junction of the traditional trench MOSFET device. Under the condition of using the same doping concentration of epitaxial material specifications, a higher breakdown voltage can be obtained. The relatively deep trench depth of the SGT-MOSFET device can utilize more silicon volume to absorb the energy of the avalanche energy test (Energy Avalanche Stress, abbreviated as EAS). Therefore, the SGT-MOSFET device can perform better during avalanche and can better withstand avalanche breakdown and surge current. In application fields such as switching power supplies, motor control, and power battery systems, the SGT-MOSFET device combined with advanced packaging is very helpful to improve the efficiency and power density of the system.

[0044] Based on the same inventive concept, an embodiment of the present utility model further provides a semiconductor structure, which is prepared by the above method of the present utility model.

[0045] Please refer to Figure 7 , which is a schematic diagram of the semiconductor structure provided by an embodiment of the present utility model. As Figure 7 shown, the semiconductor structure provided in this embodiment is prepared by the above method of the present utility model, and specifically includes: a semiconductor substrate 40, a trench 409, a field oxide layer 42, a source polysilicon 43, a gate oxide layer 44, and a polysilicon gate 45; the top surface of the source polysilicon 43 is a smooth surface, and the area of the overlapping region 461 between the polysilicon gate 45 and the source polysilicon 43 is less than a preset threshold.

[0046] Specifically, the trench 409 extends from the surface of the semiconductor substrate 4 into the semiconductor substrate 40; the field oxide layer 42 is formed on the inner wall of the trench 49, and the height difference between the top surface of the field oxide layer 42 and the surface of the semiconductor substrate 40 is equal to the target height h (for reference, see Figure 6 ); the source polysilicon 43 is formed on the surface of the field oxide layer 42 in the trench 409, the top surface of the source polysilicon 43 is a smooth surface and lower than the surface of the semiconductor substrate 40, and there is no defective morphology at the top of the source polysilicon 43; the gate oxide layer 44 is at least continuously distributed on the surface of the semiconductor substrate 40 and the surface of the source polysilicon 43 on the side wall of the trench 409; the polysilicon gate 45 covers the gate oxide layer 44 in the trench 409 and fills the trench 409.

[0047] The semiconductor substrate 40 is used to support the device structure above it, and device structures can also be formed in the semiconductor substrate 40. In this embodiment, the semiconductor substrate 40 may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.; the substrate semiconductor substrate 40 may also be a stacked structure, such as a silicon / germanium silicon stack, etc. This embodiment is described by taking the semiconductor substrate 40 including a silicon substrate 401 and an epitaxial layer 402 formed on the silicon substrate 401 as an example. The trench 409 extends from the surface of the epitaxial layer 402 into the epitaxial layer 402.

[0048] Specifically, the source polysilicon 43 is first oxidized at the top to form a re-oxidation layer 50 and then removed by wet etching, so as to reduce the height of the top surface of the source polysilicon 43 protruding above the field oxide layer 42 and to make the top of the source polysilicon 43 free of defect morphology. Further, the sum of the film thickness h2 of the re-oxidation layer 50 and the distance value from the top surface of the re-oxidation layer 50 to the surface of the semiconductor substrate is less than or equal to the target height h (shown in Figure 5A ). When the sum of the film thickness h2 of the re-oxidation layer 50 and the distance value from the top surface of the re-oxidation layer 50 to the surface of the semiconductor substrate is equal to the target height h, there can be no overlap region between the source polysilicon 43 and the subsequently formed polysilicon gate.

[0049] In this embodiment, the height h3 of the top surface of the source polysilicon 43 protruding above the remaining field oxide layer 42 is less than or equal to 0.4 um. Compared with Figure 1 the prior art shown, after the mask layer removal and the field oxide layer removal processes, the height h1 of the top surface of the source polysilicon 13 protruding above the remaining field oxide layer 12 is about 0.7 um. This embodiment can reduce the overlap region between the polysilicon gate and the source polysilicon in the active region of the device, reduce the G-S overlap coupling area of the device, and thus reduce the switching loss of the device. Since the height h3 of the top surface of the source polysilicon 43 protruding above the remaining field oxide layer 42 becomes smaller (less than or equal to 0.4 um). Compared with Figure 1 the prior art device where there is a large overlap region 161 between the polysilicon gate 15 and the source polysilicon 13 in the active region of the device, the area of the overlap region 461 between the polysilicon gate 45 and the source polysilicon 43 in this embodiment is less than a preset threshold (the preset threshold can be set to be less than or equal to the area of the existing overlap region 161). This embodiment effectively reduces the overlap region between the polysilicon gate and the source polysilicon in the active region of the device, reduces the G-S overlap coupling area of the device, and thus reduces the switching loss of the device.

[0050] In this embodiment, the cross-sectional shape of the overlap region between the source polysilicon 43 and the polysilicon gate 45 is trapezoidal. The growth of the gate oxide layer 44 will oxidize and consume part of the source polysilicon 43, forming a trapezoidal cross-sectional morphology at its top, but the top surface of the source polysilicon 43 is still a smooth surface without defect morphology.

[0051] In this embodiment, the maximum film thickness of the polysilicon gate 45 is equal to the target height h. That is, the removal amount of the field oxide layer 42 can ensure that the height (Gate Length) of the polysilicon gate 45 in the active region of the device is the same as that of the polysilicon gate of the existing device, thereby reducing the G-S overlap coupling area of the device while ensuring the device performance.

[0052] In this embodiment, the semiconductor structure further includes: a first conductivity type body region 81 formed in the semiconductor substrate 40 corresponding to the polysilicon gate 45 region around the trench 409; and a second conductivity type doped region 82 formed in the first conductivity type body region 81. The top surface of the first conductivity type body region 81 and the top surface of the second conductivity type doped region 82 are substantially flush with the top surface of the polysilicon gate 45. Specifically, the first conductivity type body region 81 is a P-type body region, and the second conductivity type doped region 82 is an N+-type doped region.

[0053] In this embodiment, the semiconductor structure further includes: a gate dielectric layer 83 covering the top surface of the polysilicon gate 45; and a source electrode 84 covering the gate dielectric layer 83 and covering the top surfaces of the first conductivity type body region 81 and the second conductivity type doped region 82.

[0054] In this embodiment, the semiconductor structure is a shielded gate trench metal oxide semiconductor field effect transistor (SGT-MOSFET). The SGT-MOSFET device has a charge coupling effect, introducing horizontal depletion on the basis of the vertical depletion of the PN junction in the traditional trench MOSFET device. A higher breakdown voltage can be obtained under the condition of using the same doping concentration of epitaxial material specifications. The relatively deep trench depth of the SGT-MOSFET device can utilize more silicon volume to absorb the energy of the Energy Avalanche Stress (EAS) test. Therefore, the SGT-MOSFET device can perform better during avalanche and can better withstand avalanche breakdown and surge current. In application fields such as switching power supplies, motor control, and power battery systems, the SGT-MOSFET device combined with advanced packaging is very helpful for improving the efficiency and power density of the system.

[0055] In the above description, the descriptions of well-known components and technologies are omitted to avoid unnecessarily confusing the concept of the present utility model. In each of the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts among the embodiments can be referred to each other. It should be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without more limitations, an element defined by the statement "further comprising one..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the said element. Additionally, without conflict, the embodiments and features in the present utility model can be combined with each other.

[0056] The above is only the preferred embodiment of the present utility model and is not intended to limit the protection scope of the present utility model. It should be pointed out that for those of ordinary skill in the art in this technical field, without departing from the principle of the present utility model, several improvements and refinements can still be made, and these improvements and refinements should also be regarded as the protection scope of the present utility model.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure comprises: Semiconductor substrate; A groove extending from the surface of the semiconductor substrate to the interior of the semiconductor substrate; A field oxide layer is formed on the inner wall of the trench, and the height difference between the top surface of the field oxide layer and the surface of the semiconductor substrate is equal to the target height; Source polysilicon is formed on the surface of the field oxide layer in the trench, the top surface of the source polysilicon is a smooth surface and is lower than the surface of the semiconductor substrate, and there is no defective morphology on the top of the source polysilicon; a gate oxide layer, which is continuously distributed at least on the surface of the semiconductor substrate and the surface of the source polysilicon on the sidewall of the trench; and A polysilicon gate covers the gate oxide layer in the trench and fills the trench, and an area of ​​an overlapped region between the polysilicon gate and the source polysilicon is smaller than a preset threshold.

2. The semiconductor structure according to claim 1, characterized in that: The semiconductor substrate includes a silicon substrate and an epitaxial layer formed on the silicon substrate, and the trench extends from the surface of the epitaxial layer into the epitaxial layer.

3. The semiconductor structure according to claim 1, characterized in that: The height of the top surface of the source polysilicon protruding from the field oxide layer is less than or equal to 0.4 um.

4. The semiconductor structure according to claim 1, characterized in that The cross-sectional shape of the region where the source polysilicon overlaps with the polysilicon gate is a trapezoid.

5. The semiconductor structure according to claim 1, characterized in that: The maximum thickness of the film layer of the polysilicon gate is equal to the target height.

6. The semiconductor structure according to claim 1, characterized in that The semiconductor structure further comprises: A first conductive type body region is formed in the semiconductor substrate at the periphery of the trench corresponding to the polysilicon gate region; A second conductive type doped region, formed in the first conductive type body region; Wherein, the top surface of the first conductive type body region and the top surface of the second conductive type doped region are substantially flush with the top surface of the polysilicon gate.

7. The semiconductor structure according to claim 6, characterized in that: The first conductive type body region is a P type body region, and the second conductive type doped region is an N+ type doped region.

8. The semiconductor structure according to claim 6, characterized in that: The semiconductor structure further comprises: a gate dielectric layer covering the top surface of the polysilicon gate; The source electrode covers the gate dielectric layer and covers the top surface of the first conductive type body region and the top surface of the second conductive type doped region.

9. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure is a shielded gate trench metal oxide semiconductor field effect transistor.

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