Semiconductor device structure

Abstract

A semiconductor device structure includes a source / drain epitaxial structure including a first semiconductor material; the first aluminum-containing layer is located on the first semiconductor material; and a second semiconductor material on the first aluminum-containing layer. The structure further includes a first semiconductor layer contacting the source / drain epitaxial structure, and a gate layer on the first semiconductor layer.

Description

Technical Field

[0001] Embodiments of the present utility model relate to the structure of semiconductor devices, and more particularly to a source / drain epitaxial structure containing aluminum. Background Art

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advancements in integrated circuit materials and design have enabled each generation of integrated circuits to have smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, the functional density (i.e., the number of interconnect devices per unit chip area) generally increases as the geometric size (i.e., the smallest component or line that can be produced by the adopted manufacturing process) shrinks. The process of size reduction generally helps to increase production capacity and reduce related costs. Size reduction also increases the complexity of processing and manufacturing integrated circuits.

[0003] Thus, methods for processing and manufacturing integrated circuits need to be improved. Summary of the Utility Model

[0004] The purpose of the present utility model is to propose a semiconductor device structure to solve at least one of the above problems.

[0005] One embodiment is a semiconductor device structure. The semiconductor device structure includes a source / drain epitaxial structure located on a substrate, and the source / drain epitaxial structure includes about 0.002 atomic % to about 0.02 atomic % of aluminum. The structure further includes a first semiconductor layer in contact with the source / drain epitaxial structure, and a gate layer located on the first semiconductor layer.

[0006] According to one embodiment of the present utility model, the thickness of the first aluminum-containing layer is 0.2 nm to 1.5 nm.

[0007] According to one embodiment of the present utility model, the source / drain epitaxial structure further includes a second aluminum-containing layer located on the second semiconductor material, and a third semiconductor material located on the second aluminum-containing layer.

[0008] According to one embodiment of the present utility model, a part of the first aluminum-containing layer is located on the upper surface of the first semiconductor material.

[0009] According to one embodiment of the present utility model, a part of the second aluminum-containing layer is located on the part of the first aluminum-containing layer and the upper surface of the second semiconductor material.

[0010] According to one embodiment of the present utility model, the thickness of the part of the second aluminum-containing layer on the first aluminum-containing layer is less than the thickness of the part of the second aluminum-containing layer on the upper surface of the second semiconductor material.

[0011] According to one embodiment of the present utility model, the third semiconductor material is located on the portion of the first aluminum-containing layer and the portion of the second aluminum-containing layer.

[0012] According to one embodiment of the present utility model, it further includes a second semiconductor layer contacting the source / drain epitaxial structure, and a third semiconductor layer contacting the source / drain epitaxial structure, wherein the second semiconductor layer is located on the first semiconductor layer, and the third semiconductor layer is located on the second semiconductor layer.

[0013] According to one embodiment of the present utility model, it further includes a plurality of dielectric spacers located between the first semiconductor layer and the second semiconductor layer and between the second semiconductor layer and the third semiconductor layer.

[0014] According to one embodiment of the present utility model, it further includes a gate dielectric layer located between the first semiconductor layer and the gate layer.

[0015] Another embodiment is a semiconductor device structure. The semiconductor device structure includes a source / drain epitaxial structure, which includes a first semiconductor material; a first aluminum-containing layer located on the first semiconductor material; and a second semiconductor material located on the first aluminum-containing layer. The structure further includes a first semiconductor layer contacting the source / drain epitaxial structure, and a gate layer located on the first semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1 to 6 are perspective views of various stages of manufacturing a semiconductor device structure in some embodiments.

[0017] Figures 7A to 7E are partial side cross-sectional views of the semiconductor device structure along the Figure 6 section line A-A at various manufacturing stages in some embodiments.

[0018] Figure 8 is a perspective view of one of the various stages of manufacturing a semiconductor device structure in some embodiments.

[0019] Figure 9 are side cross-sectional views of the semiconductor device structure along the Figure 8 section line B-B at one of the various manufacturing stages in some embodiments.

[0020] The reference numerals are as follows:

[0021] A-A, B-B: Section lines

[0022] 100: Semiconductor device structure

[0023] 101: Substrate

[0024] 102a, 102b: Substrate portions

[0025] 104: Stack of semiconductor layers

[0026] 106: First semiconductor layer

[0027] 108: Second semiconductor layer

[0028] 110: Mask structure

[0029] 202a, 202b: Fins

[0030] 204: Trench

[0031] 402: Insulating material

[0032] 404: Sacrificial gate stack

[0033] 406: Sacrificial gate dielectric layer

[0034] 408: Sacrificial gate layer

[0035] 410: Mask structure

[0036] 412: Spacer

[0037] 414: Gap

[0038] 416: Dielectric spacer

[0039] 418: First semiconductor material

[0040] 420, 424: Aluminum-containing layer

[0041] 422: Second semiconductor material

[0042] 426: Third semiconductor layer

[0043] 428: Source / drain epitaxial structure

[0044] 502: Contact etch stop layer

[0045] 504: Interlayer dielectric layer

[0046] 506: Gate dielectric layer

[0047] 508: Gate layer Detailed implementation manners

[0048] The following detailed description can be combined with the accompanying drawings for better understanding of various aspects of the present utility model. It should be noted that various structures are only for illustrative purposes and are not drawn to scale, as is normal in the industry. In fact, for clear illustration, the dimensions of various structures can be increased or decreased arbitrarily.

[0049] The following content provides different embodiments or examples that can implement different structures of the utility model. The following specific components and arrangement embodiments are used to simplify the content of the utility model and are not intended to limit the utility model. For example, the description of forming a first component on a second component includes an embodiment in which the two are in direct contact, or an embodiment in which the two are separated by other additional components but not in direct contact. In addition, multiple examples of the utility model may repeatedly use the same number for simplicity, but the elements with the same number in multiple embodiments and / or settings do not necessarily have the same corresponding relationship.

[0050] In addition, spatially relative terms such as "below," "beneath," "lower," "above," "upper," or the like are used to describe the relationship of some elements or structures to another element or structure in the drawings. These spatially relative terms include different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is rotated in a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted based on the orientation.

[0051] Figures 1 to 9 In some embodiments, the process used to manufacture the semiconductor device structure 100 is as follows. Figures 1 - 9 Additional steps may be provided before, during, and after the processes shown, and additional embodiments of the method may replace or omit some of the steps described below. The order of the steps / processes may be reversed.

[0052] Figures 1 to 6 1 is a perspective view of various stages of manufacturing a semiconductor device structure in some embodiments. Figure 1 As shown, a stack 104 of semiconductor layers is formed on a substrate 101. The substrate 101 may be a semiconductor substrate. In some embodiments, the substrate 101 includes a crystalline semiconductor layer at least located on the surface of the substrate 101. The substrate 101 may include a crystalline semiconductor material, such as but not limited to silicon, germanium, silicon germanium, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimony phosphide, gallium antimony arsenide, or indium phosphide. In this embodiment, the composition of the substrate 101 is silicon. In some embodiments, the substrate 101 is a silicon-on-insulator substrate, which includes an insulating layer (not shown) located between two silicon layers. In one embodiment, the insulating layer is an oxide.

[0053] The substrate 101 may include one or more buffer layers (not shown) on the surface of the substrate 101. The buffer layer may be used to gradually change the lattice constant of the substrate to the lattice constant of the source / drain regions grown on the substrate 101. The method of forming the buffer layer may be epitaxial growth of a single-crystalline semiconductor material, which may be, but is not limited to, silicon, germanium, germanium tin, silicon germanium, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium antimonide phosphide, gallium arsenide antimonide, gallium nitride, or indium phosphide. In other embodiments, the substrate 101 includes a silicon germanium buffer layer epitaxially grown on a silicon substrate. The germanium concentration of the silicon germanium buffer layer may increase from 30 atomic % used for the bottommost buffer layer to 70 atomic % used for the topmost buffer layer.

[0054] The substrate 101 may include various regions doped with appropriate impurities, such as p-type or n-type impurities. For example, the dopant may be boron for p-type field-effect transistors or phosphorus for n-type field-effect transistors.

[0055] The stack 104 of semiconductor layers includes a first semiconductor layer 106 and a second semiconductor layer 108. The compositions of the first semiconductor layer 106 and the second semiconductor layer 108 may be semiconductor materials with different etch selectivities and / or oxidation rates. For example, the composition of the first semiconductor layer 106 is silicon, while the composition of the second semiconductor layer 108 is silicon germanium. In one embodiment, the composition of the first semiconductor layer 106 is undoped silicon. The second semiconductor layer 108 may be doped to enhance the etch selectivity of the second semiconductor layer 108 relative to the first semiconductor layer 106. In some embodiments, the stack 104 of semiconductor layers includes alternating first semiconductor layers 106 and second semiconductor layers 108, as Figure 1 shown. The first semiconductor layer 106 or a portion thereof may form the nanostructure channel of the semiconductor device structure in a subsequent stage. The semiconductor device structure 100 may include nanostructure transistors. As used herein, the term nanostructure refers to any material portion having a nanoscale or even a microscale size, which may have any suitable shape such as an elongated shape, regardless of the cross-sectional shape of this portion. Thus, this term may refer to an elongated material portion with a circular or substantially circular cross-section, as well as a bundle or rod-shaped material portion containing a cylindrical or substantially rectangular cross-section. The gate layer may surround the nanostructure channel of the semiconductor device structure 100. The nanostructure transistor may be regarded as a nanosheet transistor, a nanowire transistor, a gate-all-around transistor, a multi-bridge channel transistor, or any transistor having a gate layer surrounding the channel. The method of using the first semiconductor layer 106 to define the channel of the semiconductor device structure 100 will be further described below.

[0056] It is worth noting that Figure 1Three first semiconductor layers 106 are shown interleaved with four second semiconductor layers 108, which is for illustrative purposes only and not to limit the embodiments of the present invention to those not specifically defined in the claims. It should be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the stack 104 of semiconductor layers, and the number of layers depends on the predetermined number of channels used in the semiconductor device structure 100. In some embodiments, the number of first semiconductor layers 106, such as the number of channels, is between 3 and 8.

[0057] As detailed below, the first semiconductor layers 106 can serve as channels used in the semiconductor device structure 100, and the thickness thereof is selected depending on device performance considerations. In some embodiments, the thickness of each of the first semiconductor layers 106 is about 6 nm to about 12 nm. Finally, the second semiconductor layers 108 will be removed, and the second semiconductor layers 108 are used to define the vertical distance between adjacent channels of the semiconductor device structure 100, and the thickness of the second semiconductor layers 108 depends on device performance considerations. In some embodiments, the thickness of each of the second semiconductor layers 108 can be about 2 nm to about 10 nm.

[0058] The method of forming the first semiconductor layers 106 and the second semiconductor layers 108 can be any suitable deposition process such as epitaxy. For example, the method of epitaxially growing the layers of the stack 104 of semiconductor layers can be a molecular beam epitaxy process, a metalorganic chemical vapor deposition process, and / or other suitable epitaxial growth processes.

[0059] A mask structure (not shown) can be formed on the stack 104 of semiconductor layers. The mask structure can include an oxygen-containing layer and a nitrogen-containing layer. The oxygen-containing layer can be a pad oxide layer such as a silicon oxide layer. The nitrogen-containing layer can be a pad nitride layer such as a silicon nitride layer. The method of forming the mask structure can be any suitable deposition process such as a chemical vapor deposition process.

[0060] Figure 2 In some embodiments, a perspective view of the semiconductor device structure 100 at one of various manufacturing stages. As Figure 2As shown, fins 202a and 202b are formed. In some embodiments, each of fins 202a and 202b includes a substrate portion 102a and 102b formed from substrate 101, a portion of the stack 104 of semiconductor layers, and a portion of the mask structure 110. The fins 202a and 202b can be fabricated using suitable processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine lithography with self-alignment processes, which result in a pattern pitch smaller than that obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate and patterned using a lithography process. A self-alignment process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers or cores can be used to etch the stack 104 of semiconductor layers and substrate 101 to pattern the fins 202a and 202b. The etching process can include dry etching, wet etching, reactive ion etching, and / or other suitable processes. As Figure 2 shown, two fins are formed, but the number of fins is not limited to two.

[0061] In some embodiments, the fins 202a and 202b can be fabricated using suitable processes, including lithography and etching processes. The lithography process can include forming a photoresist layer (not shown) on the mask structure 110, exposing light to form a pattern, performing a post-exposure bake process, and developing the photoresist to form a patterned photoresist. In some embodiments, the step of patterning the photoresist to form a photoresist pattern can use an electron beam lithography process. The photoresist pattern can then be used to protect regions of the substrate 101 and layers formed thereon, and an etching process can be performed to form trenches 204 in the unprotected regions. The trenches 204 pass through the mask structure 110 and the stack 104 of semiconductor layers and penetrate into the substrate 101 to leave extended fins 202a and 202b. The trenches 204 can be etched using dry etching such as reactive ion etching, wet etching, and / or a combination of the above.

[0062] As Figure 2As shown, an insulating material 402 is formed on a substrate 101. The insulating material 402 may be first formed on the substrate 101 to embed fins 202a and 202b in the insulating material 402. Subsequently, a planarization process such as a chemical mechanical polishing process and / or a re-etching process may be performed to expose the tops of the fins 202a and 202b from the insulating material 402. Subsequently, a portion of the insulating material 402 between adjacent fins 202a and 202b may be removed to recess the insulating material 402. The method of recessing the insulating material 402 may be any suitable process (such as dry etching or wet etching), which can selectively remove the insulating material 402 without removing the semiconductor materials of the first semiconductor layer 106 and the second semiconductor layer 108. The recessed insulating material 402 may be a shallow trench isolation. The upper surface of the insulating material 402 may be flush with or lower than the surfaces of the substrate portions 102a and 102b of the second semiconductor layer 108 contacting the substrate 101.

[0063] The composition of the insulating material 402 may be an oxygen-containing material such as silicon oxide or fluorosilicate glass, a nitrogen-containing material such as silicon nitride, silicon oxynitride, carbon oxynitride, or carbonitride, a low dielectric constant dielectric material, or any suitable dielectric material. The method of forming the insulating material 402 may be any suitable method, such as low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition.

[0064] As Figure 3 As shown, one or more sacrificial gate stacks 404 are formed on the semiconductor device structure 100. The sacrificial gate stack 404 may include a sacrificial gate dielectric layer 406, a sacrificial gate layer 408, and a mask structure 410. The sacrificial gate dielectric layer 406 may include one or more layers of dielectric materials such as silicon oxide, silicon nitride, a high dielectric constant dielectric material, and / or other suitable dielectric materials. In some embodiments, the sacrificial gate dielectric layer 406 may be deposited by a chemical vapor deposition process, a sub-atmospheric chemical vapor deposition process, a flowable chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, or other suitable processes. The sacrificial gate layer 408 may include polysilicon. The mask structure 410 may include an oxygen-containing layer and a nitrogen-containing layer.

[0065] The method of forming the sacrificial gate stack 404 may be to first deposit a sacrificial gate dielectric layer 406, a sacrificial gate layer 408, and a blanket layer of the mask structure 410, and then perform patterning and etching processes. The method of forming the blanket layers of the sacrificial gate dielectric layer 406, the sacrificial gate layer 408, and the mask structure 410 may be various processes such as chemical vapor deposition (including low-pressure chemical vapor deposition and plasma-assisted chemical vapor deposition), physical vapor deposition, atomic layer deposition, thermal oxidation, electron beam evaporation, other suitable deposition techniques, or combinations of the above. The patterning process includes a lithography process (such as photolithography or electron beam lithography), which may further include photoresist coating (such as spin coating), soft baking, aligning a photomask, exposure, post-exposure baking, photoresist development, rinsing, drying (such as spin drying and / or hard baking), other suitable lithography techniques, and / or combinations of the above. In some embodiments, the etching process may include dry etching such as reactive ion etching, wet etching, other etching methods, and / or combinations of the above. By patterning the sacrificial gate stack 404, the semiconductor layer stacks 104 of the fins 202a and 202b on both sides of the sacrificial gate stack 404 can be partially exposed. As Figure 3 shown, two sacrificial gate stacks 404 are formed, but the number of sacrificial gate stacks 404 is not limited to two. In some embodiments, more than two sacrificial gate stacks 404 are arranged along the X direction.

[0066] As Figure 3 shown, spacers 412 are formed on the sidewalls of the sacrificial gate stack 404. The method of forming the spacers 412 may be to first deposit a conformal layer, and then etch back the conformal layer to form the spacers 412. For example, a spacer material layer may conformally lie on the exposed surface of the semiconductor device structure 100. The method of forming the conformal spacer material layer may be an atomic layer deposition process. Then, anisotropic etching such as reactive ion etching may be performed on the spacer material. During the anisotropic etching process, the main spacer material layer is removed from the horizontal surfaces such as the tops of the fins 202a and 202b and the top of the sacrificial gate stack 404, and the spacers 412 are left on the vertical surfaces such as the sidewalls of the sacrificial gate stack 404. The composition of the spacers 412 may be a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, carbon silicon nitride, carbon silicon oxide, carbon silicon oxynitride, and / or combinations of the above. In some embodiments, the spacers 412 include multiple layers such as main spacer walls, liner layers, and the like.

[0067] Next, the exposed portions of the fins 202a and 202b that are not covered by the sacrificial gate stack 404 and the spacers 412 are recessed, as Figure 4As shown. The process of recessing the exposed portions of fins 202a and 202b can be an etching process such as dry etching, wet etching, or a combination of the above. In some embodiments, the exposed portions of the stack 104 of semiconductor layers of fins 202a and 202b are removed to expose substrate portions 102a and 102b. In some embodiments, a portion of substrate portions 102a and 120b can also be removed. As Figure 4 shown, the exposed portions of fins 202a and 202b are recessed below the upper surface of the insulating material 402.

[0068] At this stage, the end portions of the stack 104 of semiconductor layers under the sacrificial gate stack 404 and the spacers 412 can have a substantially flat surface, which can be flush with the corresponding spacers 412. In some embodiments, the edge portions of the stack 104 of semiconductor layers under the sacrificial gate stack 404 and the spacers 412 are slightly etched horizontally.

[0069] As Figure 5 shown, the respective edge portions of the second semiconductor layer 108 are removed to form gaps 414. In some embodiments, the method of removing a portion of the second semiconductor layer 108 can be a selective wet etching process that does not remove the first semiconductor layer 106. For example, when the composition of the second semiconductor layer 108 is silicon germanium and the composition of the first semiconductor layer 106 is silicon, the selective wet etching process can use a mixture of ammonia and hydrogen peroxide.

[0070] As Figure 6 shown, dielectric spacers 416 are formed in the gaps 414. In some embodiments, the composition of the dielectric spacers 416 can be silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon carbon oxynitride, or silicon nitride. In some embodiments, the method of forming the dielectric spacers 416 can first use a conformal deposition process such as atomic layer deposition to form a conformal dielectric layer, and then perform an anisotropic etching to remove the portions of the conformal dielectric layer other than the dielectric spacers 416. During the anisotropic etching process, the first semiconductor layer 106 and the spacers 412 can protect the dielectric spacers 416. In some embodiments, the dielectric spacers 416 can be flush with the spacers 412.

[0071] Figures 7A to 7E In some embodiments, the semiconductor device structure 100 is a partial side cross-sectional view along the Figure 6 section line A-A at various manufacturing stages. The portions of the sacrificial gate stack 404 and the spacers 412 are as Figures 7A to 7E shown for clarity of the drawings. As Figure 7AAs shown, a first semiconductor material 418 is formed on the exposed substrate portion 102b, the first semiconductor layer 106, and the dielectric spacer 416. The first semiconductor layer 418 can be formed by any suitable process, such as epitaxy like molecular beam epitaxy, metalorganic chemical vapor deposition, and / or other suitable epitaxial growth processes. The first semiconductor material 418 can be grown from the substrate portion 102b and the first semiconductor layer 106. In some embodiments, the portions of the first semiconductor material 418 grown from the vertically adjacent first semiconductor layer 106 can be connected. In this way, the first semiconductor material 418 covers the dielectric spacer 416. In some embodiments, the portion of the first semiconductor material 418 adjacent to the first semiconductor layer 106 is thicker than the portion of the first semiconductor material 418 adjacent to the dielectric spacer 416. In some embodiments, an n-type epitaxial structure is formed, and the first semiconductor material 418 includes silicon doped with an n-type dopant such as arsenic or phosphorus. The n-type dopant concentration can be about 1x10 20 / cm 3 to about 8x10 20 / cm 3 . In some embodiments, a p-type epitaxial structure is formed, and the first semiconductor material 418 includes silicon germanium doped with a p-type dopant such as boron. The p-type dopant concentration can be about 1x10 20 / cm 3 to about 8x10 20 / cm 3 . In some embodiments, the first semiconductor material 418 can be silicon germanium doped with a dopant, and the first semiconductor material 418 has about 25 atomic% to about 45 atomic% germanium.

[0072] In some embodiments, the n-type epitaxial structure and the p-type epitaxial structure are not formed simultaneously. For example, a sacrificial mask layer (not shown) can be formed first in the n-type field effect transistor region, that is, on the first semiconductor layer and the substrate portion exposed in the region where the n-type epitaxial structure is to be formed. The sacrificial mask layer can include any suitable dielectric material. After forming the p-type epitaxial structure in the p-type field effect transistor region, the sacrificial mask layer is removed. Then, another sacrificial mask layer (not shown) can be formed on the p-type epitaxial structure in the p-type field effect transistor region, and the n-type epitaxial structure is formed in the n-type field effect transistor region. After forming the n-type epitaxial structure, the sacrificial mask layer on the p-type epitaxial structure is removed. In some embodiments, a sacrificial mask layer (not shown) can be formed first in the p-type field effect transistor region, that is, on the first semiconductor layer and the substrate portion exposed in the region where the p-type epitaxial structure is to be formed. After forming the n-type epitaxial structure in the n-type field effect transistor region, the sacrificial mask layer is removed. Then, another sacrificial mask layer (not shown) is formed on the n-type epitaxial structure in the n-type field effect transistor region, and the p-type epitaxial structure is formed in the p-type field effect transistor region. After forming the p-type epitaxial structure, the sacrificial mask layer on the n-type epitaxial structure is removed.

[0073] In some embodiments, the process of forming the first semiconductor material 418 may use a chlorine-containing gas to remove the first semiconductor material 418 on the dielectric surfaces (such as the spacers 412 and the insulating material 402, Figure 6 ) without removing the first semiconductor material 418 on the semiconductor surface. The chlorine-containing gas may flow in together with a silicon-containing precursor. In this way, the first semiconductor material 418 can be selectively formed on the first semiconductor layer 106, the substrate portion 102a, and the dielectric spacer 416. In this way, the portions of the first semiconductor material 418 formed on the first semiconductor layer 106 can be connected.

[0074] As Figure 7B shown, an aluminum-containing layer 420 is formed on the first semiconductor material 418. In some embodiments, the aluminum-containing layer 420 is an aluminum layer. In some embodiments, the aluminum-containing layer 420 is an aluminum silicide layer. The method of forming the aluminum-containing layer 420 can be any suitable process such as chemical vapor deposition or physical vapor deposition. In some embodiments, a DC magnetron sputtering process is performed to form the aluminum-containing layer 420. The aluminum-containing layer 420 is also formed on dielectric materials such as the spacers 412 and the insulating material 402 ( Figure 6 ). In some embodiments, the portion of the aluminum-containing layer 420 formed on the first semiconductor material 418 can be a compliant layer, and its thickness is about 0.2 nm to about 1.5 nm. The portion of the aluminum-containing layer 420 formed on dielectric surfaces such as the spacers 412 and the insulating material 402 ( Figure 6 ) can be thinner than the portion of the aluminum-containing layer 420 formed on the semiconductor surface because the deposition rate of the aluminum-containing layer 420 on the semiconductor surface is greater than that on the dielectric surface. In some embodiments, the portion of the aluminum-containing layer 420 formed on the dielectric surface may be discontinuous. The aluminum-containing layer 420 formed on the first semiconductor material 418 can increase the critical dimension of the source / drain epitaxial structure and the deposition rate of the subsequently deposited semiconductor material without generating defects in the source / drain epitaxial structure. Therefore, if the thickness of the aluminum-containing layer 420 is less than about 0.2 nm, the aluminum-containing layer 420 may be too thin to have the above advantages. On the other hand, if the thickness of the aluminum-containing layer 420 is greater than about 1.5 nm, it may fill the openings between the stacks 104 of adjacent semiconductor layers, and semiconductor material cannot be formed on the aluminum-containing layer 420. In this way, the source / drain resistance may be increased. In addition, in embodiments where the chlorine-containing gas and the silicon-containing precursor flow in together, the aluminum-containing layer 420 can improve the selectivity loss when forming the semiconductor material of the source / drain epitaxial structure.

[0075] As Figure 7CAs shown, a second semiconductor material 422 is formed over a portion of an aluminum-containing layer 420 formed over a first semiconductor material 418. The method of forming the second semiconductor material 422 may be epitaxy. In some embodiments, the formation process of the second semiconductor material 422 may be the same as the formation process of the first semiconductor material 418. The second semiconductor material 422 may include silicon doped with a doping n-type dopant for an n-type epitaxial structure, or silicon germanium doped with a doping p-type dopant for a p-type epitaxial structure. For example, the second semiconductor material 422 may be silicon germanium doped with a dopant, and the second semiconductor material 422 has about 40 atomic % to about 60 atomic % of germanium. In some embodiments, the atomic % of germanium in the second semiconductor material 422 is greater than the atomic % of germanium in the first semiconductor material 418. In some embodiments, the dopant concentration of the second semiconductor material 422 may be about 5x10 20 / cm 3 to about 4x10 21 / cm 3 . In some embodiments, the dopant concentration of the second semiconductor material 422 is higher than the dopant concentration of the first semiconductor material 418.

[0076] The aluminum-containing layer 420 increases the critical dimension and the deposition rate of the second semiconductor material 422. The critical dimension along the X direction is limited by the opening between the stacks 104 of adjacent semiconductor layers. However, the critical dimension along the Y direction can be increased compared to the semiconductor material formed without the aluminum-containing layer 420. In some embodiments, the second semiconductor material 422 may initially be formed over a portion of the aluminum-containing layer 420 on a dielectric surface such as a spacer 412. As described above, by flowing in a chlorine-containing gas and a silicon precursor together, a portion of the second semiconductor material 422 on a portion of the aluminum-containing layer 420 on the dielectric surface can be removed when forming the second semiconductor material 422.

[0077] As Figure 7D shown, an aluminum-containing layer 424 is formed over the second semiconductor material 422. The aluminum-containing layer 424 may include the same material as the aluminum-containing layer 420, and the formation process of the aluminum-containing layer 424 and the aluminum-containing layer 420 may be the same. In some embodiments, a portion of the aluminum-containing layer 424 is formed over a portion of the aluminum-containing layer 420 on a dielectric surface (such as a spacer 412), as Figure 7DAs shown. Similar to the aluminum-containing layer 420, the aluminum-containing layer 424 formed on the aluminum-containing layer 420 is thinner because the portion of the aluminum-containing layer 420 formed on the dielectric surface is thin or discontinuous. Thus, in some embodiments, the thickness of the portion of the aluminum-containing layer 424 formed on the aluminum-containing layer 420 is less than the thickness of the portion of the aluminum-containing layer 424 formed on the second semiconductor material 422. In some embodiments, the total thickness of the portions of the aluminum-containing layers 420 and 424 formed on the spacer 412 is substantially greater than the thickness of the portions of the aluminum-containing layers 420 and 424 formed on the first semiconductor material 418 and the second semiconductor material 422, but substantially less than the sum of the thicknesses of the portions of the aluminum-containing layers 420 and 424 formed on the first semiconductor material 418 and the second semiconductor material 422.

[0078] As Figure 7E shown, a third semiconductor material 426 is formed on the aluminum-containing layer 424. The third semiconductor material 426 can be formed by epitaxy. The third semiconductor material 426 can include doped silicon for an n-type epitaxial structure or doped silicon germanium for a p-type epitaxial structure. For example, the third semiconductor material 426 can be doped silicon germanium having 45 atomic % to 55 atomic % of germanium. In some embodiments, the doping concentration of the third semiconductor material 426 can be about 1x10 21 / cm 3 to about 2x10 21 / cm 3 . In some embodiments, the dopant concentration of the third semiconductor material 426 is substantially less than the dopant concentration of the second semiconductor material 422. The first semiconductor material 418, the second semiconductor material 422, and the third semiconductor material 426, as well as the aluminum-containing layers 420 and 424, can be regarded together as a source / drain epitaxial structure 428, which can be an n-type epitaxial structure or a p-type epitaxial structure. The source / drain epitaxial structure 428 can be a source / drain region. In the embodiments of the present invention, the terms "source" and "drain" can be used interchangeably, and their structures are substantially the same. In addition, the source / drain region can refer to the source or the drain individually or collectively, depending on the context.

[0079] As Figure 7E shown, the third semiconductor material 426 fills the opening between the stacks 104 of adjacent semiconductor layers. The third semiconductor material 426 is also formed on the horizontal portions of the aluminum-containing layers 420 and 424 adjacent to the spacer 412, as Figure 7EAs shown. After forming the third semiconductor material 426, the exposed portions of the aluminum-containing layers 420 and 424 on the dielectric surface can be removed. In some embodiments, a plasma process is performed to remove the exposed portions of the aluminum-containing layers 420 and 424. The plasma process can use a hydrogen-containing plasma, which selectively removes the exposed aluminum-containing layers 420 and 424. The plasma process substantially does not affect the third semiconductor material 426, the spacers 412, the insulating material 402, and the dielectric material of the mask structure 410.

[0080] Figure 8 In some embodiments, Figure 7E A perspective view of the semiconductor device structure 100 as shown. As Figure 8 shown, the source / drain epitaxial structure 428 includes a first semiconductor layer 418, a second semiconductor layer 422, a third semiconductor material 426, and aluminum-containing layers 420 and 424, and is formed on the substrate portions 102a and 102b of the fins 202a and 202b. In some embodiments, the source / drain epitaxial structure 428 includes the aluminum-containing layers 420 and 424. In some embodiments, each of the source / drain epitaxial structures 428 includes one of the aluminum-containing layers 420 and 424. In some embodiments, each of the source / drain epitaxial structures 428 includes from about 0.002 atomic % to about 0.02 atomic % of aluminum. If the source / drain epitaxial structure 428 includes less than about 0.002 atomic % of aluminum, the critical dimension of the source / drain epitaxial structure 428 may not be increased, and the deposition time of the source / drain epitaxial structure 428 may not be shortened. On the other hand, if the source / drain epitaxial structure 428 includes more than about 0.02 atomic % of aluminum, the source / drain resistance is increased. By using the aluminum-containing layer 420 and / or the aluminum-containing layer 424, the critical dimension of the source / drain epitaxial structure 428 along the Y direction can be increased. In some embodiments, the critical dimension of the source / drain epitaxial structure 428 along the Y direction can be increased from about 35 nm to about 45 nm. In addition, the deposition time of the source / drain epitaxial structure 428 can be shortened.

[0081] Figure 9 In some embodiments, the semiconductor device structure 100 at one of various manufacturing stages along Figure 8Side cross-sectional view along cut line B-B. Details of the source / drain epitaxial structure 428 are omitted for clarity of the drawing. Subsequent processes may be performed to complete the semiconductor device structure 100. For example, a contact etch stop layer 502 may be formed over the source / drain epitaxial structure 428, and an interlayer dielectric layer 504 may be formed over the contact etch stop layer 502. The contact etch stop layer 502 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, the like, or a combination thereof. The contact etch stop layer 502 may be formed by chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. In some embodiments, the contact etch stop layer 502 is a conformal layer formed by an atomic layer deposition process. The material used for the interlayer dielectric layer 504 may include an oxide formed from tetraethyl orthosilicate, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass, fluorosilicate glass, phosphosilicate glass, borosilicate glass, and / or other suitable dielectric materials. The deposition method for the interlayer dielectric layer 504 may be a plasma-assisted chemical vapor deposition process or other suitable deposition techniques. In some embodiments, after forming the interlayer dielectric layer 504, a thermal process may be performed on the semiconductor device structure 100 to anneal the interlayer dielectric layer 504.

[0082] Next, the sacrificial gate stack 404 and the second semiconductor layer 108 are removed, and a gate dielectric layer 506 and a gate layer 508 are formed to surround the exposed portion of the first semiconductor layer 106. The sacrificial gate layer 408 can be removed first by any suitable process such as dry etching, wet etching, or a combination of the above. Next, the sacrificial gate dielectric layer 406 is removed, and the removal method can be any suitable process such as dry etching, wet etching, or a combination of the above. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide solution can be used to selectively remove the sacrificial gate layer 408. Removing the second semiconductor layer 108 can expose the dielectric spacer 416 and the first semiconductor layer 106. The method for removing the second semiconductor layer 108 can be any suitable process, such as dry etching, wet etching, or a combination of the above. The etching process can be a selective etching process. In some embodiments, the gate dielectric layer 506 includes a high-k dielectric material. The method for forming the gate dielectric layer 506 can be any suitable process, such as atomic layer deposition. In some embodiments, the method for forming the gate dielectric layer 506 is a conformal process. The gate layer 508 is formed on the gate dielectric layer 506 to surround a portion of each first semiconductor layer 106. The gate layer 508 includes one or more layers of conductive materials such as polysilicon, aluminum, copper, titanium, tantalum, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride, tungsten nitride, titanium aluminide, titanium aluminum nitride, tantalum carbonitride, tantalum carbide, tantalum silicon nitride, metal alloy, other suitable materials, and / or a combination of the above. The method for forming the gate layer 508 can be physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating, or other suitable methods.

[0083] The semiconductor device structure 100 provided by the embodiment of the present invention contains one or more aluminum-containing layers (420, 424) in the source / drain epitaxial structure 428. Some embodiments can achieve some advantages. For example, the aluminum-containing layers (420, 424) can increase the critical dimension and accelerate the deposition time.

[0084] One embodiment is a semiconductor device structure. The semiconductor device structure includes a source / drain epitaxial structure located on a substrate, and the source / drain epitaxial structure includes about 0.002 atomic % to about 0.02 atomic % of aluminum. The structure further includes a first semiconductor layer in contact with the source / drain epitaxial structure, and a gate layer located on the first semiconductor layer.

[0085] In some embodiments, the semiconductor device structure further includes a second semiconductor layer in contact with the source / drain epitaxial structure, and a third semiconductor layer in contact with the source / drain epitaxial structure, wherein the second semiconductor layer is located on the first semiconductor layer, and the third semiconductor layer is located on the second semiconductor layer.

[0086] In some embodiments, the semiconductor device structure further includes a plurality of dielectric spacers located between the first semiconductor layer and the second semiconductor layer and between the second semiconductor layer and the third semiconductor layer.

[0087] In some embodiments, the gate layer is located between the first semiconductor layer and the second semiconductor layer and between the second semiconductor layer and the third semiconductor layer.

[0088] In some embodiments, the semiconductor device structure further includes a gate dielectric layer on the first semiconductor layer, and the gate layer is on the gate dielectric layer.

[0089] Another embodiment is a semiconductor device structure. The semiconductor device structure includes a source / drain epitaxial structure including a first semiconductor material; a first aluminum-containing layer on the first semiconductor material; and a second semiconductor material on the first aluminum-containing layer. The structure further includes a first semiconductor layer in contact with the source / drain epitaxial structure, and a gate layer on the first semiconductor layer.

[0090] In some embodiments, the first aluminum-containing layer includes aluminum or aluminum silicide.

[0091] In some embodiments, the thickness of the first aluminum-containing layer is from about 0.2 nm to about 1.5 nm.

[0092] In some embodiments, the source / drain epitaxial structure further includes a second aluminum-containing layer on the second semiconductor material, and a third semiconductor material on the second aluminum-containing layer.

[0093] In some embodiments, a portion of the first aluminum-containing layer is on the upper surface of the first semiconductor material.

[0094] In some embodiments, a portion of the second aluminum-containing layer is above the portion of the first aluminum-containing layer and the upper surface of the second semiconductor material.

[0095] In some embodiments, the thickness of the portion of the second aluminum-containing layer on the first aluminum-containing layer is less than the thickness of the portion of the second aluminum-containing layer on the upper surface of the second semiconductor material.

[0096] In some embodiments, the third semiconductor material is above the portion of the first aluminum-containing layer and the portion of the second aluminum-containing layer.

[0097] In some embodiments, the semiconductor device further includes a second semiconductor layer in contact with the source / drain epitaxial structure, and a third semiconductor layer in contact with the source / drain epitaxial structure, wherein the second semiconductor layer is on the first semiconductor layer, and the third semiconductor layer is on the second semiconductor layer.

[0098] In some embodiments, the semiconductor device structure further includes a plurality of dielectric spacers between the first semiconductor layer and the second semiconductor layer and between the second semiconductor layer and the third semiconductor layer.

[0099] In some embodiments, the semiconductor device structure further includes a gate dielectric layer located between the first semiconductor layer and the gate layer.

[0100] Other embodiments are methods for forming a semiconductor device structure. The method includes forming a stack of a plurality of first semiconductor layers and a plurality of second semiconductor layers; forming a sacrificial gate stack on a part of the stack of the first semiconductor layer and the second semiconductor layer; forming a plurality of spacers on the sidewalls of the sacrificial gate stack; removing the exposed portions of the stack of the first semiconductor layer and the second semiconductor layer to expose a substrate portion; depositing a first semiconductor material on the substrate portion to contact the first semiconductor layer; and depositing a first aluminum-containing layer. A first portion of the first aluminum-containing layer is located on the first semiconductor material, and a second portion of the first aluminum-containing layer is located on the spacers. The method further includes depositing a second semiconductor material on the first portion of the first aluminum-containing layer.

[0101] In some embodiments, the thickness of the first portion of the first aluminum-containing layer is substantially greater than the thickness of the second portion of the first aluminum-containing layer.

[0102] In some embodiments, the thickness of the first portion of the first aluminum-containing layer is about 0.2 nm to about 1.5 nm.

[0103] In some embodiments, the method further includes depositing a second aluminum-containing layer, wherein a first portion of the second aluminum-containing layer is located on the second semiconductor material, and a second portion of the second aluminum-containing layer is located on the second portion of the first aluminum-containing layer.

[0104] In some embodiments, the method further includes depositing a third semiconductor material on the first portion of the second aluminum-containing layer.

[0105] In some embodiments, the method further includes removing the second portion of the first aluminum-containing layer and the second portion of the second aluminum-containing layer.

[0106] In some embodiments, the method for removing the second portion of the first aluminum-containing layer and the second portion of the second aluminum-containing layer is a plasma process.

[0107] In some embodiments, the plasma process uses a hydrogen plasma.

[0108] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent replacements do not depart from the spirit and scope of the present invention, and can be changed, replaced, or modified without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device structure, characterized in that: include: A source / drain epitaxial structure, comprising: a first semiconductor material; a first aluminum-containing layer disposed on the first semiconductor material; and a second semiconductor material disposed on the first aluminum-containing layer; a first semiconductor layer contacting the source / drain epitaxial structure; and A gate layer is located on the first semiconductor layer.

2. The semiconductor device structure according to claim 1, wherein: The first aluminum-containing layer has a thickness of 0.2 nm to 1.5 nm.

3. The semiconductor device structure according to claim 1 or 2, wherein: The source / drain epitaxial structure also includes a second aluminum-containing layer located on the second semiconductor material, and a third semiconductor material located on the second aluminum-containing layer.

4. The semiconductor device structure according to claim 3, wherein: A portion of the first aluminum-containing layer is located on an upper surface of the first semiconductor material.

5. The semiconductor device structure according to claim 4, wherein: A portion of the second aluminum-containing layer is located on the portion of the first aluminum-containing layer and an upper surface of the second semiconductor material.

6. The semiconductor device structure according to claim 5, wherein: The thickness of the portion of the second aluminum-containing layer on the first aluminum-containing layer is less than the thickness of the portion of the second aluminum-containing layer on the upper surface of the second semiconductor material.

7. The semiconductor device structure according to claim 5, wherein: The third semiconductor material is located on the portion of the first aluminum-containing layer and the portion of the second aluminum-containing layer.

8. The semiconductor device structure according to claim 1 or 2, wherein: It also includes a second semiconductor layer contacting the source / drain epitaxial structure, and a third semiconductor layer contacting the source / drain epitaxial structure, wherein the second semiconductor layer is located on the first semiconductor layer, and the third semiconductor layer is located on the second semiconductor layer.

9. The semiconductor device structure according to claim 8, wherein: Also included are a plurality of dielectric spacers located between the first semiconductor layer and the second semiconductor layer and between the second semiconductor layer and the third semiconductor layer.

10. The semiconductor device structure according to claim 1 or 2, wherein: A gate dielectric layer is also included and is located between the first semiconductor layer and the gate layer.

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