Heterojunction cell and photovoltaic module

Abstract

The utility model discloses a heterojunction cell and a photovoltaic assembly, the heterojunction cell comprises a silicon wafer, an intrinsic layer, a doping layer and a transparent conductive layer, the intrinsic layer, the doping layer and the transparent conductive layer are sequentially stacked on the front surface or the back surface of the silicon wafer, the heterojunction cell further comprises a dielectric layer and an electrode, the dielectric layer is located on the transparent conductive layer, and the electrode is located on the transparent conductive layer. The electrode penetrates through the dielectric layer along the thickness direction of the silicon wafer and is in contact with the transparent conductive layer, and the thickness of the electrode is greater than that of the dielectric layer. According to the utility model, the patterned dielectric layer is formed on the transparent conductive layer, so that a finer grid line design can be realized, and the cell efficiency and the assembly power are improved; meanwhile, the patterned dielectric layer serves as a mask for preparing the electrode, expensive photosensitive ink does not need to be adopted, and the process cost is greatly reduced.

Description

Technical Field

[0001] The utility model belongs to the technical field of solar cells, and particularly relates to a heterojunction cell and a photovoltaic module. Background Art

[0002] A heterojunction cell (HJT) is a hybrid solar cell made of crystalline silicon wafers and amorphous silicon thin films, which has many advantages such as a simple preparation process, a low process temperature, a high open-circuit voltage, a high photoelectric conversion efficiency, and a low temperature coefficient. It is one of the most widely used high-efficiency crystalline silicon solar technologies at present.

[0003] Copper electroplated cell grid lines are the ultimate route for silver removal in the existing photovoltaic industry. The copper interconnection technology can effectively reduce the BOM cost of heterojunction cells and improve the competitiveness of heterojunction cell products. However, the existing copper interconnection technology requires semiconductor yellow light area equipment and photosensitive ink for the graphic preparation of electroplating masks, which greatly increases the manufacturing cost; at the same time, the grid line quality is closely related to the properties of the ink. A finer grid line design can obtain higher cell efficiency and module power, but it requires more expensive photosensitive ink.

[0004] Therefore, in view of the above technical problems, it is necessary to provide a heterojunction cell and a photovoltaic module. Summary of the Utility Model

[0005] The purpose of the utility model is to provide a heterojunction cell and a photovoltaic module to prepare fine grid electrodes, reduce the process cost, and improve the cell efficiency and module power.

[0006] In order to achieve the above purpose, the technical solution provided by an embodiment of the utility model is as follows:

[0007] A heterojunction cell includes a silicon wafer, an intrinsic layer, a doped layer, and a transparent conductive layer that are sequentially stacked on the front or back surface of the silicon wafer. The heterojunction cell further includes a dielectric layer and an electrode. The dielectric layer is located on the transparent conductive layer. The electrode penetrates the dielectric layer along the thickness direction of the silicon wafer and is in contact with the transparent conductive layer. The thickness of the electrode is greater than the thickness of the dielectric layer.

[0008] In one embodiment, the surface of the transparent conductive layer away from the silicon wafer is a plane, and the bottom surface of the electrode is flush with the bottom surface of the dielectric layer; or,

[0009] The surface of the transparent conductive layer away from the silicon wafer is formed with a groove, and the bottom surface of the electrode is lower than the bottom surface of the dielectric layer and is in contact with the bottom surface of the groove.

[0010] In one embodiment, the dielectric layer includes SiN X 、SiO X 、SiNO X, Al 2 O 3 、ZrO 2 、MgF 2 one or more layers of; and / or,

[0011] The thickness of the dielectric layer is 30 nm to 150 nm.

[0012] In one embodiment, the dielectric layer includes an outer dielectric layer and an inner dielectric layer. The thickness of the inner dielectric layer is less than that of the outer dielectric layer, and the refractive index of the inner dielectric layer is greater than or equal to that of the outer dielectric layer.

[0013] In one embodiment, the electrode includes a first electrode portion extending along the thickness direction of the silicon wafer into the dielectric layer and in contact with the transparent conductive layer, and a second electrode portion located above the first electrode portion and extending to the surface of the dielectric layer. The maximum width of the second electrode portion is greater than the maximum width of the first electrode portion.

[0014] In one embodiment, the width W1 at the top of the second electrode portion is less than the width W2 at the bottom of the second electrode portion, and the width at the top of the first electrode portion is equal to the width at the bottom of the first electrode portion.

[0015] In one embodiment, the maximum width of the first electrode portion is 1 μm to 25 μm, and the maximum width of the second electrode portion is less than or equal to 30 μm or is 5 μm to 15 μm; and / or,

[0016] The spacing between adjacent two electrodes is 500 μm to 1000 μm; and / or,

[0017] The total thickness of the electrode is 5 μm to 20 μm.

[0018] In one embodiment, the electrode includes a seed layer entirely or partially located in the dielectric layer and a first metal layer located on the seed layer. The total thickness of the seed layer and the first metal layer is 1 μm to 15 μm.

[0019] In one embodiment, the thickness of the seed layer is 100 nm to 800 nm; and / or,

[0020] The thickness of the seed layer is greater than or equal to the thickness of the dielectric layer; and / or,

[0021] The materials of the seed layer and the first metal layer are one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn.

[0022] In one embodiment, the electrode further includes a second metal layer coated on the outside of the seed layer and the first metal layer. The material of the second metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, and Sn, and the thickness of the second metal layer is 1 μm to 5 μm.

[0023] In one embodiment, the thickness of the transparent conductive layer is 15 nm to 150 nm; and / or,

[0024] The transparent conductive layer is a combination of one or more of ITO, VTTO, IWO, HITO, VTZO, AMTO, and TTO; and / or,

[0025] The carrier concentration of the transparent conductive layer is 0.6E20 cm -3 ~5E20 cm -3 , the mobility is 30 cm 2 / Vs~120 cm 2 / Vs, the contact resistivity is 0.8 mΩ·cm 2 ~4 mΩ·cm 2 , and the refractive index is 1.9 to 2.1.

[0026] In one embodiment, a first intrinsic layer, a first doped layer, a first transparent conductive layer, and a first dielectric layer are sequentially stacked on the front surface of the silicon wafer. A second intrinsic layer, a second doped layer, a second transparent conductive layer, and a second dielectric layer are sequentially stacked on the back surface of the silicon wafer. The electrode includes a first electrode that penetrates the first dielectric layer along the thickness direction of the silicon wafer and contacts the first transparent conductive layer, and a second electrode that penetrates the second dielectric layer along the thickness direction of the silicon wafer and contacts the second transparent conductive layer. The thickness of the first electrode is greater than the thickness of the first dielectric layer, and the thickness of the second electrode is greater than the thickness of the second dielectric layer.

[0027] The technical solution provided by another embodiment of the present utility model is as follows:

[0028] A photovoltaic module, the photovoltaic module includes a plurality of the above-mentioned heterojunction cells.

[0029] Compared with the prior art, the present utility model has the following beneficial effects:

[0030] By forming a patterned dielectric layer on the transparent conductive layer, the present utility model can achieve a finer grid line design, thereby improving the cell efficiency and module power; at the same time, the patterned dielectric layer serves as a mask for preparing the electrode, eliminating the need for expensive photosensitive inks, greatly reducing the process cost, and the dielectric layer can protect the underlying transparent conductive layer from corrosion. Description of the Drawings

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0032] Figure 1 Structural schematic diagram of the heterojunction battery in Comparative Example 1 of the present invention;

[0033] Figure 2 Structural schematic diagram of the heterojunction battery in Embodiment 1 of the present invention;

[0034] Figure 3 For Figure 2 Partial enlarged schematic diagram at position A in;

[0035] Figure 4 Structural schematic diagram of the first transparent conductive layer and the first dielectric layer in Embodiment 1 of the present invention;

[0036] Figure 5 Structural schematic diagram of the first electrode in Embodiment 1 of the present invention;

[0037] Figure 6 Another structural schematic diagram of the first electrode in Embodiment 1 of the present invention;

[0038] Figure 7 Structural schematic diagram of the heterojunction battery in Embodiment 2 of the present invention;

[0039] Figure 8 For Figure 7 Partial enlarged schematic diagram at position B in;

[0040] Figure 9 Partial structural schematic diagram of the first transparent conductive layer in Embodiment 2 of the present invention. Detailed implementation manners

[0041] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0042] In the present utility model, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may mean that the first feature is directly above or obliquely above the second feature, or merely indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "underneath" the second feature may mean that the first feature is directly below or obliquely below the second feature, or merely indicates that the horizontal height of the first feature is less than that of the second feature.

[0043] The present utility model discloses a heterojunction battery, which includes a silicon wafer and an intrinsic layer, a doping layer and a transparent conductive layer that are sequentially stacked on the front or back surface of the silicon wafer. The heterojunction battery further includes a dielectric layer and an electrode. The dielectric layer is located on the transparent conductive layer. The electrode penetrates the dielectric layer along the thickness direction of the silicon wafer and is in contact with the transparent conductive layer, and the thickness of the electrode is greater than the thickness of the dielectric layer.

[0044] The present utility model also discloses a photovoltaic module, which includes the above-mentioned heterojunction battery.

[0045] By forming a patterned dielectric layer on the transparent conductive layer in the present utility model, a finer grid line design can be achieved, thereby improving the battery efficiency and module power. At the same time, the patterned dielectric layer serves as a mask for preparing the electrode, eliminating the need for expensive photosensitive inks, significantly reducing the process cost, and the dielectric layer can protect the underlying transparent conductive layer and prevent the corrosion of the transparent conductive layer in the non-metal area.

[0046] The following further illustrates the present utility model with specific examples.

[0047] Comparative Example 1:

[0048] Refer Figure 1 The structure schematic diagram of the heterojunction battery in this comparative example is shown. The heterojunction battery includes:

[0049] A silicon wafer 10', which includes a front surface (i.e., the light-receiving surface) and a back surface (i.e., the light-blocking surface) that are oppositely arranged;

[0050] A first intrinsic layer 21', a first doping layer 31' and a first transparent conductive layer 41' that are sequentially stacked on the front surface;

[0051] A second intrinsic layer 22', a first doping layer 32' and a second transparent conductive layer 42' that are sequentially stacked on the back surface;

[0052] A first electrode 51', which is in contact with the first transparent conductive layer 41';

[0053] A second electrode 52', which is in contact with the second transparent conductive layer 42'.

[0054] Exemplarily, the silicon wafer 10’ is N-type doped; the first intrinsic layer 21’ is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer, and the first doped layer 31’ is an N-type doped amorphous silicon layer or a microcrystalline silicon layer; the second intrinsic layer 22’ is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer, and the second doped layer 32’ is a P-type doped amorphous silicon layer or a microcrystalline silicon layer; the first transparent conductive layer 41’ and the second transparent conductive layer 42’ can be one or a combination of one or more of transparent conductive layers such as ITO, VTTO, IWO, HITO, VTZO, AMTO, and TTO; the first electrode 51’ and the second electrode 52’ are both grid line electrodes.

[0055] Example 1:

[0056] Refer Figure 2 The following is a schematic structural diagram of the heterojunction battery in this embodiment. The heterojunction battery includes:

[0057] A silicon wafer 10, which includes a front side (i.e., the light-receiving surface) and a back side (i.e., the backlight surface) that are oppositely arranged, and a metal region and a non-metal region are respectively included on the front side and the back side;

[0058] The first intrinsic layer 21, the first doped layer 31, and the first transparent conductive layer 41 that are sequentially stacked on the front side;

[0059] The second intrinsic layer 22, the first doped layer 32, and the second transparent conductive layer 42 that are sequentially stacked on the back side;

[0060] The first dielectric layer 51 and the first electrode 61, and the first electrode 61 extends in the thickness direction of the silicon wafer in the front metal region to the inside of the first dielectric layer 51 and is in contact with the first transparent conductive layer 41;

[0061] The second dielectric layer 52 and the second electrode 62, and the second electrode 62 extends in the thickness direction of the silicon wafer in the back metal region to the inside of the second dielectric layer 52 and is in contact with the second transparent conductive layer 42.

[0062] In this embodiment, the silicon wafer 10 is an N-type silicon wafer, with a resistivity of 0.5 Ω·m to 3 Ω·m, a thickness of 90 μm to 120 μm, and a size of 210 mm. Further, a double-sided texturing process is also performed through an alkaline texturing process to form a pyramid texture light-trapping structure (not shown) on the surface, and the size of the pyramid structure is preferably 0.5 μm to 5 μm.

[0063] In this embodiment, the first intrinsic layer 21 and the second intrinsic layer 22 are intrinsic amorphous silicon layers or intrinsic microcrystalline silicon layers, the first doped layer 31 is an N-type doped (such as phosphorus doped) amorphous silicon layer or a microcrystalline silicon layer, and the second doped layer 32 is a P-type doped (such as boron doped) amorphous silicon layer or a microcrystalline silicon layer.

[0064] In this embodiment, the first transparent conductive layer 41 and the second transparent conductive layer 42 can be one or a combination of multiple transparent conductive layers such as ITO, VTTO, IWO, HITO, VTZO, AMTO, TTO, etc., preferably an ITO transparent conductive layer; the thickness is 15 nm to 150 nm, preferably 40 nm, and the carrier concentration is 0.6E20 cm -3 ~5E20 cm -3 ,preferably 3E20 cm -3 ; the mobility is 30 cm 2 / Vs~120 cm 2 / Vs, preferably 80 cm 2 / Vs; the contact resistivity is 0.8 mΩ·cm 2 ~4 mΩ·cm 2 ,preferably 2 mΩ·cm 2 ; the refractive index is 1.9~2.1.

[0065] The substrate, the intrinsic layer, the doped layer and the transparent conductive layer in this embodiment are exactly the same as those in Comparative Example 1 and will not be elaborated here. Different from Embodiment 1, a first dielectric layer 51 and a second dielectric layer 52 are added in this embodiment, and the structures of the first electrode 61 and the second electrode 62 are also different.

[0066] The second dielectric layer 52 and the second electrode 62 are exactly the same as the first dielectric layer 51 and the first electrode 61. Refer Figure 2 and in combination with Figures 3 to 6 as shown, the first dielectric layer 51 and the first electrode 61 on the front side of the silicon wafer will be described in detail below.

[0067] The first dielectric layer 51 in this embodiment includes SiN X , SiO X , SiNO X , Al 2 O 3 , ZrO 2 , MgF 2 , etc., or can be a multi-layer composite film. The thickness of the first dielectric layer 51 is 30 nm to 150 nm. When the first dielectric layer 51 is a multi-layer composite film structure, it includes an outer dielectric layer and an inner dielectric layer. The thickness of the inner dielectric layer is less than that of the outer dielectric layer, and the refractive index of the inner dielectric layer is greater than or equal to that of the outer dielectric layer.

[0068] Refer Figure 3 as shown, in this embodiment, the SiNO X layer and the SiN X layer are respectively selected as the outer dielectric layer 502 and the inner dielectric layer 501, SiNO XThe refractive index n of the layer is ~1.9, and the thickness is ~15 nm, SiN X The refractive index n of the layer is ~2.15, and the thickness is ~35 nm. The thickness of the entire first dielectric layer 51 is ~50 nm. SiNO X layer and SiN X layers can be deposited on the first transparent conductive layer 41 by a low-temperature PECVD process.

[0069] As shown in Figure 4 , the first dielectric layer 51 is patterned by a laser process to completely remove the first dielectric layer in the metal region, exposing the underlying first transparent conductive layer 41, thereby forming a plurality of first windows 511 penetrating to the first transparent conductive layer 41. Preferably, in this embodiment, a green laser is used to remove the first dielectric layer 51 on the metal region, with a pulse width of 300 ps to 700 ps and an energy density of 0.3 J / cm 2 ~5 J / cm 2 .

[0070] Specifically, by controlling the laser parameters in the laser process, only the first dielectric layer on the first transparent conductive layer can be removed. The depth of the first window 511 is the thickness of the first dielectric layer 51, and the width of the first window is 1 μm to 25 μm, preferably 2 nm to 10 nm. Exemplarily, the width of the first window is ~5 μm and the depth is ~50 nm.

[0071] In other embodiments, the first window 511 can also be formed by other processes, such as a wet etching process, rather than being limited to the aforementioned laser process. In some embodiments, the first window may not be prepared separately, but instead formed synchronously during the electrode preparation process, which will not be elaborated here.

[0072] The first electrode 61 in this embodiment is a gate line electrode. As shown in Figure 2 , Figure 3 and Figure 5 , the first electrode 61 includes a first electrode portion 611 extending in the thickness direction of the silicon wafer into the first dielectric layer 51 and in contact with the first transparent conductive layer 41, and a second electrode portion 612 located above the first electrode portion 611 and extending to the surface of the first dielectric layer 51, and the maximum width of the second electrode portion 612 is greater than the maximum width of the first electrode portion 611. In addition, the surface of the first transparent conductive layer 41 away from the silicon wafer is a plane, and the bottom surface of the first electrode portion 611 is flush with the bottom surface of the first dielectric layer 51.

[0073] Further, the width W1 at the top of the second electrode portion 612 is smaller than the width W2 at the bottom of the second electrode portion 612. The side surface of the second electrode portion 612 is arranged as an inclined surface. At the same time, the width W2 at the bottom of the second electrode portion 612 is greater than the width of the first electrode portion (i.e., the width of the first window 511). In this embodiment, the width of the first electrode portion 611 is a constant value W3 in the direction of the silicon wafer thickness. Thus arranged, the maximum width of the first electrode portion 611 is W3, and the maximum width of the second electrode portion 612 is W2.

[0074] In some embodiments, the side surface of the second electrode portion 612 can be other shapes, such as regular or irregular curved surfaces, etc. Any solution that satisfies the width W1 at the top of the second electrode portion 612 being smaller than the width W2 at the bottom of the second electrode portion 612 falls within the scope protected by the present utility model.

[0075] Specifically, the thickness of the first electrode portion 612 (i.e., the thickness of the first dielectric layer) is 30 nm to 150 nm, preferably 100 nm. The maximum width W3 of the first electrode portion (i.e., the width of the first window 511) is 1 μm to 25 μm, preferably 10 μm. The maximum width W2 at the bottom of the second electrode portion 612 is 10 μm to 30 μm, preferably 5 μm to 15 μm. The width W1 at the top of the second electrode portion 612 is preferably between W3 and W2, such as 12 μm.

[0076] In addition, in this embodiment, the total thickness of the first electrode is 5 μm to 20 μm, preferably 10 μm, and the spacing between adjacent two first electrodes is 500 μm to 1000 μm.

[0077] The first electrode in the present utility model is a gate line electrode, which can be a main gate line or a fine gate line. The line width and spacing of the main gate line and the fine gate line are designed according to actual requirements and will not be elaborated here.

[0078] Refer Figure 6 As shown, the first electrode 61 in this embodiment is prepared by PVD, electroplating or electroless plating processes. The first electrode 61 includes a seed layer 601 that is entirely or partially located in the first dielectric layer and a first metal layer 602 located on the seed layer 601. The total thickness of the seed layer 601 and the first metal layer 602 is 1 μm to 15 μm. Further, it also includes a second metal layer 603 coated on the outer sides of the seed layer 601 and the first metal layer 602.

[0079] Specifically, the seed layer 601 and the first metal layer 602 are made of the same material, which can be one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc. The thickness of the seed layer is 100 nm to 800 nm; the material of the second metal layer 603 is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc., and the thickness of the second metal layer is 1 μm to 5 μm. Preferably, both the seed layer 601 and the first metal layer 602 are Cu metal layers, the total thickness of the seed layer 601 and the first metal layer 602 is about 7 μm, the second metal layer 603 is a Sn metal layer, and the thickness is about 3 μm. The total thickness of the entire first electrode is about 10 μm.

[0080] Among them, the seed layer can be prepared by PVD (Physical Vapor Deposition), electroplating or electroless plating processes, and the first metal layer and the second metal layer can be prepared by electroplating or electroless plating processes.

[0081] Taking electroplated copper as an example for the first metal layer, the electroplated copper solution includes copper sulfate, sulfuric acid, copper balls, and additives that can optimize the crystal structure of the copper layer. The concentration of Cu in the electroplated copper solution 2+ is 50 g / L, and the concentration of sulfuric acid is 40 g / L.

[0082] Taking electroplated tin as an example for the second metal layer, the electroplated tin solution includes stannous methylsulfonate and tin plating additives. The concentration of Sn in the electroplated tin solution 2+ is 30 g / L, and the concentration of methylsulfonic acid is 200 g / L.

[0083] In a preferred embodiment, the thickness of the seed layer 601 is greater than the thickness of the first dielectric layer 51 (i.e., the depth of the first window 511). In this way, the prepared seed layer not only fills the inside of the first window 511 but also covers the surface of the first dielectric layer 51 beside the first window 511. In this case, the entire first electrode portion 611 is the seed layer, and the outside of the second electrode portion 612 is the second metal layer, and the inside is the first metal layer and a part of the seed layer.

[0084] In other embodiments, the thickness of the seed layer can also be equal to the thickness of the first dielectric layer 51 or less than the thickness of the first dielectric layer 51. In this way, the seed layer is only formed inside the first window 511.

[0085] The above has described in detail the first dielectric layer 51 and the first electrode 61 on the front side of the silicon wafer in this embodiment. The second dielectric layer 52 and the second electrode 62 on the back side of the silicon wafer are exactly the same as the first dielectric layer 51 and the first electrode 61 on the front side of the silicon wafer, and will not be elaborated here.

[0086] Furthermore, the first electrode 61 and the second electrode 62 in the present utility model can also be prepared by screen printing process. By printing conductive paste at the window of the dielectric layer and curing it to form a metallized structure, the electrode material can be one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc. The screen printing process is a conventional process and will not be elaborated here.

[0087] Example 2:

[0088] Refer Figure 7 and combine with Figure 8 、 Figure 9 As shown, the heterojunction battery in this embodiment is basically the same as the heterojunction battery in Example 1. The difference is that a groove 411 is formed on the surface of the first transparent conductive layer 41 away from the silicon wafer, and the bottom surface of the first electrode part in the first electrode 51 is lower than the bottom surface of the first dielectric layer 51 and is in contact with the bottom surface of the groove 411.

[0089] Similarly, the structures of the second transparent conductive layer 42, the second dielectric layer 52 and the second electrode 62 are exactly the same as those of the first transparent conductive layer 41, the first transparent conductive layer 51 and the first electrode 61, and will not be elaborated here.

[0090] Among them, the groove on the surface of the first transparent conductive layer 41 can be formed by laser process or etching process, etc., and will not be elaborated here.

[0091] IV performance tests were carried out on different heterojunction batteries, and the test data are as follows in the table:

[0092]

[0093] Among them, Control Group 1 is the heterojunction battery structure in Comparative Example 1, and the grid electrodes on the front and back are both prepared by screen printing with low-temperature silver paste. The grid line width is ~25μm and the number is 60;

[0094] Control Group 2 is the heterojunction battery structure in Comparative Example 1, and the grid electrodes on the front and back are both prepared by copper interconnection technology. The grid line width is ~15μm and the number is 100;

[0095] Experimental Group 1 is the heterojunction battery structure in Example 1, with dielectric layers on both the front and back. The grid electrode structure refers to Example 1. The grid line width is ~10μm and the number is 150.

[0096] It can be seen that in Experimental Group 1, by introducing the dielectric layer, compared with the two control groups, finer grid electrodes can be prepared, with smaller line width and spacing.

[0097] Compared with Control Group 1, in Control Group 2, for the copper interconnect technology compared with the conventional printing technology, the grid lines have become finer, the series resistance Rs has decreased, the fill factor FF has increased by 0.75%, and the cell efficiency Eta has increased by 0.25%.

[0098] Compared with Control Group 2, in Experimental Group 1, compared with the traditional copper interconnect technology, introducing a dielectric layer can further refine the grid lines. However, due to the presence of the dielectric layer, the overall series resistance Rs slightly increases, the fill factor FF decreases by 0.72%, but the optical gain (short - circuit current density Jsc) can increase by 0.5 mA / cm 2 , and finally the cell efficiency can be increased by about 0.1%.

[0099] Furthermore, in the present utility model, a pulsed laser can be used to modify the exposed transparent conductive layer in the window, so that the transparent conductive layer can obtain a higher carrier concentration, a higher mobility, and a lower contact resistivity. Exemplarily, an infrared laser can be used for the modification treatment, with a pulse width of 100 ns - 800 ns and an energy density of 0.54 J / cm 2 ~6 J / cm 2 .

[0100] Before the modification treatment, the carrier concentration of the transparent conductive layer in the window is 0.6E20 cm -3 ~5E20 cm -3 , preferably 3E20 cm -3 , the mobility is 30 cm 2 / Vs ~ 120 cm 2 / Vs, preferably 80 cm 2 / Vs, and the contact resistivity is 0.8 mΩ·cm 2 ~4 mΩ·cm 2 , preferably 2 mΩ·cm 2 ; after the modification treatment, the carrier concentration of the transparent conductive layer in the window is 2.5E20 cm -3 ~6.5E20 cm -3 , preferably 4.5E20 cm -3 , the mobility is 40 cm 2 / Vs ~ 150 cm 2 / Vs, preferably 88 cm 2 / Vs, and the contact resistivity is 0.4 mΩ·cm 2 ~3 mΩ·cm 2 , preferably 1.5 mΩ·cm 2 .

[0101] It can be seen that through the pulsed laser modification treatment, the carrier concentration can be increased by ~1.5E20 cm -3 , and the mobility can be increased by ~8 cm 2 / Vs, the contact resistivity can be reduced by ~0.5 mΩ·cm 2 . On the premise of ensuring the maintenance of the optical gain (short-circuit current density Jsc), the contact resistivity can be reduced, and the cell efficiency Eta can be further increased by 0.05%.

[0102] For those skilled in the art, it is obvious that the present utility model is not limited to the details of the above exemplary embodiments, and the present utility model can be implemented in other specific forms without departing from the spirit or basic characteristics of the present utility model. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present utility model is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present utility model. Any reference signs in the claims should not be construed as limiting the claims involved.

[0103] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A heterojunction battery, characterized in that: It includes a silicon wafer and an intrinsic layer, a doped layer and a transparent conductive layer stacked in sequence on the front or back side of the silicon wafer. The heterojunction battery also includes a dielectric layer and an electrode. The dielectric layer is located on the transparent conductive layer. The electrode penetrates the dielectric layer along the thickness direction of the silicon wafer and contacts the transparent conductive layer. The thickness of the electrode is greater than the thickness of the dielectric layer.

2. The heterojunction battery according to claim 1, characterized in that: The surface of the transparent conductive layer away from the silicon wafer is a plane, and the bottom surface of the electrode is flush with the bottom surface of the dielectric layer.

3. The heterojunction battery according to claim 1, characterized in that: A groove is formed on the surface of the transparent conductive layer away from the silicon wafer, and the bottom surface of the electrode is lower than the bottom surface of the dielectric layer and contacts with the bottom surface of the groove.

4. The heterojunction battery according to claim 1, characterized in that: The dielectric layer includes SiN X 、SiO X 、SiNO X , one or more layers of Al2O3, ZrO2, MgF2; and / or, The thickness of the dielectric layer is 30nm-150nm.

5. The heterojunction battery according to claim 1, characterized in that: The dielectric layer comprises an outer dielectric layer and an inner dielectric layer, the thickness of the inner dielectric layer is smaller than that of the outer dielectric layer, and the refractive index of the inner dielectric layer is greater than or equal to the refractive index of the outer dielectric layer.

6. The heterojunction battery according to claim 2 or 3, characterized in that: The electrode includes a first electrode portion extending into the dielectric layer along the thickness direction of the silicon wafer and contacting the transparent conductive layer, and a second electrode portion located above the first electrode portion and extending to the surface of the dielectric layer, wherein the maximum width of the second electrode portion is greater than the maximum width of the first electrode portion.

7. The heterojunction battery according to claim 6, characterized in that: The width W1 of the top of the second electrode portion is smaller than the width W2 of the bottom of the second electrode portion, and the width of the top of the first electrode portion is equal to the width of the bottom of the first electrode portion.

8. The heterojunction battery according to claim 7, characterized in that: The maximum width of the first electrode portion is 1 μm to 25 μm, and the maximum width of the second electrode portion is less than or equal to 30 μm or is 5 μm to 15 μm; and / or, The distance between two adjacent electrodes is 500 μm to 1000 μm; and / or, The total thickness of the electrode is 5 μm to 20 μm.

9. The heterojunction battery according to claim 1, characterized in that: The electrode comprises a seed layer which is entirely or partially located in the dielectric layer and a first metal layer which is located on the seed layer. The total thickness of the seed layer and the first metal layer is 1 μm to 15 μm.

10. The heterojunction battery according to claim 9, characterized in that: The thickness of the seed layer is 100 nm to 800 nm; and / or, The thickness of the seed layer is greater than or equal to the thickness of the dielectric layer.

11. The heterojunction battery according to claim 9, characterized in that: The electrode further comprises a second metal layer covering the seed layer and the outer side of the first metal layer, and the thickness of the second metal layer is 1 μm to 5 μm.

12. The heterojunction battery according to claim 1, characterized in that: The thickness of the transparent conductive layer is 15 nm to 150 nm.

13. The heterojunction battery according to claim 1, characterized in that: A first intrinsic layer, a first doped layer, a first transparent conductive layer and a first dielectric layer are sequentially stacked on the front side of the silicon wafer, and a second intrinsic layer, a second doped layer, a second transparent conductive layer and a second dielectric layer are sequentially stacked on the back side of the silicon wafer. The electrode comprises a first electrode that penetrates the first dielectric layer along the thickness direction of the silicon wafer and contacts the first transparent conductive layer, and a second electrode that penetrates the second dielectric layer along the thickness direction of the silicon wafer and contacts the second transparent conductive layer. The thickness of the first electrode is greater than the thickness of the first dielectric layer, and the thickness of the second electrode is greater than the thickness of the second dielectric layer.

14. A photovoltaic module, characterized in that: The photovoltaic module comprises the heterojunction cell according to any one of claims 1 to 13.

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