Gate driving circuit with anti-noise and light-emitting driving functions
By designing a gate driving circuit with anti-noise and light-emitting driving functions, integrating the gate driving block and light-emitting driving block, and adopting the configuration of an anti-noise startup circuit and an anti-noise circuit, the problems of complex circuit design and excessive number of components in the prior art are solved, and efficient anti-noise and light-emitting driving functions are achieved, reducing costs and improving the yield of the circuit.
Patent Information
- Application Number
- CN202422081807.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-27
- Publication Date
- 2025-06-13
- Estimated Expiration
- 2034-08-27
AI Technical Summary
In the prior art, in the active Mini-LED array backboard circuit design, it is necessary to provide sequential square waves and luminous signals respectively, resulting in excessive number of circuit components and complex design.
A gate driving circuit with anti-noise and light-emitting driving functions is designed. By integrating the gate driving block and the light-emitting driving block, the anti-noise startup circuit, the first anti-noise circuit and the second anti-noise circuit are adopted to ensure effective noise immunity in different working areas.
By integrating circuit blocks and noise-impact circuits, process costs are reduced, the yield of integrated circuits is improved, and narrow border effect is achieved, while ensuring the noise-impact capability of gate drive blocks and light-emitting drive blocks in all periods at different times.
Smart Images
Figure CN222980145U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a gate driving circuit, in particular to a gate driving circuit with anti-noise and light-emitting driving functions. Background Art
[0002] In recent years, the backplane circuit design of active matrix micro light-emitting diodes (Mini-LEDs) has become increasingly popular. Driving Mini-LEDs requires providing a sequential square wave and an emission signal (EM signal). In the early backplane circuit design, the sequential square wave was provided by a gate driver on array (GOA), and the emission signal was provided by an emission driver on array (EOA).
[0003] With the development of active mini-LED array driving, the design of the backplane circuit is also very important. If the emission signal requires an additional circuit to provide, and the backplane circuit must have GOA and EOA circuits, and the pixel circuit of the TFT layer also needs to design a GOA circuit, the number of components will be too large.
[0004] Therefore, how to improve the circuit design to integrate the GOA circuit and the EOA circuit to overcome the above defects has become an important issue to be solved in this field. Summary of the Utility Model
[0005] The technical problem to be solved by the utility model is to provide a gate driving circuit with anti-noise and light-emitting driving functions in view of the deficiencies of the prior art.
[0006] To solve the above technical problems, one of the technical solutions adopted by the present utility model is to provide a gate driving circuit with anti-noise and light-emitting driving functions, which is characterized in that the gate driving circuit with anti-noise and light-emitting driving functions includes: an anti-noise startup circuit that receives a synchronous voltage signal and provides a first anti-noise startup signal that acts at least in a first non-operating interval during a sequence driving period, and a second anti-noise startup signal that acts at least in a second non-operating interval during a light-emitting period; a gate driving block, including: a gate driving sub-circuit that receives a serial input signal and an input frequency signal and charges a first output node to generate a gate driving sequence signal in a first operating interval during the sequence driving period; and a first anti-noise circuit connected to the first output node and receiving the first anti-noise startup signal to maintain the first output node at a low level at least in the first non-operating interval; a light-emitting driving block, including: a light-emitting driving circuit that receives a simultaneous output signal and the synchronous voltage signal and charges a second output node in a second operating interval during the light-emitting period to generate a synchronous light-emitting signal; and a second anti-noise circuit connected to the second output node, receiving the second anti-noise startup signal and maintaining the voltage of the second output node at a low level at least in the second non-operating interval.
[0007] Optionally, the gate driving sub-circuit includes: a first transistor, the first end and the control end of the first transistor receive the serial input signal, and the second end of the first transistor is connected to a first node; a second transistor, the first end of the second transistor receives the input frequency signal, the control end of the second transistor is connected to the first node, and the third end of the second transistor is connected to the first output node; and a first capacitor connected between the control end and the second end of the second transistor.
[0008] Optionally, in the first non-operating interval, the serial input signal is at a high level to charge the first node to a high potential, and the input frequency signal is at a low level to make the first output node at a low level; wherein, in the first operating interval, the serial input signal is at a low level, the input frequency signal is at a high level to charge the first output node to a high potential, and through the coupling of the first capacitor, the level of the first node is increased.
[0009] Optionally, the anti-noise startup circuit includes: a third transistor, a first end and a control end of the third transistor receiving a first voltage signal, a second end of the third transistor being connected to a second node; a fourth transistor, a first end of the fourth transistor being connected to the second node, a control end of the fourth transistor receiving the synchronization voltage signal, a second end of the fourth transistor receiving a second voltage signal; a fifth transistor, a first end of the fifth transistor being connected to the first anti-noise circuit, a control end of the fifth transistor being connected to the second node, a second end of the fifth transistor being connected to the second anti-noise circuit through a third node; and a sixth transistor, a first end of the sixth transistor being connected to the third node, a control end of the sixth transistor receiving the synchronization voltage signal, a second end of the sixth transistor receiving the second voltage signal.
[0010] Optionally, the first voltage signals are all at a high level, the second voltage signals are all at a low level. In the first non-operating interval, the synchronization voltage signal is at a low level, the third transistor is turned on, the fourth transistor and the sixth transistor are turned off, and the second node being at a high level turns on the fifth transistor to serve as the first anti-noise startup signal to cause the first anti-noise circuit to discharge the first output node to a low potential.
[0011] Optionally, the first anti-noise circuit includes: a seventh transistor, a first end and a control end of the seventh transistor receiving the first voltage signal, a second end of the seventh transistor being connected to a fourth node; an eighth transistor, a first end of the eighth transistor receiving the first voltage signal, a control end of the eighth transistor being connected to the fourth node, a second end of the eighth transistor being connected to the first end of the fifth transistor; a ninth transistor, a first end of the ninth transistor being connected to the fourth node, a control end of the ninth transistor receiving the serial input signal, a second end of the ninth transistor receiving the second voltage signal; a tenth transistor, a first end of the tenth transistor being connected to the fourth node, a control end of the tenth transistor being connected to the first output node, a second end of the tenth transistor receiving the second voltage signal; an eleventh transistor, a first end of the eleventh transistor being connected to the second end of the eighth transistor, a control end of the eleventh transistor being connected to the first output node, a second end of the eleventh transistor receiving the second voltage signal; a twelfth transistor, a first end of the twelfth transistor being connected to the first node, a control end of the twelfth transistor being connected to the first end of the fifth transistor, a second end of the twelfth transistor receiving the second voltage signal; and a thirteenth transistor, a first end of the thirteenth transistor being connected to the first output node, a control end of the thirteenth transistor being connected to the first end of the fifth transistor, a second end of the thirteenth transistor receiving the second voltage signal.
[0012] Optionally, in the first non-operating interval, the serial input signal is at a high level, causing the ninth transistor to conduct, the seventh transistor and the eighth transistor to conduct in response to the first voltage signal, causing the twelfth transistor and the thirteenth transistor to conduct and pull the first output node to a low level, and in response to the first output node being at a low level, the tenth transistor and the eleventh transistor are turned off.
[0013] Optionally, the light-emitting driving circuit includes: a fourteenth transistor, a first end of the fourteenth transistor receiving the simultaneous output signal, a control end of the fourteenth transistor being connected to a fifth node, a second end of the fourteenth transistor being connected to the second output node; a fifteenth transistor, a first end and a control end of the fifteenth transistor receiving the synchronous voltage signal, a second end of the fifteenth transistor being connected to the fifth node; and a second capacitor, connected between the control end and the second end of the fourteenth transistor.
[0014] Optionally, in the second non-operating interval, the synchronous voltage signal is at a high level, the simultaneous output signal is at a low level, the second capacitor is pre-charged, the fifth transistor is turned off, and the fourth transistor and the sixth transistor are turned on, and the second output node is maintained at a low level; wherein, in the second operating interval, the synchronous voltage signal and the simultaneous output signal are at a high level, the second output node is pulled to a high level in response to the simultaneous output signal, and the level of the fifth node is increased by coupling through the second capacitor.
[0015] Optionally, the second anti-noise circuit includes: a sixteenth transistor, a first end of the sixteenth transistor is connected to the fifth node, a control end of the sixteenth transistor is connected to the third node, and a second end of the sixteenth transistor receives the second voltage signal; a seventeenth transistor, a first end of the seventeenth transistor is connected to the second output node, a control end of the seventeenth transistor is connected to the third node, and a second end of the seventeenth transistor receives the second voltage signal; wherein, in the first non-operating interval, the sixteenth transistor and the seventeenth transistor are turned on to pull the second output node to a low potential.
[0016] One beneficial effect of the present invention is that the gate drive circuit with anti-noise and light-emitting drive functions provided by the present invention can reduce the manufacturing cost and improve the yield of integrated circuits, and can also achieve the effect of a narrow border through the technical solution of integrating the gate drive block and the light-emitting drive block.
[0017] In addition, for the gate drive circuit with anti-noise and light-emitting drive functions provided by the present invention, through the configuration of the anti-noise startup circuit, the first anti-noise circuit and the second anti-noise circuit, when the gate drive block is in session, the light-emitting drive block can be anti-noise all the time, and when the light-emitting drive block is in session, the gate drive block can be anti-noise all the time.
[0018] To enable a further understanding of the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the provided drawings are only for reference and illustration, and are not used to limit the present invention. Brief Description of the Drawings
[0019] Figure 1 It is a block diagram of the gate drive circuit with anti-noise and light-emitting drive functions according to an embodiment of the present invention.
[0020] Figure 2 It is a circuit diagram of the gate drive sub-circuit according to an embodiment of the present invention.
[0021] Figure 3This is the circuit diagram of the anti-noise startup circuit according to an embodiment of the present invention.
[0022] Figure 4 This is the circuit diagram of the first anti-noise circuit according to an embodiment of the present invention.
[0023] Figure 5 This is the circuit diagram of the light-emitting drive circuit according to an embodiment of the present invention.
[0024] Figure 6 This is the circuit diagram of the second anti-noise circuit according to an embodiment of the present invention.
[0025] Figure 7 This is the timing diagram of the signals of the gate drive circuit with anti-noise and light-emitting drive functions according to an embodiment of the present invention.
[0026] Figure 8 、 9 They are respectively the simulation waveform results of the gate drive sequence signal Out[n] and the synchronous light-emitting signal Sn of the gate drive circuit according to an embodiment of the present invention at levels 10, 100, 150, 180 and at normal temperature (25°C), high temperature (85°C), and low temperature (-40°C). Detailed implementation manners
[0027] The following are specific embodiments to illustrate the implementation manners of the present invention regarding the "gate drive circuit with anti-noise and light-emitting drive functions". Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. Additionally, the drawings of the present invention are only for simple schematic illustration and are not drawn according to actual dimensions, which is stated in advance. The following implementation manners will further detail the relevant technical content of the present invention, but the disclosed content is not used to limit the protection scope of the present invention. Additionally, the term "or" used herein should, depending on the actual situation, possibly include any one or a combination of more of the associated listed items.
[0028] Refer to Figure 1 As shown, an embodiment of the present invention provides a gate drive circuit 1 with anti-noise and light-emitting drive functions, including an anti-noise startup circuit 10, a gate drive block 12, and a light-emitting drive block 14.
[0029] The anti-noise startup circuit 10 is configured to be controlled by a synchronous voltage signal Vst to provide a first anti-noise startup signal S1 that acts at least in a first non-operating interval during sequence driving, and a second anti-noise startup signal S2 that acts at least in a second non-operating interval during light emission.
[0030] The gate driving block 12 includes a gate driving sub-circuit 120 and a first anti-noise circuit 122. The gate driving sub-circuit 120 is configured to charge a first output node No1 according to a serial input signal Out[n - 4] and an input frequency signal CLK1 to generate a gate driving sequence signal Out[n] in a first working period during sequential driving. The gate driving sequence signal Out[n] can be input into a pixel compensation circuit in a display device. The purpose of the gate driving block 12 is to output a sequential square wave (i.e., the gate driving sequence signal Out[n]) during the reset period and the compensation period of the pixel circuit, and this square wave can be used to drive an active compensation circuit such as a Mini-LED display. However, the present utility model is not limited thereto, and the gate driving circuit provided by the present utility model can be applied to pixel circuits of AMOLED, Mini-LED, and Micro-LED.
[0031] It should be noted that when the display is operating, the gate driving circuit may be in the off state most of the time to ensure that the internal liquid crystal maintains the required display color voltage value. However, during circuit operation, it may be interfered by noise from a voltage source, a frequency signal (AC signal), or parasitic capacitance coupling. This may cause the first output node No1 to be erroneously turned on, and further cause the display panel to flicker or show an incorrect image. For this reason, the present utility model designs a first anti-noise circuit 122, which is connected to the first output node No1 and is controlled by a first anti-noise activation signal S1 to keep the gate driving sequence signal Out[n] of the first output node No1 at a low level at least in a first non-working period during sequential driving.
[0032] On the other hand, the light emitting driving block 14 includes a light emitting driving circuit 140 and a second anti-noise circuit 142. The light emitting driving circuit 140 is configured to be controlled by a simultaneous output signal S_Sig and a synchronous voltage signal Vst to charge a second output node No2 in a second working period during light emission to generate a synchronous light emission signal Sn. The purpose of the light emitting driving circuit 140 to generate the synchronous light emission signal Sn (for example, a synchronous square wave signal) is to control a driving transistor that supplies current to each light emitting diode in the display device.
[0033] Similar to the first output node No1 of the gate driving sub-circuit 120, the second output node No2 may also be erroneously turned on due to noise interference from a voltage source, a frequency signal (AC signal), or parasitic capacitance coupling. Therefore, the present utility model also designs a second anti-noise circuit 142, which is connected to the second output node and is controlled by a second anti-noise activation signal S2 to keep the synchronous light emission signal Sn of the second output node No2 at a low level at least in a second non-working period.
[0034] The above content only briefly describes the specific architecture of the gate driving circuit 1 with anti-noise and light-emitting driving functions of the present invention. The details of each block will be described in more detail below.
[0035] Refer to Figures 2 to 6 as shown, Figure 2 is the circuit diagram of the gate driving circuit according to an embodiment of the present invention, Figure 3 is the circuit diagram of the anti-noise startup circuit according to an embodiment of the present invention, Figure 4 is the circuit diagram of the gate driving circuit, the anti-noise startup circuit and the first anti-noise circuit according to an embodiment of the present invention, Figure 5 is the circuit diagram of the light-emitting driving circuit according to an embodiment of the present invention, Figure 6 is the complete circuit diagram of the gate driving circuit with anti-noise and light-emitting driving functions according to an embodiment of the present invention.
[0036] In the following description, each transistor may be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET) or an amorphous silicon thin-film transistor, and the first terminal, the second terminal and the control terminal of the transistor may be the source electrode, the drain electrode and the gate electrode respectively. However, the above is only an example, and the present invention is not limited thereto.
[0037] As Figure 2 shown, the gate driving sub-circuit 120 includes a first transistor T1, a second transistor T2 and a first capacitor C1. The first terminal and the control terminal of the first transistor T1 receive the serial input signal Out[n-4], and the second terminal of the first transistor T1 is connected to the first node N1. The first terminal of the second transistor T2 receives the input frequency signal CLK1, the control terminal of the second transistor T2 is connected to the first node N1, and the third terminal of the second transistor T2 is connected to the first output node No1. The first capacitor C1 is connected between the control terminal and the second terminal of the second transistor T2.
[0038] Figure 7 is the timing diagram of the signals of the gate driving circuit with anti-noise and light-emitting driving functions according to an embodiment of the present invention. Please refer to Figure 7 , the gate driving circuit 1 with anti-noise and light-emitting driving functions provided by the present invention can operate during the serial driving period P1 and the light-emitting period P2. Among them, the serial driving period P1 includes a first non-working interval P1-1, a first working interval P1-2 and a third non-working interval P1-3, and the light-emitting period P2 includes a second non-working interval P2-1, a second working interval P2-2 and a fourth non-working interval P2-3.
[0039] In the first non-operating interval P1-1, the serial input signal Out[n-4] from the other gate drive circuit 1 is at a high level, causing the first node N1 to be charged to a high potential, and the input frequency signal CLK1 is at a low level, causing the first output node No1 to be at a low level.
[0040] In the first operating interval P1-2, the serial input signal Out[n-4] is at a low level, and the input frequency signal CLK1 is at a high level, causing the first output node No1 to be charged to a high potential and, through coupling by the first capacitor C1, causing the level of the first node N1 to rise. Through coupling by the first capacitor C1, the first node N1 can be coupled to a higher voltage, enabling the second transistor T2 to turn on more completely. In the first operating interval P1-2, a gate drive sequence signal Out[n] can be generated at the first output node No1.
[0041] Please refer further to Figure 3 , the anti-noise startup circuit may include a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. The first end and the control end of the third transistor T3 receive a first voltage signal VH, and the second end of the third transistor T3 is connected to the second node N2. The first end of the fourth transistor T4 is connected to the second node N2, the control end of the fourth transistor T4 receives a synchronization voltage signal Vst, and the second end of the fourth transistor T4 receives a second voltage signal VSS. The first voltage signal VH may be, for example, a voltage signal with a high level, and its voltage may be, for example, 20V. The second voltage signal VSS may be, for example, a voltage signal with a low level, and its voltage may be, for example, -5V.
[0042] The first end of the fifth transistor T5 is connected to the first anti-noise circuit 122, the control end of the fifth transistor T5 is connected to the second node N2, and the second end of the fifth transistor T5 is connected to the second anti-noise circuit 142 through the third node N3. The first end of the sixth transistor T6 is connected to the third node N3, the control end of the sixth transistor T6 receives the synchronization voltage signal Vst, and the second end of the sixth transistor T6 receives the second voltage signal VSS.
[0043] As Figure 7 shown, in the first non-operating interval P1-1, the high-level first voltage signal VH turns on the third transistor T3, the synchronization voltage signal Vst is at a low level, turning off the fourth transistor T4 and the sixth transistor T6, and the high level of the second node N2 turns on the fifth transistor T5 to serve as the first anti-noise startup signal S1 to cause the first anti-noise circuit 122 to discharge the first output node No1 to a low level.
[0044] During the second non-operating period P2-1, the high-level first voltage signal VH turns on the third transistor T3, and the synchronous voltage signal Vst is at a high level, turning on the fourth transistor T4 and the sixth transistor T6. However, the second node N2 is pulled to a low level, turning off the fifth transistor T5. At this time, the sixth transistor T6 is turned on, pulling the voltage of the third node N3 to a low potential, serving as the second anti-noise start signal S2 to cause the second anti-noise circuit 142 to maintain the first output node No1 at a low potential.
[0045] Please refer to Figure 4 , which shows the specific connection relationships of the anti-noise start circuit 10, the gate drive sub-circuit 120, and the first anti-noise circuit 122. The first anti-noise circuit 122 may include a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13. The first end and the control end of the seventh transistor T7 receive the first voltage signal VH, and the second end of the seventh transistor T7 is connected to the fourth node N4. The first end of the eighth transistor T8 receives the first voltage signal VH, the control end of the eighth transistor T8 is connected to the fourth node N4, and the second end of the eighth transistor T8 is connected to the first end of the fifth transistor T5.
[0046] Furthermore, the first end of the ninth transistor T9 is connected to the fourth node N4, the control end of the ninth transistor T9 receives the serial input signal Out[n-4], and the second end of the ninth transistor T9 receives the second voltage signal VSS. The first end of the tenth transistor T10 is connected to the fourth node N4, the control end of the tenth transistor T10 is connected to the first output node No1, and the second end of the tenth transistor T10 receives the second voltage signal VSS. The first end of the eleventh transistor T11 is connected to the second end of the eighth transistor T8, the control end of the eleventh transistor T11 is connected to the first output node No1, and the second end of the eleventh transistor T11 receives the second voltage signal VSS.
[0047] The first end of the twelfth transistor T12 is connected to the first node N1, the control end of the twelfth transistor T12 is connected to the first end of the fifth transistor T5, and the second end of the twelfth transistor T12 receives the second voltage signal VSS. The first end of the thirteenth transistor T13 is connected to the first output node No1, the control end of the thirteenth transistor T13 is connected to the first end of the fifth transistor T5, and the second end of the thirteenth transistor T13 receives the second voltage signal VSS.
[0048] As Figure 7As shown, in the first non-operating interval P1-1, the serial input signal Out[n-4] is at a high level, causing the ninth transistor T9 to conduct. The seventh transistor T7 and the eighth transistor T8 conduct in response to the first voltage signal VH being at a high level, causing the twelfth transistor T12 and the thirteenth transistor T13 to conduct and pull the first output node No1 to a low level. That is to say, in the first non-operating interval P1-1, the first anti-noise circuit 122 can be turned on to discharge the gate drive sequence signal Out[n] of the first output node No1 to a low potential, so as to ensure that the gate line remains closed and keep the internal voltage of the liquid crystal at the correct value. In addition, in response to the first output node No1 being at a low level, the tenth transistor T10 and the eleventh transistor T11 are turned off.
[0049] In the first operating period P1-2, the serial input signal Out[n-4] is at a low level, causing the ninth transistor T9 to turn off. Although the seventh transistor T7 and the eighth transistor T8 conduct in response to the first voltage signal VH being at a high level, since the first output node No1 is at a high level, the tenth transistor T10 and the eleventh transistor T11 will conduct, causing the control terminals of the twelfth transistor T12 and the thirteenth transistor T13 to be pulled to a low level by the second voltage signal VSS and turn off. That is to say, in the first operating period P1-2, the first anti-noise circuit 122 can be turned off to avoid discharging the gate drive sequence signal Out[n] of the first output node No1 to a low potential.
[0050] In the third non-operating period P1-3, the input frequency signal CLK1 becomes low, causing the first anti-noise circuit 122 to turn on and the gate drive sequence signal Out[n] to become low.
[0051] Please refer to Figure 5 and Figure 6 , the light-emitting drive circuit 140 may include a fourteenth transistor T14, a fifteenth transistor T15 and a second capacitor C2. The first end of the fourteenth transistor T14 receives the simultaneous output signal S_Sig, the control terminal of the fourteenth transistor T14 is connected to the fifth node N5, and the second end of the fourteenth transistor T14 is connected to the second output node No2. The first end and the control terminal of the fifteenth transistor T15 receive the synchronous voltage signal Vst, and the second end of the fifteenth transistor T15 is connected to the fifth node N5. The second capacitor C2 is connected between the control terminal and the second end of the fourteenth transistor T14.
[0052] Please refer to Figure 6, the second anti-noise circuit 142 may include a sixteenth transistor T16 and a seventeenth transistor T17. A first end of the sixteenth transistor T16 is connected to a fifth node N5, a control end of the sixteenth transistor T16 is connected to a third node N3, and a second end of the sixteenth transistor T16 receives a second voltage signal VSS. A first end of the seventeenth transistor T17 is connected to a second output node No2, a control end of the seventeenth transistor T17 is connected to the third node N3, and a second end of the seventeenth transistor T17 receives the second voltage signal VSS.
[0053] As Figure 7 shown, during the entire gate driving period (i.e., including a first non-operating interval P1-1, a first operating interval P1-2, and a third non-operating interval P1-3), the synchronous voltage signal Vst and the simultaneous output signal S_Sig are at a low level, turning on the fifth transistor T5. Therefore, the third node N3 is at a high potential, turning on the sixteenth transistor T16 and the seventeenth transistor T17, and pulling the second output node No2 to a low level, which can resist noise interference.
[0054] In addition, in the second non-operating interval P2-1, the synchronous voltage signal Vst is at a high level and the simultaneous output signal S_Sig is at a low level. Therefore, the fifteenth transistor T15 is turned on to pre-charge the second capacitor C2. In the anti-noise startup circuit, since the synchronous voltage signal Vst is at a high level, the fourth transistor T4 is turned on to pull the second node N2 to a low level, turning off the fifth transistor T5. At this time, the sixth transistor T6 is turned on in response to the high-level synchronous voltage signal Vst. Therefore, the fifth transistor T5 serves as an anti-noise isolation component, enabling the gate driving sub-circuit 120 to resist noise through the first anti-noise circuit 122 throughout the second non-operating interval P2-1 without affecting the operation of the light-emitting driving circuit 140.
[0055] In the second operating interval P2-2, the synchronous voltage signal Vst and the simultaneous output signal S_Sig are at a high level. The second output node No2 generates a high-level synchronous light-emitting signal Sn in response to the simultaneous output signal S_Sig, and the second capacitor C2 couples the fifth node N5 to a higher voltage, enabling the fourteenth transistor T14 to turn on more completely.
[0056] In the fourth non-operating interval P2-3, both the synchronous voltage signal Vst and the simultaneous output signal S_Sig become low levels. Therefore, the first anti-noise circuit 122 returns to an on state similar to that in the third non-operating period P1-3, and the second anti-noise circuit 142 returns to an on state similar to that during the entire gate driving period P1, enabling the synchronous light-emitting signal Sn to resist noise, which will not be elaborated here.
[0057] Please refer to Figure 8 、 9, Figure 8 、 9 are respectively the simulation waveform results of the gate drive sequence signal Out[n] and the synchronous light emission signal Sn of the gate drive circuit according to the embodiments of the present invention at levels 10, 100, 150, 180 and at normal temperature (25°C), high temperature (85°C), and low temperature (-40°C).
[0058] It should be noted that the simulation is carried out with the first voltage signal VH being a DC 20V, the second voltage signal VSS being a DC -5V, the control unit providing input frequency signals CLK1 to CLK8, and an AC signal (AC) with a high voltage of 20V and a low voltage of -5V to simulate and calculate the gate drive sequence signal Out[n] and the synchronous light emission signal Sn. Among them, the rise time (Tr, rising time) is defined as the time required for the voltage change from 10% to 90% during the process of charging from -5V to 20V; the fall time (Tf, falling time) is defined as the time required for the voltage change from 90% to 10% during the process of discharging from 20V to -5V.
[0059] It can be seen from the simulation results that the gate drive sequence signal Out[n] and the synchronous light emission signal Sn of the gate drive circuit according to the embodiments of the present invention can achieve good anti-interference effects at levels 10, 100, 150, 180 and at normal temperature (25°C), high temperature (85°C), and low temperature (-40°C).
[0060] [Advantages of the Embodiment]
[0061] One of the advantages of the present invention is that the gate drive circuit with anti-noise and light emission drive functions provided by the present invention can reduce the manufacturing cost and improve the yield of integrated circuits through the technical solution of integrating the gate drive block and the light emission drive block, and can further achieve the effect of a narrow border.
[0062] In addition, for the gate drive circuit with anti-noise and light emission drive functions provided by the present invention, through the configuration of the anti-noise startup circuit, the first anti-noise circuit and the second anti-noise circuit, when the gate drive block is in session, the light emission drive block can be anti-noise all the time, and when the light emission drive block is in session, the gate drive block can be anti-noise all the time.
[0063] The content disclosed above is only the preferred feasible embodiment of the present invention, and does not limit the protection scope of the claims of the present invention. Therefore, all equivalent technical changes made by using the content of the specification and drawings of the present invention are included in the protection scope of the claims of the present invention.
Claims
1. A gate drive circuit with anti-noise and light-emitting driving functions, characterized in that: The gate drive circuit with anti-noise and light-emitting drive functions comprises: An anti-noise startup circuit receives a synchronous voltage signal and provides a first anti-noise startup signal that acts in a first non-operating interval during at least a sequence driving period, and a second anti-noise startup signal that acts in a second non-operating interval during at least a light-emitting period; A gate driver block, comprising: a gate driving sub-circuit receiving a serial input signal and an input frequency signal and charging a first output node to generate a gate driving sequence signal in a first working interval during the sequence driving period; and a first anti-noise circuit connected to the first output node and receiving the first anti-noise start signal to maintain the first output node at a low level at least in the first non-operating interval; A light-emitting driving block, comprising: a light-emitting driving circuit, receiving a simultaneous output signal and the synchronous voltage signal and charging a second output node in a second working interval of the light-emitting period to generate a synchronous light-emitting signal; and A second anti-noise circuit is connected to the second output node, receives the second anti-noise start signal and maintains the voltage of the second output node at a low level at least in the second non-operating interval.
2. The gate driving circuit with anti-noise and light-emitting driving functions according to claim 1, characterized in that: The gate drive subcircuit comprises: a first transistor, wherein a first terminal and a control terminal of the first transistor receive the serial input signal, and a second terminal of the first transistor is connected to a first node; a second transistor, wherein a first terminal of the second transistor receives the input frequency signal, a control terminal of the second transistor is connected to the first node, and a third terminal of the second transistor is connected to the first output node; and A first capacitor is connected between the control terminal and the second terminal of the second transistor.
3. The gate driving circuit with anti-noise and light-emitting driving functions according to claim 2, characterized in that: In the first non-operating interval, the serial input signal is at a high level so that the first node is charged to a high potential, and the input frequency signal is at a low level so that the first output node is at a low level; Among them, in the first working interval, the serial input signal is at a low level, and the input frequency signal is at a high level, so that the first output node is charged to a high potential, and the level of the first node is increased through the first capacitor coupling.
4. The gate driving circuit with anti-noise and light-emitting driving functions according to claim 2, characterized in that: The anti-noise startup circuit comprises: a third transistor, wherein a first terminal of the third transistor and a control terminal of the third transistor receive a first voltage signal, and a second terminal of the third transistor is connected to a second node; a fourth transistor, wherein a first terminal of the fourth transistor is connected to the second node, a control terminal of the fourth transistor receives the synchronization voltage signal, and a second terminal of the fourth transistor receives a second voltage signal; a fifth transistor, wherein a first terminal of the fifth transistor is connected to the first anti-noise circuit, a control terminal of the fifth transistor is connected to the second node, and a second terminal of the fifth transistor is connected to the second anti-noise circuit via a third node; and A sixth transistor, wherein a first terminal of the sixth transistor is connected to the third node, a control terminal of the sixth transistor receives the synchronous voltage signal, and a second terminal of the sixth transistor receives the second voltage signal.
5. The gate driving circuit with anti-noise and light-emitting driving functions according to claim 4, characterized in that: The first voltage signals are all high level, the second voltage signals are all low level, in the first non-working interval, the synchronization voltage signal is low level, the third transistor is turned on, the fourth transistor and the sixth transistor are turned off, the second node is high level to turn on the fifth transistor, so as to serve as the first anti-noise start signal to enable the first anti-noise circuit to discharge the first output node to a low potential.
6. The gate driving circuit with anti-noise and light-emitting driving functions according to claim 4, characterized in that: The first anti-noise circuit comprises: a seventh transistor, a first terminal of the seventh transistor and a control terminal of the seventh transistor receiving the first voltage signal, and a second terminal of the seventh transistor connected to a fourth node; an eighth transistor, a first terminal of the eighth transistor receiving the first voltage signal, a control terminal of the eighth transistor connected to the fourth node, and a second terminal of the eighth transistor connected to the first terminal of the fifth transistor; a ninth transistor, wherein a first terminal of the ninth transistor is connected to the fourth node, a control terminal of the ninth transistor receives the serial input signal, and a second terminal of the ninth transistor receives the second voltage signal; a tenth transistor, wherein a first terminal of the tenth transistor is connected to the fourth node, a control terminal of the tenth transistor is connected to the first output node, and a second terminal of the tenth transistor receives the second voltage signal; an eleventh transistor, a first end of the eleventh transistor being connected to the second end of the eighth transistor, a control end of the eleventh transistor being connected to the first output node, and a second end of the eleventh transistor receiving the second voltage signal; a twelfth transistor, wherein a first terminal of the twelfth transistor is connected to the first node, a control terminal of the twelfth transistor is connected to the first terminal of the fifth transistor, and a second terminal of the twelfth transistor receives the second voltage signal; and A thirteenth transistor, wherein a first end of the thirteenth transistor is connected to the first output node, a control end of the thirteenth transistor is connected to the first end of the fifth transistor, and a second end of the thirteenth transistor receives the second voltage signal.
7. The gate driving circuit with anti-noise and light-emitting driving functions according to claim 6, characterized in that: In the first non-working interval, the serial input signal is at a high level, so that the ninth transistor is turned on, the seventh transistor and the eighth transistor are turned on in response to the first voltage signal, so that the twelfth transistor and the thirteenth transistor are turned on to pull the first output node to a low level, and in response to the first output node being at a low level, the tenth transistor and the eleventh transistor are turned off.
8. The gate driving circuit with anti-noise and light-emitting driving functions according to claim 6, characterized in that: The light-emitting driving circuit comprises: a fourteenth transistor, a first terminal of the fourteenth transistor receiving the simultaneous output signal, a control terminal of the fourteenth transistor connected to a fifth node, and a second terminal of the fourteenth transistor connected to the second output node; a fifteenth transistor, a first terminal and a control terminal of the fifteenth transistor receiving the synchronous voltage signal, and a second terminal of the fifteenth transistor connected to the fifth node; and A second capacitor is connected between the control terminal of the fourteenth transistor and the second terminal of the fourteenth transistor.
9. The gate driving circuit with anti-noise and light-emitting driving functions according to claim 8, characterized in that: In the second non-operating interval, the synchronization voltage signal is at a high level, the simultaneous output signal is at a low level, the second capacitor is precharged, the fifth transistor is turned off, and the fourth transistor and the sixth transistor are turned on, and the second output node is maintained at a low level; In the second working interval, the synchronous voltage signal and the simultaneous output signal are at a high level, the second output node is pulled to a high level in response to the simultaneous output signal, and the level of the fifth node is increased through the second capacitor coupling.
10. The gate driving circuit with anti-noise and light-emitting driving functions according to claim 8, characterized in that: The second anti-noise circuit comprises: a sixteenth transistor, wherein a first terminal of the sixteenth transistor is connected to the fifth node, a control terminal of the sixteenth transistor is connected to the third node, and a second terminal of the sixteenth transistor receives the second voltage signal; a seventeenth transistor, wherein a first terminal of the seventeenth transistor is connected to the second output node, a control terminal of the seventeenth transistor is connected to the third node, and a second terminal of the seventeenth transistor receives the second voltage signal; In the first non-operating interval, the sixteenth transistor and the seventeenth transistor are turned on to pull the second output node to a low potential.