Low noise amplifier

Abstract

The utility model relates to a low noise amplifier. The low-noise amplifier comprises a signal input end, a signal output end, a first bias providing circuit, a second bias providing circuit, a third bias providing circuit, a first-stage amplifying circuit and a second-stage amplifying circuit, wherein the first-stage amplifying circuit and the second-stage amplifying circuit are sequentially connected between the signal input end and the signal output end; the first bias providing circuit is configured to provide a first stable voltage so as to provide a first laminated bias voltage for the first-stage amplification circuit and the second-stage amplification circuit respectively; the second bias providing circuit is configured to provide a third bias voltage so as to provide a second laminated bias voltage for the first-stage amplification circuit; the third bias providing circuit is configured to provide a fourth bias voltage to provide a second stack bias voltage to the second stage amplifier circuit. The low-noise amplifier is high in gain, low in noise coefficient and high in stability.

Description

Technical Field

[0001] This application relates to the field of electronic technologies, and particularly to a low-noise amplifier. Background Art

[0002] Currently, many modern electronic systems include radio frequency transceiver devices, such as personal computers, tablet computers, wireless network components, televisions, cable television system "set-top boxes", radar systems, and cellular phones, which are capable of transmitting and receiving on multiple frequency bands. A radio frequency transceiver device typically includes a Low Noise Amplifier (LNA) for amplifying the signal received by an antenna. The gain and stability of the low-noise amplifier are key indicators affecting its performance.

[0003] Therefore, high gain and stability of the low-noise amplifier are crucial. Summary of the Utility Model

[0004] In view of this, embodiments of this application provide a low-noise amplifier to solve at least one problem in the background art.

[0005] Embodiments of this application provide a low-noise amplifier, which includes a signal input terminal, a signal output terminal, a first bias providing circuit, a second bias providing circuit, a third bias providing circuit, and a first-stage amplification circuit and a second-stage amplification circuit sequentially connected between the signal input terminal and the signal output terminal;

[0006] The first bias providing circuit is configured to provide a first stable voltage to provide a first stacked bias voltage to the first-stage amplification circuit and the second-stage amplification circuit respectively;

[0007] The second bias providing circuit is configured to provide a third bias voltage to provide a second stacked bias voltage to the first-stage amplification circuit;

[0008] The third bias providing circuit is configured to provide a fourth bias voltage to provide a second stacked bias voltage to the second-stage amplification circuit.

[0009] In an alternative embodiment, the first bias providing circuit includes a second resistor and a fifth transistor;

[0010] The first end of the second resistor is respectively connected to the gate and the drain of the fifth transistor, the second end of the second resistor is connected to the power supply terminal and is configured to provide the first stable voltage, and the source of the fifth transistor is connected to the ground terminal.

[0011] In an alternative embodiment, the low-noise amplifier further includes a voltage conversion circuit;

[0012] The voltage conversion circuit is configured to convert the first stable voltage into a first bias voltage to provide a first stacked bias voltage for the first-stage amplification circuit; and convert the first stable voltage into a second bias voltage to provide a first stacked bias voltage for the second-stage amplification circuit.

[0013] In an alternative embodiment, the voltage conversion circuit includes a third resistor, a fourth resistor, and a fifth resistor;

[0014] The first ends of the third resistor, the fourth resistor, and the fifth resistor are respectively configured to receive the first stable voltage, the second end of the fourth resistor is configured to provide the first bias voltage, the second end of the fifth resistor is configured to provide the second bias voltage, and the second end of the third resistor is connected to the power supply terminal.

[0015] In an alternative embodiment, the second bias providing circuit includes a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a sixteenth resistor, a sixth transistor, a seventh transistor, and an eighth transistor;

[0016] The first end of the sixth resistor is configured to receive an external voltage, the second end of the sixth resistor is respectively connected to the first end of the seventh resistor and the gate of the sixth transistor, the second end of the seventh resistor is respectively connected to the drain of the seventh transistor and the gate of the eighth transistor, the source of the sixth transistor is respectively connected to the gate of the seventh transistor and the first end of the eighth resistor, the drain of the sixth transistor is respectively connected to the first end of the ninth resistor and the drain of the eighth transistor, the second end of the ninth resistor is connected to the power supply terminal, the source of the eighth transistor is respectively connected to the first end of the tenth resistor and the first end of the sixteenth resistor, the second end of the sixteenth resistor is configured to provide the third bias voltage, and the source of the seventh transistor, the second end of the eighth resistor, and the second end of the tenth resistor are connected to the ground terminal;

[0017] In an alternative embodiment, the third bias providing circuit includes an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a seventeenth resistor, a ninth transistor, a tenth transistor, and an eleventh transistor;

[0018] The first terminal of the eleventh resistor is configured to receive an external voltage. The second terminal of the eleventh resistor is connected to the first terminal of the twelfth resistor and the gate of the ninth transistor respectively. The second terminal of the twelfth resistor is connected to the drain of the tenth transistor and the gate of the eleventh transistor respectively. The source of the ninth transistor is connected to the gate of the tenth transistor and the first terminal of the thirteenth resistor respectively. The drain of the ninth transistor is connected to the first terminal of the fourteenth resistor and the drain of the eleventh transistor respectively. The second terminal of the fourteenth resistor is connected to the power supply terminal. The source of the eleventh transistor is connected to the first terminal of the fifteenth resistor and the first terminal of the seventeenth resistor respectively. The second terminal of the seventeenth resistor is configured to provide the fourth bias voltage. The source of the tenth transistor, the second terminal of the thirteenth resistor, and the second terminal of the fifteenth resistor are connected to the ground terminal.

[0019] In an alternative embodiment, the first-stage amplifier circuit includes a first transistor and a second transistor; and / or, the second-stage amplifier circuit includes a third transistor and a fourth transistor;

[0020] The gate of the first transistor is configured to receive the first bias voltage. The gate of the second transistor is configured to receive the third bias voltage. The source of the first transistor is connected to the drain of the second transistor and connected to the gate of the fourth transistor. The drain of the first transistor is connected to the power supply terminal. The source of the second transistor is connected to the ground terminal;

[0021] The gate of the third transistor is configured to receive the second bias voltage. The gate of the fourth transistor is configured to receive the fourth bias voltage. The source of the third transistor is connected to the drain of the fourth transistor. The drain of the third transistor is connected to the power supply terminal and the signal output terminal respectively. The source of the fourth transistor is connected to the ground terminal.

[0022] In an alternative embodiment, the low-noise amplifier further includes an inter-stage matching circuit;

[0023] The inter-stage matching circuit is connected between the first-stage amplifier circuit and the second-stage amplifier circuit, and is configured to achieve impedance matching between the first-stage amplifier circuit and the second-stage amplifier circuit;

[0024] and / or, the inter-stage matching circuit includes a second capacitor, a third capacitor, and a first resistor;

[0025] The first terminal of the second capacitor is connected to the drain of the second transistor. The second terminal of the second capacitor is connected to the gate of the fourth transistor and the first terminal of the third capacitor respectively. The second terminal of the third capacitor is connected to the first terminal of the first resistor. The second terminal of the first resistor is connected to the drain of the fourth transistor.

[0026] In an alternative embodiment, the low-noise amplifier further includes an input matching circuit;

[0027] The input matching circuit is connected between the signal input end and the first-stage amplification circuit and is configured to achieve input impedance matching;

[0028] And / or, the input matching circuit includes a first capacitor;

[0029] The first end of the first capacitor is connected to the signal input end, and the second end of the first capacitor is connected to the gate of the second transistor.

[0030] In an alternative embodiment, the low-noise amplifier further includes an output matching network;

[0031] The output matching network is configured to achieve output impedance matching;

[0032] And / or, the output matching network includes a fourth capacitor, a fifth capacitor, a sixth capacitor, a first diode, a second diode, a third diode, a fourth diode, a first inductor, and a second inductor;

[0033] The first end of the fifth capacitor is respectively connected to the output end of the second-stage amplification circuit, the first end of the fourth capacitor, and the first end of the second inductor. The second end of the fifth capacitor is respectively connected to the positive electrode of the first diode and the signal output end. The negative electrode of the first diode is connected to the negative electrode of the second diode. The positive electrode of the second diode and the second end of the fourth capacitor are respectively connected to the ground terminal. The first end of the first inductor is connected to the power input end of the first-stage amplification circuit. The second end of the first inductor, the second end of the second inductor, the first end of the sixth capacitor, and the positive electrode of the third diode are respectively connected to the power supply terminal. The negative electrode of the third diode and the negative electrode of the fourth diode are connected. The positive electrode of the fourth diode and the second end of the sixth capacitor are respectively connected to the ground terminal.

[0034] The beneficial effects brought by the technical solutions provided in the embodiments of the present application include: through the first-stage amplification circuit and the second-stage amplification circuit, the gain of the low-noise amplifier is increased, and the noise coefficient is reduced. And the first-stage amplification circuit can have a sufficiently high gain to suppress the noise of the subsequent stage. And through the first bias supply circuit, the second bias supply circuit, and the third bias supply circuit, the first stacked bias voltage and the second stacked bias voltage are respectively provided, improving the stability.

[0035] Additional aspects and advantages of the embodiments of the present application will be given in part in the following description, will become apparent in part from the following description, or will be understood through the practice of the embodiments of the present application. Description of the Drawings

[0036] The accompanying drawings described herein are used to provide a further understanding of the present application and form a part of the present application. Among them, the accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the accompanying drawings:

[0037] Figure 1 is a schematic diagram of the principle of Example 1 of the low-noise amplifier in the embodiments of the present application;

[0038] Figure 2 is a schematic diagram of the principle of Example 2 of the low-noise amplifier in the embodiments of the present application;

[0039] Figure 3 is a schematic diagram of the principle of Example 3 of the low-noise amplifier in the embodiments of the present application;

[0040] Figure 4 is a schematic circuit diagram of a specific example of the low-noise amplifier in the embodiments of the present application. Detailed implementation manners

[0041] To make the technical solutions and beneficial effects of the embodiments of the present application more obvious and understandable, the following is a clear and complete description by listing specific embodiments. Obviously, the listed embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used in the description of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0042] It should be noted that terms such as "first", "second", etc. may be used in this application to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element. When describing "first", it does not necessarily mean that "second" exists; and when discussing "second", it does not indicate that "first" necessarily exists in the present application. The singular forms of "a", "an", and "the" may also be intended to include the plural forms, unless the context clearly indicates otherwise. The term "comprising" is used to determine the existence of the included features, but does not exclude the existence or addition of one or more other features. The term "and / or" includes any and all combinations of the related listed items. The meaning of the term "plural" is two or more. The term "connection" means that there is a transmission of electrical signals or data between the connected end and the connected-to end, and can be understood as "electrical connection", "communication connection", etc. "Connection" can be a direct connection between two components, or an indirect connection established through other components, or a connection inside two components, or any other possible connection form.

[0043] An embodiment of the present application provides a low-noise amplifier. As Figure 1 shown, the low-noise amplifier 1000 includes a signal input terminal IN, a signal output terminal VOUT, a first bias providing circuit 30, a second bias providing circuit 40, a third bias providing circuit 90, and a first-stage amplification circuit 10 and a second-stage amplification circuit 20 that are sequentially connected between the signal input terminal IN and the signal output terminal VOUT;

[0044] The first bias providing circuit 30 is configured to provide a first stable voltage to provide a first stacked bias voltage to the first-stage amplification circuit 10 and the second-stage amplification circuit 20 respectively;

[0045] The second bias providing circuit 40 is configured to provide a third bias voltage to provide a second stacked bias voltage to the first-stage amplification circuit 10;

[0046] The third bias providing circuit 90 is configured to provide a fourth bias voltage to provide a second stacked bias voltage to the second-stage amplification circuit 20.

[0047] In the embodiment of the present application, the first-stage amplification circuit 10 and the second-stage amplification circuit 20 may be signal amplification circuits composed of stacked transistors. In some possible implementation manners, at least one of the first-stage amplification circuit 10 and the second-stage amplification circuit 20 may use a classic cascode structure or other deformed cascode structures to reduce noise and improve gain.

[0048] In the stacked transistors, there may be at least two groups of stacked transistors, and each group of transistors may have at least one transistor. The first stacked bias voltage may be the control terminal voltage of at least one group of transistors in at least two groups of transistors, and the second stacked bias voltage may be the control terminal voltage of other groups of transistors except the at least one group of transistors in at least two groups of transistors. In some possible implementation manners, the first stacked bias voltage may be greater than the second stacked bias voltage. The first stacked bias voltage may be provided to the gate of the transistor that requires a higher bias voltage in the stacked transistors of the cascode structure, and the second stacked bias voltage may be provided to the gate of the transistor that requires a lower bias voltage in the stacked transistors of the cascode structure. Higher and lower in the present application are relative values.

[0049] The signal is input through the signal input terminal IN of the low-noise amplifier 1000, and after being amplified by two stages of the first-stage amplification circuit 10 and the second-stage amplification circuit 20 in sequence, it is output through the signal output terminal VOUT, thereby realizing high-gain amplification of the signal.

[0050] In the embodiments of the present application, the first-stage amplification circuit and the second-stage amplification circuit are adopted to increase the gain of the low-noise amplifier and reduce the noise figure. Moreover, the first-stage amplification circuit can have a sufficiently high gain to suppress the noise of the subsequent stage. Additionally, through the first bias supply circuit, the second bias supply circuit, and the third bias supply circuit, the first stacked bias voltage and the second stacked bias voltage are respectively provided, improving the stability.

[0051] As a specific example, as Figure 4 shown, the first bias supply circuit 30 includes a second resistor R2 and a fifth transistor M5;

[0052] The first end of the second resistor R2 is respectively connected to the gate and the drain of the fifth transistor M5. The second end of the second resistor R2 is connected to the power supply terminal VDD and is configured to provide a first stable voltage. The source of the fifth transistor M5 is connected to the ground terminal GND.

[0053] In the present application, the transistor can be a PMOS transistor (P-type metal oxide semiconductor field effect transistor, abbreviated as PMOS transistor), an NMOS transistor (N-type metal oxide semiconductor field effect transistor, abbreviated as NMOS transistor), or a combination thereof. It can also include at least one or a combination of devices such as BJT (bipolar junction transistor), SCR (silicon controlled rectifier), GTO (gate turn-off thyristor), MOSFET (metal oxide semiconductor field effect transistor, abbreviated as MOS transistor), IGBT (insulated gate bipolar transistor), MCT (MOS controlled thyristor), and SIT (static induction transistor). "Connected to" in the present application means an indirect connection that can be established through other components. For example, "A is connected to B" means that A can be connected to B after passing through other components.

[0054] In the embodiments of the present application, the first stable voltage is provided by the second resistor R2 and the fifth transistor M5, improving the stability of the first stable voltage, thereby improving the stability of the first bias voltage and the second bias voltage.

[0055] In an alternative embodiment, as Figure 2 shown, the low-noise amplifier 1000 further includes a voltage conversion circuit 50;

[0056] The voltage conversion circuit 50 is configured to convert the first stable voltage into a first bias voltage to provide the first stacked bias voltage for the first-stage amplification circuit 10; and convert the first stable voltage into a second bias voltage to provide the first stacked bias voltage for the second-stage amplification circuit 20.

[0057] In the embodiments of the present application, the voltage conversion circuit 50 can be set according to actual requirements. For example, it can be a resistor network. The first bias voltage can be supplied to the gate of the transistor that requires a relatively high bias voltage among the stacked transistors of the first-stage amplifier circuit 10. The second bias voltage can be supplied to the gate of the transistor that requires a relatively high bias voltage among the stacked transistors of the second-stage amplifier circuit 20. Through the voltage conversion circuit, the first stable voltage can reach the normal operating ranges of subsequent different amplifier circuits respectively, ensuring the realization of circuit performance.

[0058] As a specific example, as Figure 4 shown, the voltage conversion circuit 50 includes a third resistor R3, a fourth resistor R4, and a fifth resistor R5;

[0059] The first ends of the third resistor R3, the fourth resistor R4, and the fifth resistor R5 are respectively configured to receive the first stable voltage. The second end of the fourth resistor R4 is configured to provide the first bias voltage. The second end of the fifth resistor R5 is configured to provide the second bias voltage. The second end of the third resistor R3 is connected to the power supply terminal VDD.

[0060] In an alternative embodiment, as Figure 2 shown, the second bias providing circuit 40 is configured to generate a third bias voltage to provide a second stacked bias voltage to the first-stage amplifier circuit 10;

[0061] The third bias providing circuit 90 is configured to generate a fourth bias voltage to provide a second stacked bias voltage to the second-stage amplifier circuit 20.

[0062] In the embodiments of the present application, the circuit structures of the second bias providing circuit 40 and the third bias providing circuit 90 can be the same or different, and can be set according to actual requirements. The third bias voltage can be supplied to the gate of the transistor that requires a relatively low bias voltage among the stacked transistors of the first-stage amplifier circuit 10. The fourth bias voltage can be supplied to the gate of the transistor that requires a relatively low bias voltage among the stacked transistors of the second-stage amplifier circuit 20. By the second bias providing circuit 40 and the third bias providing circuit 90 respectively providing the third bias voltage and the fourth bias voltage, the normal operating ranges of subsequent different amplifier circuits can be reached respectively, ensuring the realization of circuit performance.

[0063] As a specific example, as Figure 4 shown, the second bias providing circuit 40 includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a sixteenth resistor R16, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8;

[0064] The first terminal of the sixth resistor R6 is configured to receive an external voltage VB1. The second terminal of the sixth resistor R6 is respectively connected to the first terminal of the seventh resistor R7 and the gate of the sixth transistor M6. The second terminal of the seventh resistor R7 is respectively connected to the drain of the seventh transistor M7 and the gate of the eighth transistor M8. The source of the sixth transistor M6 is respectively connected to the gate of the seventh transistor M7 and the first terminal of the eighth resistor R8. The drain of the sixth transistor M6 is respectively connected to the first terminal of the ninth resistor R9 and the drain of the eighth transistor M8. The second terminal of the ninth resistor R9 is connected to the power supply terminal VDD. The source of the eighth transistor M8 is respectively connected to the first terminal of the tenth resistor R10 and the first terminal of the sixteenth resistor R16. The second terminal of the sixteenth resistor R16 is configured to provide a third bias voltage. The source of the seventh transistor M7, the second terminal of the eighth resistor R8, and the second terminal of the tenth resistor R10 are connected to the ground terminal GND;

[0065] And / or, the third bias providing circuit includes an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a seventeenth resistor R17, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11;

[0066] The first terminal of the eleventh resistor R11 is configured to receive an external voltage VB1. The second terminal of the eleventh resistor R11 is respectively connected to the first terminal of the twelfth resistor R12 and the gate of the ninth transistor M9. The second terminal of the twelfth resistor R12 is respectively connected to the drain of the tenth transistor M10 and the gate of the eleventh transistor M11. The source of the ninth transistor M9 is respectively connected to the gate of the tenth transistor M10 and the first terminal of the thirteenth resistor R13. The drain of the ninth transistor M9 is respectively connected to the first terminal of the fourteenth resistor R14 and the drain of the eleventh transistor M11. The second terminal of the fourteenth resistor R14 is connected to the power supply terminal VDD. The source of the eleventh transistor M11 is respectively connected to the first terminal of the fifteenth resistor R15 and the first terminal of the seventeenth resistor R17. The second terminal of the seventeenth resistor R17 is configured to provide a fourth bias voltage. The source of the tenth transistor M10, the second terminal of the thirteenth resistor R13, and the second terminal of the fifteenth resistor R15 are connected to the ground terminal.

[0067] In the embodiment of the present application, the sixth transistor M6 can stabilize the drain voltage of the eighth transistor M8. The seventh transistor M7 can stabilize the gate voltage of the eighth transistor M8. And through the eighth transistor M8, it can be realized that it is not affected by the external voltage, and the stability of the third bias voltage is improved.

[0068] The ninth transistor M9 can stabilize the drain voltage of the eleventh transistor M11, the tenth transistor M10 can stabilize the gate voltage of the eleventh transistor M11, and through the eleventh transistor M11, it is possible to achieve immunity to external voltages, improving the stability of the fourth bias voltage.

[0069] As a specific example, the first-stage amplifier circuit 10 includes a first transistor M1 and a second transistor M2; and / or, the second-stage amplifier circuit 20 includes a third transistor M3 and a fourth transistor M4;

[0070] The gate of the first transistor M1 is configured to receive a first bias voltage, the gate of the second transistor M2 is configured to receive a third bias voltage, the source of the first transistor M1 is connected to the drain of the second transistor M2 and connected to the gate of the fourth transistor M4, the drain of the first transistor M1 is connected to the power supply terminal VDD, and the source of the second transistor M2 is connected to the ground terminal GND;

[0071] The gate of the third transistor M3 is configured to receive a second bias voltage, the gate of the fourth transistor M4 is configured to receive a fourth bias voltage, the source of the third transistor M3 is connected to the drain of the fourth transistor M4, the drain of the third transistor M3 is respectively connected to the power supply terminal VDD and the signal output terminal VOUT, and the source of the fourth transistor M4 is connected to the ground terminal GND.

[0072] In the embodiments of the present application, the third transistor M3 and the fourth transistor M4 form a two-layer stacked cascode structure, improving the gain of the low-noise amplifier and reducing the noise figure. The cascode structure of the embodiments of the present application is not limited to this, and it can also be a stack of three layers or more.

[0073] In an alternative embodiment, as Figure 3 shown, the low-noise amplifier 1000 further includes an inter-stage matching circuit 60;

[0074] The inter-stage matching circuit 60 is connected between the first-stage amplifier circuit 10 and the second-stage amplifier circuit 20, and is configured to achieve impedance matching between the first-stage amplifier circuit 10 and the second-stage amplifier circuit 20. By increasing the isolation between the input stage (the first stage) and the output stage (the second stage), the stability is improved.

[0075] As a specific example, as Figure 4 shown, the inter-stage matching circuit 60 includes a second capacitor C2, a third capacitor C3, and a first resistor R1;

[0076] The first end of the second capacitor C2 is connected to the drain of the second transistor M2, the second end of the second capacitor C2 is respectively connected to the gate of the fourth transistor M4 and the first end of the third capacitor C3, the second end of the third capacitor C3 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the drain of the fourth transistor M4.

[0077] In an alternative embodiment, the low-noise amplifier 1000 further includes an input matching circuit 70;

[0078] The input matching circuit 70 is connected between the signal input terminal IN and the first-stage amplifier circuit 10, and is configured to achieve input impedance matching.

[0079] As a specific example, as Figure 4 shown, the input matching circuit 70 includes a first capacitor C1;

[0080] The first end of the first capacitor C1 is connected to the signal input terminal IN, and the second end of the first capacitor C1 is connected to the gate of the second transistor M2.

[0081] In an alternative embodiment, the low-noise amplifier 1000 further includes an output matching network 80;

[0082] The output matching network 80 is configured to achieve output impedance matching.

[0083] In the embodiments of the present application, impedance matching is performed through the inter-stage matching circuit, the input matching circuit, and the output matching network, improving the signal transmission quality.

[0084] As a specific example, as Figure 4 shown, the output matching network 80 includes a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a first inductor L1, and a second inductor L2;

[0085] The first end of the fifth capacitor C5 is respectively connected to the output terminal of the second-stage amplifier circuit 20, the first end of the fourth capacitor C4, and the first end of the second inductor L2. The second end of the fifth capacitor C5 is respectively connected to the positive electrode of the first diode D1 and the signal output terminal VOUT. The negative electrode of the first diode D1 is connected to the negative electrode of the second diode D2. The positive electrode of the second diode D2 and the second end of the fourth capacitor C4 are respectively connected to the ground terminal GND. The first end of the first inductor L1 is connected to the power input terminal of the first-stage amplifier circuit 10. The second end of the first inductor L1, the second end of the second inductor L2, the first end of the sixth capacitor C6, and the positive electrode of the third diode D3 are respectively connected to the power supply terminal VDD. The negative electrode of the third diode D3 is connected to the negative electrode of the fourth diode D4. The positive electrode of the fourth diode D4 and the second end of the sixth capacitor C6 are respectively connected to the ground terminal GND.

[0086] In the embodiments of the present application, the power input terminal of the first-stage amplifier circuit 10 may be the drain of the first transistor M1, and the output terminal of the second-stage amplifier circuit 20 may be the drain of the third transistor M3. The first diode D1 and the second diode D2 with their negative electrodes connected, and the third diode D3 and the fourth diode D4 with their negative electrodes connected can play the role of preventing reverse current and limiting voltage, thereby improving the circuit safety.

[0087] It should be understood that the above embodiments are all exemplary and do not cover all possible implementation manners included in the claims. Without departing from the scope of the present disclosure, various deformations and changes can be made based on the above embodiments. Similarly, any combination of the technical features of the above embodiments can be made to form additional embodiments of the present application that may not be explicitly described. Therefore, the above embodiments only represent several implementation manners of the present application and do not limit the protection scope of the patent of the present application.

Claims

1. A low noise amplifier, characterized in that: The low noise amplifier comprises a signal input terminal, a signal output terminal, a first bias providing circuit, a second bias providing circuit, a third bias providing circuit, and a first stage amplifying circuit and a second stage amplifying circuit sequentially connected between the signal input terminal and the signal output terminal; The first bias providing circuit is configured to provide a first stable voltage to provide a first stacked bias voltage to the first stage amplifying circuit and the second stage amplifying circuit respectively; The second bias providing circuit is configured to provide a third bias voltage to provide a second stacked bias voltage to the first stage amplifier circuit; The third bias providing circuit is configured to provide a fourth bias voltage to provide a second stack bias voltage to the second stage amplifying circuit.

2. The low noise amplifier according to claim 1, characterized in that: The first bias providing circuit includes a second resistor and a fifth transistor; The first end of the second resistor is connected to the gate of the fifth transistor and the drain of the fifth transistor respectively, the second end of the second resistor is connected to the power supply terminal and is configured to provide the first stable voltage, and the source of the fifth transistor is connected to the ground terminal.

3. The low noise amplifier according to claim 2, characterized in that: The low noise amplifier also includes a voltage conversion circuit; The voltage conversion circuit is configured to convert the first stable voltage into a first bias voltage to provide a first stacked bias voltage to the first stage amplifier circuit; and convert the first stable voltage into a second bias voltage to provide a first stacked bias voltage to the second stage amplifier circuit.

4. The low noise amplifier according to claim 3, characterized in that: The voltage conversion circuit includes a third resistor, a fourth resistor and a fifth resistor; The first end of the third resistor, the first end of the fourth resistor and the first end of the fifth resistor are respectively configured to receive the first stable voltage, the second end of the fourth resistor is configured to provide the first bias voltage, the second end of the fifth resistor is configured to provide the second bias voltage, and the second end of the third resistor is connected to the power supply terminal.

5. The low noise amplifier according to claim 4, characterized in that: The second bias providing circuit includes a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a sixteenth resistor, a sixth transistor, a seventh transistor and an eighth transistor; The first end of the sixth resistor is configured to receive an external voltage, the second end of the sixth resistor is respectively connected to the first end of the seventh resistor and the gate of the sixth transistor, the second end of the seventh resistor is respectively connected to the drain of the seventh transistor and the gate of the eighth transistor, the source of the sixth transistor is respectively connected to the gate of the seventh transistor and the first end of the eighth resistor, the drain of the sixth transistor is respectively connected to the first end of the ninth resistor and the drain of the eighth transistor, the second end of the ninth resistor is connected to the power supply terminal, the source of the eighth transistor is respectively connected to the first end of the tenth resistor and the first end of the sixteenth resistor, the second end of the sixteenth resistor is configured to provide the third bias voltage, and the source of the seventh transistor, the second end of the eighth resistor and the second end of the tenth resistor are connected to the ground terminal.

6. The low noise amplifier according to claim 5, characterized in that: The third bias providing circuit includes an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a seventeenth resistor, a ninth transistor, a tenth transistor and an eleventh transistor; The first end of the eleventh resistor is configured to receive an external voltage, the second end of the eleventh resistor is respectively connected to the first end of the twelfth resistor and the gate of the ninth transistor, the second end of the twelfth resistor is respectively connected to the drain of the tenth transistor and the gate of the eleventh transistor, the source of the ninth transistor is respectively connected to the gate of the tenth transistor and the first end of the thirteenth resistor, the drain of the ninth transistor is respectively connected to the first end of the fourteenth resistor and the drain of the eleventh transistor, the second end of the fourteenth resistor is connected to the power supply terminal, the source of the eleventh transistor is respectively connected to the first end of the fifteenth resistor and the first end of the seventeenth resistor, the second end of the seventeenth resistor is configured to provide the fourth bias voltage, and the source of the tenth transistor, the second end of the thirteenth resistor and the second end of the fifteenth resistor are connected to the ground terminal.

7. The low noise amplifier according to claim 6, characterized in that: The first-stage amplifier circuit includes a first transistor and a second transistor; and / or, the second-stage amplifier circuit includes a third transistor and a fourth transistor; The gate of the first transistor is configured to receive the first bias voltage, the gate of the second transistor is configured to receive the third bias voltage, the source of the first transistor is connected to the drain of the second transistor and to the gate of the fourth transistor, the drain of the first transistor is connected to the power supply terminal, and the source of the second transistor is connected to the ground terminal; The gate of the third transistor is configured to receive the second bias voltage, the gate of the fourth transistor is configured to receive the fourth bias voltage, the source of the third transistor is connected to the drain of the fourth transistor, the drain of the third transistor is respectively connected to the power supply terminal and the signal output terminal, and the source of the fourth transistor is connected to the ground terminal.

8. The low noise amplifier according to claim 7, characterized in that: The low noise amplifier also includes an inter-stage matching circuit; The inter-stage matching circuit is connected between the first-stage amplifying circuit and the second-stage amplifying circuit, and is configured to achieve impedance matching between the first-stage amplifying circuit and the second-stage amplifying circuit; And / or, the inter-stage matching circuit includes a second capacitor, a third capacitor and a first resistor; The first end of the second capacitor is connected to the drain of the second transistor, the second end of the second capacitor is respectively connected to the gate of the fourth transistor and the first end of the third capacitor, the second end of the third capacitor is connected to the first end of the first resistor, and the second end of the first resistor is connected to the drain of the fourth transistor.

9. The low noise amplifier according to claim 8, characterized in that: The low noise amplifier also includes an input matching circuit; The input matching circuit is connected between the signal input terminal and the first-stage amplification circuit and is configured to achieve input impedance matching; And / or, the input matching circuit includes a first capacitor; A first end of the first capacitor is connected to the signal input end, and a second end of the first capacitor is connected to the gate of the second transistor.

10. The low noise amplifier according to any one of claims 1 to 9, characterized in that: The low noise amplifier also includes an output matching network; The output matching network is configured to achieve output impedance matching; And / or, the output matching network includes a fourth capacitor, a fifth capacitor, a sixth capacitor, a first diode, a second diode, a third diode, a fourth diode, a first inductor and a second inductor; The first end of the fifth capacitor is respectively connected to the output end of the second-stage amplifier circuit, the first end of the fourth capacitor and the first end of the second inductor, the second end of the fifth capacitor is respectively connected to the positive electrode of the first diode and the signal output end, the negative electrode of the first diode is connected to the negative electrode of the second diode, and the positive electrode of the second diode and the second end of the fourth capacitor are respectively connected to the ground end; the first end of the first inductor is connected to the power input end of the first-stage amplifier circuit, the second end of the first inductor, the second end of the second inductor, the first end of the sixth capacitor and the positive electrode of the third diode are respectively connected to the power supply end, the negative electrode of the third diode is connected to the negative electrode of the fourth diode, and the positive electrode of the fourth diode and the second end of the sixth capacitor are respectively connected to the ground end.

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