Clock frequency detection circuit and image sensor chip

Abstract

The utility model discloses a clock frequency detection circuit and an image sensor chip. The clock frequency detection circuit comprises a clock signal processing module, a switched capacitor module, a conversion module and an output module. The clock signal processing module provides a switch control signal for the switched capacitor module according to a to-be-tested clock signal; the switched capacitor module carries out periodic charging and discharging according to the switch control signal so as to generate impedance corresponding to the frequency of the clock signal to be detected; the conversion module generates corresponding detection current according to the impedance; the output module outputs the detection current so as to calculate the frequency of the to-be-detected clock signal according to the detection current. According to the technical scheme, the frequency of the clock signal to be detected can be detected according to the impedance generated by the switched capacitor module and the detection current generated by the conversion module, and the detection mode is directly related to the frequency of the clock signal, so that accurate detection of the clock frequency of the input system is realized.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic circuits, in particular to a clock frequency detection circuit and an image sensor chip. Background Art

[0002] In the prior art, the input system clock of a chip is often provided by a crystal oscillator. As the input reference clock of the entire chip, its frequency determines the normality of each internal clock of the chip. Detecting whether the system clock frequency is within the designed value is crucial for monitoring whether the chip works properly. The chip input system in the prior art cannot determine whether its frequency meets the design requirements. Therefore, a circuit that can detect whether the input system clock frequency meets the design requirements is needed. Summary of the Utility Model

[0003] An embodiment of the utility model provides a clock frequency detection circuit and an image sensor chip to solve the above technical problems.

[0004] A first aspect of an embodiment of the utility model provides a clock frequency detection circuit, including: a clock signal processing module, a switched-capacitor module, a conversion module, and an output module;

[0005] One end of the clock signal processing module receives a clock signal to be measured, and the other end is connected to the signal input end of the switched-capacitor module to provide a switching control signal for the switched-capacitor module according to the clock signal to be measured;

[0006] The switched-capacitor module performs periodic charge and discharge according to the switching control signal to generate an impedance corresponding to the frequency of the clock signal to be measured;

[0007] One end of the conversion module is connected to the load connection end of the switched-capacitor module, and the other end is connected to one end of the output module to generate a corresponding detection current according to the impedance;

[0008] The output module outputs the detection current to calculate the frequency of the clock signal to be measured according to the detection current.

[0009] A second aspect of an embodiment of the utility model provides an image sensor chip, including: the clock frequency detection circuit described in the first aspect.

[0010] The technical effects of the embodiments of the present utility model are as follows: This technical solution can detect the frequency of the clock signal to be measured according to the impedance generated by the switched-capacitor module and the detection current generated by the conversion module. Since this detection method is directly related to the frequency of the clock signal, it has high precision; and the circuit structure of this clock frequency detection circuit is relatively simple, without a complex conversion process, reducing the complexity of implementation; in addition, this technical solution can adapt to clock signals with different frequency ranges, and can flexibly respond to different application scenarios by adjusting the parameters of circuit elements, realizing wide-range detection of the input system clock frequency of the image sensor chip, solving the problem that the prior art cannot determine whether the input clock frequency meets the design requirements, thereby ensuring the normal operation of the image sensor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments of the present utility model. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0012] Figure 1 is a schematic structural diagram of a clock frequency detection circuit provided by Embodiment 1 of the present utility model;

[0013] Figure 2 is a first schematic structural diagram of a switched-capacitor module in a clock frequency detection circuit provided by Embodiment 1 of the present utility model;

[0014] Figure 3 is Figure 2 the circuit diagram of the switched-capacitor module provided;

[0015] Figure 4 is a second schematic structural diagram of a switched-capacitor module in a clock frequency detection circuit provided by Embodiment 1 of the present utility model;

[0016] Figure 5 is Figure 4 the circuit diagram of the switched-capacitor module provided;

[0017] Figure 6 is a third schematic structural diagram of a switched-capacitor module in a clock frequency detection circuit provided by Embodiment 1 of the present utility model;

[0018] Figure 7 is a schematic structural diagram of a clock signal processing module in a clock frequency detection circuit provided by Embodiment 1 of the present utility model;

[0019] Figure 8It is the circuit diagram of a non-overlapping clock generation circuit in a clock signal processing module in a clock frequency detection circuit provided by Embodiment 1 of the present utility model;

[0020] Figure 9 It is the circuit diagram of a clock differential output circuit in a clock signal processing module in a clock frequency detection circuit provided by Embodiment 1 of the present utility model;

[0021] Figure 10 It is the waveform diagram of each signal in a clock signal processing module in a clock frequency detection circuit provided by Embodiment 1 of the present utility model;

[0022] Figure 11 It is the structural diagram of a conversion module in a clock frequency detection circuit provided by Embodiment 1 of the present utility model;

[0023] Figure 12 It is the circuit diagram of an output module in a clock frequency detection circuit provided by Embodiment 1 of the present utility model;

[0024] Figure 13 It is another circuit diagram of an output module in a clock frequency detection circuit provided by Embodiment 1 of the present utility model;

[0025] Figure 14 It is the circuit diagram of a clock frequency detection circuit provided by Embodiment 1 of the present utility model;

[0026] In the figure: 101, clock signal processing module; 102, switched capacitor module; 103, conversion module; 104, output module; 111, non-overlapping clock generation circuit; 112, clock differential output circuit; 121, first switch module; 122, second switch module; 123, capacitor module; 124, load module; 125, first TG gate; 126, second TG gate; 127, first capacitor; 128, first switching transistor; 129, second switching transistor; 130, second capacitor; 131, first switched capacitor unit; 132, second switched capacitor unit; 133, third switched capacitor unit; 134, switching circuit; 141, comparator; 142, fifth switch module; 143, current mirror unit; 144, current amplification unit; 1121, first clock differential output sub-circuit; 1122, second clock differential output sub-circuit. Detailed implementation manners

[0027] To make the above objects, features and advantages of the present utility model more obvious and understandable, the present utility model will be further described below with reference to the accompanying drawings and embodiments.

[0028] It should be noted that specific details are set forth in the following description to facilitate a full understanding of the present utility model. However, the present utility model can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the connotation of the present utility model. Therefore, the present utility model is not limited by the specific embodiments disclosed below.

[0029] Example 1

[0030] Embodiment 1 provides a clock frequency detection circuit, as Figure 1 shown, including: a clock signal processing module 101, a switched capacitor module 102, a conversion module 103, and an output module 104;

[0031] One end of the clock signal processing module 101 receives the clock signal to be measured, and the other end is connected to the signal input end of the switched capacitor module 102 to provide a switching control signal for the switched capacitor module 102 according to the clock signal to be measured;

[0032] The switched capacitor module 102 performs periodic charge and discharge according to the switching control signal to generate an impedance corresponding to the frequency of the clock signal to be measured;

[0033] One end of the conversion module 103 is connected to the load connection end of the switched capacitor module 102, and the other end is connected to one end of the output module 104 to generate a corresponding detection current according to the impedance;

[0034] The output module 104 outputs the detection current to calculate the frequency of the clock signal to be measured according to the detection current.

[0035] In Embodiment 1, the clock frequency detection circuit includes a clock signal processing module 101, a switched capacitor module 102, a conversion module 103, and an output module 104. Each module has a specific function, and the frequency of the clock signal to be measured is obtained through the collaborative work of the four modules. The functions of these modules are as follows:

[0036] The clock signal processing module 101 receives the clock signal to be measured, which is the target to be measured. The clock signal processing module 101 generates a switching control signal according to the input clock signal. The switching control signal is an electrical signal that controls the state of an electronic switch (such as a MOSFET switch, etc.), and determines whether the electronic switch is turned on or off within a specific time period to ensure that the capacitor can be normally charged and discharged, and can be used to control the charge and discharge process of the switched capacitor module 102.

[0037] The switched-capacitor module 102 performs periodic charging and discharging through a switch control signal, thereby generating an impedance corresponding to the frequency of the input clock signal. Specifically: Under the control of the switch control signal, the switched-capacitor module 102 performs charge and discharge operations of charges at fixed time intervals. By controlling the charge and discharge frequency and method, the switched-capacitor module 102 generates an impedance characteristic related to the frequency of the input clock signal. The working principle of the switched-capacitor module 102 is as follows: The switched-capacitor module 102 includes a switch module and a capacitor module. When the switch module switches to the charging path, the capacitor module obtains charges from the power supply or the input node. When the switch module switches to the discharging path, the capacitor module releases the charges to the load or other parts of the circuit. The frequency of the charge and discharge process is determined by the frequency of the switch control signal, which is usually synchronized with the input clock signal. At the same time, the capacitor module exhibits an equivalent impedance characteristic during the charge and discharge process, and this impedance is determined by the charge and discharge frequency and method of the capacitor module. Therefore, by adjusting the frequency of the switch control signal to regulate the charge and discharge frequency, the equivalent impedance of the capacitor can be changed. When the frequency of the control signal increases, the equivalent impedance of the capacitor decreases; when the frequency decreases, the equivalent impedance increases. By adjusting the frequency and duty cycle of the switch control signal, the equivalent impedance of the switched-capacitor module 102 has a certain relationship with the frequency of the input clock signal. This relationship can be used for frequency detection. For example, the equivalent impedance can be reflected by measuring the current or voltage output by the capacitor module, thereby inferring the frequency of the input clock signal.

[0038] The conversion module 103 converts the impedance generated by the switched-capacitor module 102 into a corresponding current signal. The conversion module 103 can be various forms of voltage-current conversion circuits. By sensing the impedance of the switched-capacitor module 102, a corresponding detection current is generated, and the magnitude of this current is proportional to the impedance.

[0039] The output module 104 outputs the detection current. The output module 104 can be a current mirror module, which can output a preset range of currents according to a preset ratio. Calculating the frequency of the clock signal to be measured based on the detection current means calculating the frequency of the input clock signal through calculation formula conversion and other methods according to the magnitude of the detection current. The calculation formula is the conversion relationship between current and frequency, which can be obtained based on the structure and working principle of the switched-capacitor module 102.

[0040] The technical effect of a clock frequency detection circuit provided by the first embodiment lies in that: according to the impedance generated by the switched-capacitor module and the detection current generated by the conversion module, this technical solution can accurately detect the frequency of the clock signal to be measured. Since this detection method is directly related to the frequency of the clock signal, it has high precision. Moreover, the structure of this clock frequency detection circuit is relatively simple and does not require a complex conversion process, reducing the implementation complexity. In addition, this technical solution can adapt to clock signals with different frequency ranges, and can flexibly respond to different application scenarios by adjusting the parameters of circuit elements, realizing the accurate detection of the input system clock frequency of the chip, solving the problem that the prior art cannot determine whether the input clock frequency meets the design requirements, thereby ensuring the normal operation of the chip.

[0041] In this embodiment, the switched-capacitor module 102 performs periodic charge and discharge according to the switch control signal. As an implementation manner of the switched-capacitor module 102, the switched-capacitor module 102 includes at least one switched-capacitor unit, and the switched-capacitor unit includes a first charge-discharge loop and a second charge-discharge loop; within one charge-discharge cycle, one of the first charge-discharge loop and the second charge-discharge loop is used to charge the conversion module 103 according to the switch control signal, and the other is used to discharge according to the switch control signal to generate an impedance corresponding to the frequency of the clock signal to be measured according to the charge-discharge cycle.

[0042] Among them, the working process of this implementation manner is as follows: after receiving the clock signal to be measured, the clock signal processing module 101 generates a switch control signal, and this switch control signal determines the switch states of the first charge-discharge loop and the second charge-discharge loop. Within one charge-discharge cycle, the switch control signal closes the switch of the first charge-discharge loop, and the capacitor module starts to charge, and the charging current is controlled by the conversion module 103. At the same time, the switch control signal closes the switch of the second charge-discharge loop, and the charge in the capacitor module discharges through a specific path, and the conversion module 103 records the current change during the discharge process. In the next charge-discharge cycle, the switch control signal switches states, and the functions of the first charge-discharge loop and the second charge-discharge loop are interchanged. The originally charged loop discharges, and the originally discharged loop charges. The charge-discharge cycle is determined by the frequency of the clock signal to be measured. Therefore, the charge-discharge cycle of the capacitor module is proportional to the frequency of the clock signal. The conversion module 103 converts the charge-discharge behavior of the capacitor module into a current signal, and by detecting the characteristics of the current signal, the impedance corresponding to the clock frequency can be calculated.

[0043] The technical effect of this embodiment is as follows: This embodiment can accurately convert the frequency of the clock signal to be measured into a current signal. Since the charge and discharge cycle is directly related to the clock signal frequency, high-precision frequency detection is ensured. Through the alternating operation of the first charge and discharge circuit and the second charge and discharge circuit, this alternating process ensures that the capacitor is always switched between charging and discharging, thereby generating a stable current signal. This embodiment can adapt to different ranges of clock signal frequencies by adjusting the generation method of the switch control signal and the capacitance value.

[0044] In this embodiment, there are various implementation manners for the circuit structure of the switched-capacitor module 102 that realizes the functions of the above embodiment, including but not limited to the following implementation manners:

[0045] 1. Dual-switch single-capacitor circuit: It consists of one capacitor and two switches. In one cycle, the two switches are alternately turned on and off, and the capacitor is charged and discharged within one cycle, generating an equivalent impedance proportional to the clock frequency.

[0046] 2. Dual-capacitor alternating charge and discharge circuit: It uses two capacitors and four switches. Every two switches control one capacitor, and within one cycle of the clock, the capacitors alternately perform charge and discharge operations.

[0047] 3. Differential switched-capacitor circuit: It consists of two switched-capacitor units that separately process positive and negative input signals. Each unit includes a pair of switches and one capacitor.

[0048] 4. Polyphase switched-capacitor circuit: It uses multiple clock signals with phase offsets to control multiple switched-capacitor units. By performing switch operations at different phases, more refined charge and discharge control can be achieved.

[0049] 5. Circuit with multiple switched-capacitor units connected in series or parallel: Multiple switched-capacitor units are connected in series or parallel, and the participation of each capacitor is controlled by a switch matrix. By switching the connection mode of the capacitors, the total capacitance value can be changed, thereby adjusting the equivalent impedance.

[0050] As an implementation manner of the structure of the switched-capacitor module 102, this embodiment is only an example and does not limit the structure of the switched-capacitor module 102. As Figure 2 shown, the switched-capacitor module 102 includes a first switch module 121, a second switch module 122, and a capacitor module 123. One end of the first switch module 121 is connected to the conversion module 103, the other end of the first switch module 121 is connected to the capacitor module 123 and the second switch module 122, the other end of the second switch module 122 is connected to the load module 124, and the other end of the capacitor is grounded.

[0051] The working process of this embodiment includes:

[0052] Charging stage: When the first switching module 121 is controlled to conduct and the second switching module 122 is controlled to turn off through a switching control signal, the conversion module 103, the first switching module 121, and the capacitor module 123 form a charging loop, and the conversion module 103 charges the capacitor module 123 until the capacitor module 123 is charged to the voltage provided by the conversion module 103.

[0053] Discharging stage: When the first switching module 121 is controlled to turn off and the second switching module 122 is controlled to conduct through a switching control signal, the capacitor module 123, the second switching module 122, and the load module 124 form a discharging loop, and the capacitor module 123 discharges the load module 124, and the charges in the capacitor module 123 are released to the load module 124.

[0054] The working principle of this embodiment is as follows: The first switching module 121 and the second switching module 122 are alternately turned on and off to control the charging and discharging processes of the capacitor module 123. The capacitor module 123 completes charging and discharging within one clock cycle, thereby generating the required current. The charging and discharging times can be controlled by adjusting the on-time of the switch, thereby changing the amount of charge transfer in the capacitor module 123, so that the switched-capacitor module 102 can adapt to different signal frequency requirements. The average current can be expressed as the amount of charge transfer within one clock cycle. As Figure 3 shown, it is the circuit diagram of this embodiment. The first switching module 121 is the switch K1, the second switching module 122 is the switch K2, and the capacitor module 123 is the capacitor C. The impedance of this circuit can be calculated by the following formula:

[0055]

[0056] R = Cf -1

[0057] where I is the average current, Q 1 is the amount of charge transfer between the conversion module 103 and the capacitor module 123 when the switch K1 is on within one charge-discharge cycle, Q 2 is the amount of charge transfer between the conversion module 103 and the capacitor module 123 when the switch K2 is on within one charge-discharge cycle, C is the capacitance value of the capacitor C, V A is the output terminal voltage of the conversion module 103, V B is the input terminal voltage of the load module, T 1 is the on-time of the switch K1 within one charge-discharge cycle, T2 is the on-time of the switch K2 within one charge-discharge cycle, R is the impedance, and f is the frequency of the clock signal.

[0058] As another embodiment of the structure of the switched-capacitor module 102, this embodiment is only an example and does not limit the structure of the switched-capacitor module 102. For example,Figure 4 As shown, the first charge and discharge circuit includes a first TG gate 125, a first switching transistor 128, and a first capacitor 127, and the second charge and discharge circuit includes a second TG gate 126, a second switching transistor 129, and a second capacitor 130;

[0059] One end of the first TG gate 125 and one end of the second TG gate 126 are commonly connected as the load connection end of the switched capacitor unit. The other end of the first TG gate 125 and the first end of the first capacitor 127 are respectively connected to one end of the first switching transistor 128. The second end of the first capacitor 127 and the other end of the first switching transistor 128 are commonly connected to ground. The other end of the second TG gate 126 and the first end of the second capacitor 130 are respectively connected to one end of the second switching transistor 129. The second end of the second capacitor 130 and the other end of the second switching transistor 129 are commonly connected to ground;

[0060] The first control terminal of the first TG gate 125, the second control terminal of the first TG gate 125, the first control terminal of the second TG gate 126, and the second control terminal of the second TG gate 126 are respectively connected to different switching control signals. Moreover, the second control terminal of the first TG gate 125 and the control terminal of the second switching transistor 129 are connected to the same switching control signal, and the first control terminal of the second TG gate 126 and the control terminal of the first switching transistor 128 are connected to the same switching control signal.

[0061] The working process of this embodiment is as follows:

[0062] First capacitor 127 charging and second capacitor 130 discharging stage: When the first TG gate 125 and the second switching transistor 129 are controlled to conduct through the switching control signal, and at the same time the second TG gate 126 and the first switching transistor 128 are controlled to turn off, the conversion module 103, the first TG gate 125, and the first capacitor 127 form a first charging circuit, and the conversion module 103 charges the first capacitor 127 until the first capacitor 127 is charged to the voltage provided by the conversion module 103; the second capacitor 130 and the second switching transistor 129 form a first discharging circuit, and the second capacitor 130 discharges through the second switching transistor 129.

[0063] First capacitor 127 discharging and second capacitor 130 charging stage: When the first TG gate 125 and the second switching transistor 129 are controlled to turn off through the switching control signal, and at the same time the second TG gate 126 and the first switching transistor 128 are controlled to conduct, the conversion module 103, the second TG gate 126, and the second capacitor 130 form a second charging circuit, and the conversion module 103 charges the second capacitor 130 until the second capacitor 130 is charged to the voltage provided by the conversion module 103; the first capacitor 127 and the first switching transistor 128 form a second discharging circuit, and the first capacitor 127 discharges through the first switching transistor 128.

[0064] As Figure 5As shown, it is the circuit diagram of this embodiment. The first TG gate 125 is gate TG1, the second TG gate 126 is gate TG2, the first switching transistor 128 is switching transistor M1, the second switching transistor 129 is switching transistor M2, the first capacitor 127 is capacitor C1, and the second capacitor 130 is capacitor C2. The working principle of this embodiment is as follows: During one clock cycle, the upper plates of capacitor C1 and capacitor C2 are respectively connected to the Vo node and the GND node. Therefore, the average current can be expressed as the amount of charge transfer during one clock cycle, and the following formula can be obtained:

[0065]

[0066] Among them, C is the capacitance value of capacitor C1 and capacitor C2, is the average current, f ck is the frequency of the clock signal, V 0 is the voltage of the Vo node. By setting the conversion module 103, the voltage of the Vo node can be clamped near the reference voltage. Therefore, the magnitude of the output current is linearly related to the frequency of the input signal. By calibrating the coefficient, the frequency of the input signal can be accurately calculated by measuring the output current.

[0067] It should be noted that the voltages of the upper plates of capacitor C1 and capacitor C2 need to be converted within the period. If their capacitance values are too large, the waveform inversion will be incomplete. Therefore, their values need to be determined according to the range of the detection clock. For an input clock frequency of 10 MHz to 100 MHz, it is better that the capacitance value is less than 500 fF.

[0068] As another embodiment of the structure of the switched-capacitor module 102, this embodiment is only for example and does not limit the structure of the switched-capacitor module 102. As Figure 6 shown, the switched-capacitor module 102 includes a first switched-capacitor unit 131, a second switched-capacitor unit 132, a third switched-capacitor unit 133, and a switching circuit 134;

[0069] The first end of the switching circuit 134 is respectively connected to one end of each switched-capacitor unit. The second end of the switching circuit 134 forms the load connection end of the switched-capacitor module 102. The control end of the switching circuit 134 is connected to the bit control signal to turn on or off at least one switched-capacitor unit according to the bit control signal;

[0070] The other ends of the first switched-capacitor unit 131, the second switched-capacitor unit 132, and the third switched-capacitor unit 133 are commonly connected to the ground.

[0071] Among them, the first switched-capacitor unit 131, the second switched-capacitor unit 132, and the third switched-capacitor unit 133 can have exactly the same structure. For example, if they are all 1 bit, then the number of bits in the conduction bit control signal bit_ctrl represents the number of bits. The first switched-capacitor unit 131, the second switched-capacitor unit 132, and the third switched-capacitor unit 133 can also be 1 bit, 2 bits, and 4 bits respectively. Then, when all are conducting, it is 7 bits, and so on. It should be noted that for the 2-bit switched-capacitor unit compared with the 1-bit switched-capacitor unit, the sizes of the internal capacitors and switching transistors should be correspondingly increased.

[0072] Specifically, each switched-capacitor unit can include a capacitor and a corresponding switching transistor. One end of the switching circuit 134 is connected to the load connection end of each switched-capacitor unit, and the control end receives the bit control signal bit_ctrl to control the conduction or cut-off of each switched-capacitor unit according to the signal. The bit control signal bit_ctrl is used to control the state of each switched-capacitor unit in the switching circuit 134. For example, the value of bit_ctrl can control the conduction of at least one switched-capacitor unit. If bit_ctrl is "011" (assuming three bits), it means that the second switched-capacitor unit 132 and the third switched-capacitor unit 133 are conducting, while the first switched-capacitor unit 131 is not conducting. Different switched-capacitor units can have different capacitance values. For example, the first switched-capacitor unit 131 is 1 bit, the second switched-capacitor unit 132 is 2 bits, and the third switched-capacitor unit 133 is 4 bits, which means that the capacitance and the size of the switching transistor of the second switched-capacitor unit 132 are twice that of the first switched-capacitor unit 131, and the third switched-capacitor unit 133 is four times that of the first switched-capacitor unit 131. According to the number of bits of bit to be conducted, different total capacitance values can be combined. For example, when all switched-capacitor units are conducting, the total capacitance is 7 bits, and when the first switched-capacitor unit 131 and the second switched-capacitor unit 132 are conducting, the total capacitance is 3 bits.

[0073] The technical effect of this embodiment is that this embodiment allows flexible adjustment of the capacitance value to match different application requirements. Through the bit control signal, fine control of the output capacitance value can be achieved, thereby precisely adjusting the system output characteristics. Different combinations of bit positions can expand the capacitance value range of the system to meet a wider range of application requirements.

[0074] For the switching control signal generated by the clock signal processing module 101, the switching control signal for controlling the charging and discharging process of the switched-capacitor module 102 can perform precise timing control to ensure that the capacitor is charged and discharged at the correct time. The clock signal processing module 101 that generates the switching control signal includes but is not limited to the following structures:

[0075] 1. Non-overlapping clock generation circuit:

[0076] Use logic gates (such as AND gates, OR gates, NOT gates, etc.) to generate non-overlapping clock signals, ensuring that multiple switches do not conduct simultaneously within one clock cycle, thereby avoiding short-circuit situations.

[0077] 2. Clock divider:

[0078] Use a divider to divide a high-frequency clock signal to the required lower frequency, generating an appropriate switching control signal frequency to control the charge and discharge cycles of the switched-capacitor module.

[0079] 3. Pulse-width modulation (PWM) circuit:

[0080] Use pulse-width modulation technology to generate a switching control signal by adjusting the width and period of the pulse, controlling the charging and discharging timing of the capacitor.

[0081] As an implementation manner of the structure of the clock signal processing module 101, this implementation manner is only an example and does not limit the structure of the clock signal processing module 101. For example, Figure 7 As shown, the clock signal processing module 101 includes a non-overlapping clock generation circuit 111 and a clock differential output circuit 112 that are connected to each other; the non-overlapping clock generation circuit 111 receives the clock signal to be measured to generate two non-overlapping clock signals; the clock differential output circuit 112 outputs a switching control signal to the switched-capacitor module 102 according to the two non-overlapping clock signals.

[0082] Among them, the non-overlapping clock generation circuit 111 receives the clock signal to be measured and converts it into two non-overlapping clock signals. The characteristic of the non-overlapping clock signals is that the two signals will not be in the high-level state simultaneously, thereby avoiding short-circuit problems in the circuit. Specifically, when the input clock signal to be measured enters the non-overlapping clock generation circuit 111, the circuit divides the clock signal into two phases, generating two complementary non-overlapping clock signals within each clock cycle, that is, when one clock signal is high, the other is low, and vice versa.

[0083] Among them, after the clock differential output circuit 112 receives the two non-overlapping clock signals from the non-overlapping clock generation circuit 111, the clock differential output circuit 112 processes these signals into the switching control signals required by the switched-capacitor module 102. This circuit ensures the stability and symmetry of the output signal, and can generate two sets of forward and reverse signals without delay, which can be used to control the conduction and closing of each switch in the switched-capacitor module 102, thereby precisely controlling the charge and discharge process of the capacitor.

[0084] The technical effect of this embodiment is that through the combination of a non-overlapping clock generation circuit and a clock differential output circuit, an accurate clock signal can be generated, which has high symmetry and stability and is suitable for high-precision signal processing applications. The design of the non-overlapping clock generation circuit ensures that the two clock signals will never be in the high-level state at the same time, thus avoiding the problem of circuit short-circuit that may be caused by clock signal overlap.

[0085] Among them, the non-overlapping clock generation circuit 111 in the clock signal processing module 101 is a circuit structure for generating two complementary clock signals without overlapping parts. The structure of the non-overlapping clock generation circuit 111 includes but is not limited to the following several types:

[0086] 1. Delay-chain non-overlapping clock generator:

[0087] A series of cascaded delay elements, such as inverters or buffers, are used to delay the input clock signal, and the delayed signal generates non-overlapping clocks through logic gates (such as NAND gates).

[0088] 2. RC-delay non-overlapping clock generator:

[0089] An RC network is used to introduce delay to generate non-overlapping clock signals. Usually, a delay network composed of resistors and capacitors is connected in front of an inverter or a NAND gate.

[0090] 3. Dual-latch non-overlapping clock generator:

[0091] Two latches are used. One latch receives the original clock signal and generates the first non-overlapping clock, and the other latch receives the first non-overlapping clock and generates the second non-overlapping clock.

[0092] 4. Logic-gate non-overlapping clock generator:

[0093] Using basic logic gates such as AND gates, OR gates, NAND gates, etc., non-overlapping clocks are generated through combinational logic. The input clock signal generates two non-overlapping clocks that are not high at the same time after passing through these logic gates.

[0094] As an implementation manner of the structure of the non-overlapping clock generation circuit 111, this implementation manner is only an example and does not limit the structure of the non-overlapping clock generation circuit 111. For example, Figure 8As shown, the non-overlapping clock generation circuit 111 includes a first buffer B1, a second buffer B2, a third buffer B3, a first NOT gate N1, a second NOT gate N2, a third NOT gate N3, a fourth NOT gate N4, a fifth NOT gate N5, a sixth NOT gate N6, a seventh NOT gate N7, a first NAND gate NA1, and a second NAND gate NA2; the input end of the first buffer B1 and the input end of the first NOT gate N1 are commonly connected and are connected to the clock signal to be measured clkin, the output end of the first buffer B1 is connected to the first input end of the first NAND gate NA1, the output end of the first NOT gate N1 is connected to the first input end of the second NAND gate NA2, the output end of the first NAND gate NA1 is connected to the input end of the second NOT gate N2, the output end of the second NOT gate N2 is connected to the input end of the third NOT gate N3, the output end of the third NOT gate N3 is respectively connected to the input end of the fourth NOT gate N4 and the second input end of the second NAND gate NA2, the output end of the fourth NOT gate N4 is connected to the input end of the second buffer B2, the output end of the second buffer B2 outputs the first clock signal ckn, the output end of the second NAND gate NA2 is connected to the input end of the fifth NOT gate N5, the output end of the fifth NOT gate N5 is connected to the input end of the sixth NOT gate N6, the output end of the sixth NOT gate N6 is respectively connected to the input end of the seventh NOT gate N7 and the second input end of the first NAND gate NA1, the output end of the seventh NOT gate N7 is connected to the input end of the third buffer B3, and the output end of the third buffer B3 outputs the second clock signal ckp.

[0095] The working process of this embodiment includes the following stages:

[0096] Clock signal input stage: The clock signal to be measured is input to the input ends of the first buffer B1 and the first NOT gate N1. The function of the first buffer B1 is to provide the driving ability of the signal to avoid the load impact of the subsequent circuit on the clock signal to be measured. Its output is connected to the first input end of the first NAND gate NA1. The first NOT gate N1 performs an inversion process on the input clock signal, and its output signal serves as the basis for signal processing in the next stage and is connected to the first input end of the second NAND gate NA2.

[0097] First clock signal generation stage: The function of the first NAND gate NA1 is to combine the clock signal output by the buffer and the inverted signal to start generating the first signal part of the non-overlapping clock. The series processing of the second NOT gate N2 and the third NOT gate N3 further delays the signal and generates an inverted signal. The processing of this part of the signal ensures the non-overlapping characteristics of the two clock signals. The output of the third NOT gate N3 is divided into two paths. One path outputs the first clock signal ckn through the fourth NOT gate N4 and the second buffer B2; the other path is connected to the second input end of the second NAND gate NA2 to further process and generate the second clock signal ckp.

[0098] Second clock signal generation stage: The output of the second NAND gate NA2 is processed by the fifth NOT gate N5 and the sixth NOT gate N6 to delay and invert the signal. The output signal of the sixth NOT gate N6 is inverted by the seventh NOT gate N7 and connected to the input terminal of the third buffer B3, and finally the second clock signal ckp is output.

[0099] In this embodiment, the signal waveforms of the first clock signal ckn and the second clock signal ckp generated after the clock signal to be measured clkin passes through the non-overlapping clock generation circuit 111 are as Figure 10 shown. The dotted line position indicates that the high levels of the first clock signal ckn and the second clock signal ckp do not overlap. Therefore, the technical effect of this embodiment is that through the combination of multiple NOT gates and NAND gates, the phase of the clock signal can be accurately controlled, so that the two generated clock signals have a strict non-overlapping characteristic, preventing the situation where the two clock signals are both at a high level at the same time and avoiding the short-circuit current problem in the circuit.

[0100] Among them, the clock differential output circuit 112 in the clock signal processing module 101 is used to generate two differential clock signals that are inverted with each other. The clock differential output circuit 112 includes but is not limited to the following structures:

[0101] 1. Direct differential amplifier structure:

[0102] Use a differential amplifier circuit to directly convert a single-ended clock signal into a differential clock signal, and the two outputs at both ends of the differential amplifier are inverted signals with each other.

[0103] 2. Transformer-coupled differential output:

[0104] Convert a single-ended signal into a differential signal through a transformer, and use the center tap of the transformer to provide a symmetric differential output.

[0105] 3. Logic gate to generate differential signal:

[0106] Use logic gates (such as NAND gates, inverters) to generate differential signals. The single-ended clock signal generates an inverted signal through an inverter, and then the original signal and the inverted signal are output as two parts of the differential signal together.

[0107] 4. Differential signal buffer structure:

[0108] Use a pair of matched differential signal buffers (such as differential pair amplifiers) to generate high-quality differential clock signals. The input single-ended clock signal outputs positive and negative signals respectively through the differential pair structure.

[0109] As an implementation manner of the structure of the clock differential output circuit 112, this implementation manner is only an example, and the structure of the clock differential output circuit 112 is not limited, such as Figure 9As shown, the clock differential output circuit 112 includes a first clock differential output sub - circuit 1121 and a second clock differential output sub - circuit 1122;

[0110] The first clock differential output sub - circuit 1121 includes a fourth buffer B4, a fifth buffer B5, an eighth NOT gate N8, a ninth NOT gate N9, and a tenth NOT gate N10. The input terminal of the fourth buffer B4 receives the first clock signal ckn. The output terminal of the fourth buffer B4 is respectively connected to the input terminal of the eighth NOT gate N8 and the input terminal of the fifth buffer B5. The output terminal of the eighth NOT gate N8 is connected to the input terminal of the ninth NOT gate N9. The output terminal of the ninth NOT gate N9 outputs a first switch control signal ckno. The output terminal of the fifth buffer B5 is connected to the input terminal of the tenth NOT gate N10. The output terminal of the tenth NOT gate N10 outputs a second switch control signal cknbo.

[0111] The second clock differential output sub - circuit 1122 includes a sixth buffer B6, a seventh buffer B7, an eleventh NOT gate N11, a twelfth NOT gate N12, and a thirteenth NOT gate N13. The input terminal of the sixth buffer B6 receives the second clock signal ckp. The output terminal of the sixth buffer B6 is respectively connected to the input terminal of the eleventh NOT gate N11 and the input terminal of the seventh buffer B7. The output terminal of the eleventh NOT gate N11 is connected to the input terminal of the twelfth NOT gate N12. The output terminal of the twelfth NOT gate N12 outputs a third switch control signal ckpo. The output terminal of the seventh buffer B7 is connected to the input terminal of the thirteenth NOT gate N13. The output terminal of the thirteenth NOT gate N13 outputs a fourth switch control signal ckpbo.

[0112] The working process of this embodiment is as follows:

[0113] The working process of the first clock differential output sub - circuit 1121: The fourth buffer B4 receives the first clock signal ckn. Its output terminal is connected to the input terminals of the eighth NOT gate N8 and the fifth buffer B5. The fourth buffer B4 provides signal driving ability and ensures signal integrity. The eighth NOT gate N8 inverts the output signal of the fourth buffer B4 to generate an inverted signal. The ninth NOT gate N9 further inverts the output signal of the eighth NOT gate N8 and outputs a first switch control signal ckno. The fifth buffer B5 directly buffers the first clock signal ckn and outputs it to the input terminal of the tenth NOT gate N10. The tenth NOT gate N10 inverts the output signal of the fifth buffer B5 to generate a second switch control signal cknbo.

[0114] Working process of the second clock differential output sub - circuit 1122: The sixth buffer B6 receives the second clock signal ckp, and its output terminal is connected to the input terminals of the eleventh NOT gate N11 and the seventh buffer B7. The sixth buffer B6 also provides signal driving ability and ensures signal integrity. The eleventh NOT gate N11 inverts the output signal of the sixth buffer B6 to generate an inverted signal. The twelfth NOT gate N12 further inverts the output signal of the eleventh NOT gate N11 to output the third switch control signal ckpo. The seventh buffer B7 directly buffers the second clock signal ckp and outputs it to the input terminal of the thirteenth NOT gate N13. The thirteenth NOT gate N13 inverts the output signal of the seventh buffer B7 to generate the fourth switch control signal ckpbo.

[0115] The waveforms of the first switch control signal ckno, the second switch control signal cknbo, the third switch control signal ckpo, and the fourth switch control signal ckpbo generated by the clock differential output circuit 112 are as Figure 10 shown. The technical effect of this embodiment is that through the combination of multiple - stage NOT gates and buffers, this circuit can generate differential signals with high symmetry. The design of multiple - stage inversion and buffering enhances the stability and reliability of the signals, reduces the influence caused by process deviations or environmental changes, and ensures the stable output of the circuit under various working conditions.

[0116] Among them, for the conversion module 103 in the first embodiment, the conversion module 103 is used to convert the impedance formed in the switched - capacitor module 102 into a corresponding current signal. The conversion module 103 includes but is not limited to the following structures:

[0117] 1. Comparator and switch module:

[0118] By combining a comparator and a switch module to provide a fixed voltage to the switched - capacitor module, the impedance can be converted into a current signal.

[0119] 2. Operational amplifier and resistor network:

[0120] By combining an operational amplifier (OP - AMP) with a resistor network, the impedance can be converted into a current signal. For example, the output current of the operational amplifier is controlled by a feedback resistor.

[0121] 3. Current converter:

[0122] The current converter includes various types, such as current sources, current pumps, etc., which convert the input impedance signal into a corresponding current.

[0123] As an implementation manner of the circuit structure of the conversion module 103, this implementation manner is only an example and does not limit the structure of the conversion module 103. For example, Figure 11As shown in the figure, the conversion module 103 includes a comparator 141 and a third switching transistor 142; a first input terminal of the comparator 141 receives a reference voltage, a second input terminal of the comparator 141 and one end of the third switching transistor 142 are commonly connected to form one end of the conversion module 103, an output terminal of the comparator 141 is connected to a control terminal of the third switching transistor 142, and the other end of the third switching transistor 142 forms the other end of the conversion module 103.

[0124] The working process of this embodiment is as follows:

[0125] A reference voltage V_ref is applied to the first input terminal of the comparator 141. The reference voltage can be a fixed voltage and is used to compare with the input signal V0. The comparator 141 compares the input signal V0 (the voltage at the load connection terminal of the switched-capacitor module 102) with the reference voltage V_ref in real time. When the input signal voltage is higher than the reference voltage, the comparator 141 outputs a high-level signal to drive the third switching transistor 142 to conduct; conversely, when the input signal voltage is lower than the reference voltage, the comparator 141 outputs a low-level signal to turn off the third switching transistor 142. When the third switching transistor 142 conducts, current flows from the source terminal to the drain terminal (MOSFET transistor) or from the emitter terminal to the collector terminal (BJT transistor). The magnitude of this current is related to the impedance characteristics of the input signal. The conduction and cutoff of the third switching transistor 142 are controlled by the output of the comparator 141. Therefore, the change in the output current directly reflects the change in the input signal. The output terminal of the conversion module 103 is located at the drain of the third switching transistor 142 (MOSFET transistor) or the collector (BJT transistor), and the output current signal can be further converted into a frequency.

[0126] The technical effect of this embodiment is that: by comparing the voltage at the load connection terminal of the switched-capacitor module with the reference voltage through a comparator, the conversion module can very sensitively detect the voltage change at the load connection terminal of the switched-capacitor module. Furthermore, the voltage at the Vo point is clamped near the V_ref point voltage by the comparator and the third switching transistor. Therefore, the magnitude of the output current is linearly related to the frequency of the input signal. By calibrating the coefficient, the frequency of the input signal can be accurately calculated by measuring the output current.

[0127] For the output module 104 in the first embodiment, the output module 104 can be a current mirror module, including but not limited to: a fixed-ratio current mirror, a composite adjustable-ratio current mirror, a mirror current-doubling current mirror, a bipolar current mirror, and so on.

[0128] As an implementation manner of the circuit structure of the output module 104, this implementation manner is only an example and does not limit the structure of the conversion module 103. For example, Figure 12As shown, the output module 104 includes a current mirror unit, and the current mirror unit includes a fourth switching transistor M4 and a fifth switching transistor M5. One end of the fourth switching transistor M4 and one end of the fifth switching transistor M5 are commonly connected and receive the power supply voltage AVDD. The control end of the fourth switching transistor M4, the other end of the fourth switching transistor M4, and the control end of the fifth switching transistor M5 are commonly connected to form one end of the output module 104, and the other end of the fifth switching transistor M5 forms the output end of the output module 104.

[0129] Among them, the fourth switching transistor M4 can be an NMOS transistor, and the source electrode of the fourth switching transistor M4 and the source electrode or emitter of the fifth switching transistor are commonly connected to the power supply voltage AVDD. The gate electrode and drain electrode of the fourth switching transistor M4 and the gate electrode of the fifth switching transistor M5 are commonly connected to form the input end of the current mirror, which is used to receive the input current I_in and control its conduction state through the fourth switching transistor M4. The input current I_in flows in through the fourth switching transistor M4, and its gate-source voltage determines the working state of the fourth switching transistor M4. Since the gate electrodes of the fourth switching transistor M4 and the fifth switching transistor M5 are commonly connected, that is, the gate-source voltage of the fifth switching transistor M5 is the same as that of the fourth switching transistor M4. Therefore, if the sizes and characteristics of the fourth switching transistor M4 and the fifth switching transistor M5 are completely matched, the current I_out passing through the fifth switching transistor M5 will be proportional to the input current I_in. The drain electrode of the fifth switching transistor M5 forms the output end of the current mirror, and the output current I_out is copied to the load or subsequent circuits. The magnitude of the output current I_out depends on the size ratio of the fourth switching transistor M4 and the fifth switching transistor M5, that is, if the size ratios of the two are the same, then I_out is equal to I_in; if the size ratio of the fifth switching transistor M5 is n times that of the fourth switching transistor, then I_out is n times that of I_in.

[0130] The technical effect of this embodiment is that by matching the size ratios of the fourth switching transistor and the fifth switching transistor, precise current replication can be achieved, with high linearity.

[0131] As an implementation manner of the output module 104 for adjusting the current, the output module 104 further includes a current amplification unit 144, as Figure 13 shown, the current amplification unit 144 includes a sixth switching transistor M6, a seventh switching transistor M7, an eighth switching transistor M8, and a ninth switching transistor M9;

[0132] One end of the sixth switching transistor M6 and one end of the seventh switching transistor M7 are commonly connected and receive a power supply voltage. The control end of the sixth switching transistor M6 and the control end of the seventh switching transistor M7 are respectively connected to the control end of the fourth switching transistor M4. The other end of the sixth switching transistor M6 is connected to one end of the eighth switching transistor M8. The other end of the seventh switching transistor M7 is connected to one end of the ninth switching transistor M9. The other ends of the eighth switching transistor M8, the ninth switching transistor M9, and the fifth switching transistor M5 are commonly connected to form the output end of the output module 104;

[0133] The control end of the eighth switching transistor M8 is connected to the third control signal bit0, and the control end of the ninth switching transistor M9 is connected to the fourth control signal bit1. The current amplification unit 144 adjusts the amplification factor of the detected current according to the third control signal bit0 and the fourth control signal bit1.

[0134] The working process of this embodiment is as follows: The control end of the fourth switching transistor M4 is connected to the control ends of the sixth switching transistor M6 and the seventh switching transistor M7, that is, the gate-source voltage of the sixth switching transistor M6 and the seventh switching transistor M7 is the same as that of the fourth switching transistor M4, so that their currents are proportional to the current I_in input by the fourth switching transistor M4. The sources or emitters of the sixth switching transistor M6 and the seventh switching transistor M7 are commonly connected and connected to the power supply voltage (Vdd), forming the primary part of the current amplification unit 144. The drain of the sixth switching transistor M6 is connected to the source of the eighth switching transistor M8, and the drain of the seventh switching transistor M7 is connected to the source of the ninth switching transistor M9. The gates of the eighth switching transistor M8 and the ninth switching transistor M9 are respectively connected to the third control signal bit0 and the fourth control signal bit1, which are used to adjust the conduction degrees of the eighth switching transistor M8 and the ninth switching transistor M9, so as to control the flowing current. The drains of the eighth switching transistor M8 and the ninth switching transistor M9 are commonly connected to the drain of the fifth switching transistor M5, forming the output end of the output module 104. The output current is composed of the currents of the fifth switching transistor M5, the eighth switching transistor M8, and the ninth switching transistor M9. By adjusting the third control signal bit0 and the fourth control signal bit1, the conduction states of the eighth switching transistor M8 and the ninth switching transistor M9 can be changed, so as to adjust the magnitude of the output current and realize the amplification of the current.

[0135] The technical effect of this embodiment is that: Through the adjustment of the third control signal and the fourth control signal, the dynamic control of the current amplification factor is allowed, so that the output current can be adjusted in real time according to the demand, adapting to different load conditions or signal processing requirements. Since the sixth switching transistor and the seventh switching transistor share the control signal with the fourth switching transistor, the accuracy of the current mirror is guaranteed.

[0136] As a circuit structure of a clock frequency detection circuit provided in the first embodiment, this circuit structure can be a combination of different implementation manners of the above-mentioned various modules. As a combination manner, such as Figure 14As shown, the clock frequency detection circuit includes a clock signal processing module 101, a switched capacitor module 102, a conversion module 103, and an output module 104. The circuit structure of the clock signal processing module 101 can be Figure 7 and Figure 8 the circuit structures provided, and the circuit structure of the switched capacitor module 102 can be Figure 5 the circuit structure of. The conversion module 103 includes a comparator AMP, a switching transistor M5, a capacitor C3, and a capacitor C4. The comparator AMP and the switching transistor M5 form a negative feedback loop. The functions of the capacitors C3 and C4 are to reduce the jitter of the output node of the comparator AMP and the Vfb node and to ensure loop stability. The circuit structure of the output module 104 can be Figure 11 the circuit structure of. The clock signal processing module 101 converts the input clock into two non-overlapping high-level clocks, and then further converts them into four switch control signals. The switched capacitor module 102 exhibits different impedances at different clock frequencies. Through the negative feedback loop in the conversion module 103, different impedances are converted into different magnitudes of current and output through the current mirror in the output module 104. By detecting the magnitude of the output current, the input clock frequency is detected.

[0137] Example 2

[0138] Embodiment 2 provides an image sensor chip, which includes the clock frequency detection circuit provided in Embodiment 1.

[0139] The image sensor chip provided in Embodiment 2 can be widely applied to various types of image sensors, which usually require precise clock signals to ensure normal operation, including but not limited to the following image sensors:

[0140] 1. CMOS image sensor: Widely used in mobile phone cameras, digital cameras, security monitoring, and other fields.

[0141] 2. CCD image sensor: Used in high-precision cameras and professional imaging equipment.

[0142] 3. Industrial image sensor: Used in industrial applications such as machine vision systems and automated detection.

[0143] 4. Medical imaging sensor: Used in medical imaging equipment such as endoscopes and microscopes.

[0144] 5. Automotive image sensor: Used in vehicle advanced driver assistance systems (ADAS), rearview cameras, etc.

[0145] 6. Biometric sensor: Used in biometric recognition systems such as fingerprint recognition and face recognition.

[0146] The clock frequency detection circuit of this technical solution provides high-precision and wide-frequency-range detection capabilities through a switched-capacitor module and a conversion module, and can adapt to the clock signal requirements of different frequency ranges in the above various applications, thereby ensuring the normal operation of these image sensor chips in different application scenarios.

[0147] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A clock frequency detection circuit, characterized in that: include: Clock signal processing module, switch capacitor module, conversion module and output module; One end of the clock signal processing module receives the clock signal to be measured, and the other end is connected to the signal input end of the switch capacitor module to provide a switch control signal for the switch capacitor module according to the clock signal to be measured; The switch capacitor module performs periodic charging and discharging according to the switch control signal to generate an impedance corresponding to the frequency of the clock signal to be measured; One end of the conversion module is connected to the load connection end of the switch capacitor module, and the other end is connected to one end of the output module, so as to generate a corresponding detection current according to the impedance; The output module outputs the detection current to calculate the frequency of the clock signal to be measured according to the detection current.

2. The clock frequency detection circuit according to claim 1, characterized in that: The switch capacitor module includes at least one switch capacitor unit, and the switch capacitor unit includes a first charge-discharge loop and a second charge-discharge loop; In a charge and discharge cycle, one of the first charge and discharge circuit and the second charge and discharge circuit is used to enable the conversion module to charge it according to the switch control signal, and the other is used to enable it to discharge according to the switch control signal, so as to generate an impedance corresponding to the frequency of the clock signal to be measured according to the charge and discharge cycle.

3. The clock frequency detection circuit according to claim 2, characterized in that: The switch capacitor module includes a first switch capacitor unit, a second switch capacitor unit, a third switch capacitor unit and a switch circuit; The first end of the switch circuit is connected to one end of each switch capacitor unit respectively, the second end of the switch circuit constitutes the load connection end of the switch capacitor module, and the control end of the switch circuit is connected to a bit control signal to turn on or off at least one switch capacitor unit according to the bit control signal; The other end of the first switch capacitor unit, the other end of the second switch capacitor unit and the other end of the third switch capacitor unit are commonly connected to the ground.

4. The clock frequency detection circuit according to claim 2 or 3, characterized in that: The first charge-discharge loop includes a first TG gate, a first switch tube and a first capacitor, and the second charge-discharge loop includes a second TG gate, a second switch tube and a second capacitor; One end of the first TG gate and one end of the second TG gate are connected together as a load connection end of the switch capacitor unit, the other end of the first TG gate and the first end of the first capacitor are connected to one end of the first switch tube respectively, the second end of the first capacitor and the other end of the first switch tube are connected together to the ground, the other end of the second TG gate and the first end of the second capacitor are connected to one end of the second switch tube respectively, and the second end of the second capacitor and the other end of the second switch tube are connected together to the ground; The first control end of the first TG gate, the second control end of the first TG gate, the first control end of the second TG gate, and the second control end of the second TG gate are respectively connected to different switch control signals, and the second control end of the first TG gate and the control end of the second switch tube are connected to the same switch control signal, and the first control end of the second TG gate and the control end of the first switch tube are connected to the same switch control signal.

5. The clock frequency detection circuit according to claim 1, characterized in that: The clock signal processing module includes a non-overlapping clock generation circuit and a clock differential output circuit connected to each other; The non-overlapping clock generating circuit receives the clock signal to be tested to generate two non-overlapping clock signals; The clock differential output circuit outputs the switch control signal to the switch capacitor module according to the two non-overlapping clock signals.

6. The clock frequency detection circuit according to claim 5, characterized in that: The non-overlapping clock generation circuit includes a first buffer, a second buffer, a third buffer, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, a first NAND gate and a second NAND gate; The input end of the first buffer is connected to the input end of the first NOT gate and is connected to the clock signal to be measured. The output end of the first buffer is connected to the first input end of the first NAND gate, the output end of the first NAND gate is connected to the first input end of the second NAND gate, the output end of the first NAND gate is connected to the input end of the second NAND gate, the output end of the second NAND gate is connected to the input end of the third NAND gate, the output end of the third NAND gate is respectively connected to the input end of the fourth NAND gate and the second input end of the second NAND gate, the output end of the fourth NAND gate is connected to the input end of the second buffer, the output end of the second buffer outputs the first clock signal, the output end of the second NAND gate is connected to the input end of the fifth NAND gate, the output end of the fifth NAND gate is connected to the input end of the sixth NAND gate, the output end of the sixth NAND gate is respectively connected to the input end of the seventh NAND gate and the second input end of the first NAND gate, the output end of the seventh NAND gate is connected to the input end of the third buffer, and the output end of the third buffer outputs the second clock signal.

7. The clock frequency detection circuit according to claim 6, characterized in that: The clock differential output circuit includes a first clock differential output subcircuit and a second clock differential output subcircuit; The first clock differential output sub-circuit includes a fourth buffer, a fifth buffer, an eighth NOT gate, a ninth NOT gate and a tenth NOT gate, an input end of the fourth buffer receives the first clock signal, an output end of the fourth buffer is respectively connected to an input end of the eighth NOT gate and an input end of the fifth buffer, an output end of the eighth NOT gate is connected to an input end of the ninth NOT gate, an output end of the ninth NOT gate outputs a first switch control signal, an output end of the fifth buffer is connected to an input end of the tenth NOT gate, and an output end of the tenth NOT gate outputs a second switch control signal; The second clock differential output sub-circuit includes a sixth buffer, a seventh buffer, an eleventh NOT gate, a twelfth NOT gate and a thirteenth NOT gate, the input end of the sixth buffer receives the second clock signal, the output end of the sixth buffer is respectively connected to the input end of the eleventh NOT gate and the input end of the seventh buffer, the output end of the eleventh NOT gate is connected to the input end of the twelfth NOT gate, the output end of the twelfth NOT gate outputs a third switch control signal, the output end of the seventh buffer is connected to the input end of the thirteenth NOT gate, and the output end of the thirteenth NOT gate outputs a fourth switch control signal.

8. The clock frequency detection circuit according to claim 1, characterized in that: The conversion module includes a comparator and a third switch tube; The first input end of the comparator receives a reference voltage, the second input end of the comparator and one end of the third switch tube are connected together to form one end of the conversion module, the output end of the comparator is connected to the control end of the third switch tube, and the other end of the third switch tube constitutes the other end of the conversion module.

9. The clock frequency detection circuit according to claim 8, characterized in that: The conversion module further includes a third capacitor, one end of the third capacitor is connected to the output end of the comparator, and the other end of the third capacitor is grounded; and / or, The conversion module further includes a fourth capacitor, one end of the fourth capacitor is connected to the second input end of the comparator, and the other end of the fourth capacitor is grounded.

10. The clock frequency detection circuit according to claim 1, characterized in that: The output module includes a current mirror unit, and the current mirror unit includes a fourth switch tube and a fifth switch tube; One end of the fourth switch tube and one end of the fifth switch tube are connected together and receive the power supply voltage, the control end of the fourth switch tube, the other end of the fourth switch tube and the control end of the fifth switch tube are connected together to form one end of the output module, and the other end of the fifth switch tube constitutes the output end of the output module.

11. The clock frequency detection circuit according to claim 10, characterized in that: The output module further includes a current amplifying unit, and the current amplifying unit includes a sixth switch tube, a seventh switch tube, an eighth switch tube and a ninth switch tube; One end of the sixth switch tube and one end of the seventh switch tube are connected in common and receive a power supply voltage, the control end of the sixth switch tube and the control end of the seventh switch tube are connected to the control end of the fourth switch tube respectively, the other end of the sixth switch tube is connected to one end of the eighth switch tube, the other end of the seventh switch tube is connected to one end of the ninth switch tube, and the other end of the eighth switch tube, the other end of the ninth switch tube and the other end of the fifth switch tube are connected in common as the output end of the output module; The control end of the eighth switch tube is connected to the third control signal, the control end of the ninth switch tube is connected to the fourth control signal, and the current amplification unit adjusts the amplification factor of the detection current according to the third control signal and the fourth control signal.

12. An image sensor chip, characterized in that: include: A clock frequency detection circuit as claimed in any one of claims 1 to 11.

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