Image sensor and electronic device

Abstract

The utility model provides an image sensor and an electronic device, the image sensor comprises a pixel array and a voltage clamping circuit coupled to an output bit line of a pixel unit, the voltage clamping circuit comprises a starting control module used for providing starting voltage; the control end of the voltage transfer module receives the transfer voltage and is used for generating clamping voltage based on the transfer voltage, the first end receives the starting voltage, and the second end outputs the clamping voltage; and the control end of the output module receives the output control signal, and the output module is used for outputting the received clamping voltage to an output bit line. By improving the structure of the image sensor and designing the voltage clamping circuit corresponding to the output bit line, the transfer voltage provided by the control end can be converted into the clamping voltage to the output bit line, the structure design can be simplified, the clamping control precision can be improved, and the reliability of the image sensor can be improved. In addition, different clamp voltages can be controlled in different operation stages of the image sensor, the control flexibility is improved, and the final imaging quality is provided.

Description

Technical Field

[0001] The utility model belongs to the technical field of image acquisition, and particularly relates to an image sensor and an electronic device. Background Art

[0002] An image sensor is an important component of a digital camera. According to different components, it can be divided into two categories: CCD (Charge Coupled Device) and CMOS (Complementary Metal Oxide Semiconductor). With the continuous development of CMOS integrated circuit manufacturing technology, especially the design and manufacturing technology of CMOS image sensors, CMOS image sensors have gradually replaced CCD image sensors and become the mainstream. CMOS image sensors have the advantages of low voltage, low power consumption, low cost, and high integration, and have important application values in the fields of machine vision, consumer electronics, high-definition monitoring, and medical imaging.

[0003] However, in the existing design of CMOS image sensors, the signal amplitude output from the pixel unit in the pixel array to the column line often has problems of being too high or too low, which ultimately affects the imaging quality. In addition, the coupling interference of the horizontal traces in the pixel array in the existing design will also affect the output of the column line, so that the output signal of the column line of the selected row will also be affected by other pixel signals, and the current of the power supply / ground of the pixel circuit is unstable.

[0004] Therefore, it is necessary to provide an image sensor and an electronic device to solve the problems such as the column line output signal exceeding the amplitude in the prior art. Summary of the Utility Model

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present utility model is to provide an image sensor and an electronic device for solving the problems such as the column line output signal exceeding the amplitude in the prior art.

[0006] To achieve the above purpose and other related purposes, the present utility model provides an image sensor, including:

[0007] A pixel array, including a plurality of pixel units arranged in an array;

[0008] A voltage clamping circuit, coupled to the output bit line of the pixel unit, including:

[0009] A start control module for providing a start voltage;

[0010] A voltage transfer module, the control end of which receives a transfer voltage, and the voltage transfer module is used to generate a clamping voltage based on the transfer voltage, wherein the first end of the voltage transfer module is coupled to the start control module to receive the start voltage, and the second end is used to output the clamping voltage; and,

[0011] An output module, whose control terminal receives an output control signal, has its first terminal coupled to the second terminal of the voltage transfer module, and its second terminal coupled to the output bit line, for outputting the received clamping voltage to the output bit line.

[0012] The present application also provides an electronic device, including the image sensor according to any one of the above solutions.

[0013] The present application also provides a control method for the image sensor according to any one of the above solutions, and the control method includes the following steps:

[0014] Provide a pixel selection signal to read out the selected pixel unit;

[0015] Provide the output control signal and the transfer voltage to the voltage clamping circuit to control the voltage of the output bit line of the selected pixel unit based on the clamping voltage.

[0016] As described above, the image sensor and the electronic device of the present utility model, by improving the structure of the image sensor and designing a voltage clamping circuit for the corresponding output bit line, can convert the transfer voltage provided by the control terminal into a clamping voltage to the output bit line based on the design of the voltage transfer module. The present application can simplify the structure design, improve the clamping control accuracy. The present application can also control different clamping voltages at different stages of the operation of the image sensor, improve the control flexibility, and provide the final imaging quality. Description of the Drawings

[0017] Figure 1 Shown as a basic structural block diagram of an image sensor system.

[0018] Figure 2 Shown as a schematic diagram of a pixel circuit of an image sensor.

[0019] Figure 3 Shown as a schematic diagram of a voltage clamping circuit provided by an embodiment of the present application.

[0020] Figure 4 Shown as another schematic diagram of a voltage clamping circuit provided by an embodiment of the present application.

[0021] Figure 5 Shown as an application example of a pixel unit provided by an embodiment of the present application.

[0022] Figure 6 Shown as another application example of a pixel unit provided by an embodiment of the present application.

[0023] Figure 7 Shown as yet another application example of a pixel unit provided by an embodiment of the present application.

[0024] Figure 8 It shows the layout design of a voltage clamping circuit provided by an embodiment of the present application.

[0025] Figure 9 It shows an operation control example of an image sensor provided by an embodiment of the present application.

[0026] Figure 10 It shows an example of the transfer voltage design provided by an embodiment of the present application.

[0027] Description of component numbers

[0028] 110 - Start control module; 111 - Shared connection structure; 120 - Voltage transfer module; 130 - Output module; 140 - Virtual photosensitive module; 140_1, 140_2 - Virtual photosensitive sub - modules. Detailed implementation manners

[0029] The following uses specific specific examples to illustrate the implementation manners of the present utility model. Those skilled in the art can easily understand other advantages and effects of the present novelty from the content disclosed in this specification. The present novelty can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present utility model.

[0030] It should be emphasized that the term "including / comprising" when used herein refers to the presence of features, whole parts, steps or components, but does not exclude the presence or addition of one or more other features, whole parts, steps or components.

[0031] Features described and / or illustrated for one embodiment can be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or replace features in other embodiments. When detailing the embodiments of the present novelty, for ease of explanation, the cross - sectional views showing the device structure will be enlarged locally out of the general proportion. The schematic diagrams are only examples and should not limit the scope of protection of the present utility model herein. In actual production, three - dimensional spatial dimensions including length, width and depth should be included.

[0032] For convenience of description, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can also be one or more intermediate layers. The structure where the described first feature is "above" the second feature can include the embodiment where the first and second features are formed in direct contact, and can also include the embodiment where additional features are formed between the first and second features, so that the first and second features may not be in direct contact. In addition, "coupled" means that it can be directly or indirectly connected.

[0033] The illustrations provided in this embodiment only schematically illustrate the basic concept of the present utility model. Therefore, only the components related to the present utility model are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex. The content proposed by the present utility model will be described in detail below with reference to the accompanying drawings.

[0034] Figure 1 It is shown as a basic structural block diagram of an image sensor system. The image sensor includes a readout circuit and a control circuit connected to a pixel array. Additionally, a functional logic unit is connected to the readout circuit, and the readout circuit and the control circuit are connected to a status register to implement the control of the pixel array. The pixel array includes a plurality of pixels (P1, P2, P3) arranged in rows (R1, R2, R3... Ry) and columns (C1, C2, C3... Cx). The pixel signals output by the pixel array are output to the readout circuit via column lines. In some applications, the image sensor acquires and reads image data in a mode specified by the status register and then transmits it to the functional logic unit. In a specific implementation, the readout circuit may include an analog-to-digital conversion (ADC) circuit and other circuits.

[0035] In certain applications, the status register may include a programmed selection system to determine whether the readout system exposes and reads through a rolling shutter mode or a global shutter mode. The functional logic unit can store the original image data or the image data after image processing. In some implementations, the readout circuit may read out one row of image data along the readout column lines at a time. Of course, other methods can also be used to read out the image data. The operation of the control circuit can be determined by the current settings of the status register. For example, the control circuit generates a shutter signal for controlling image acquisition. In certain applications, this shutter signal can be a global exposure signal, enabling all pixels of the pixel array to simultaneously acquire their image data through a single acquisition window. In other applications, this shutter signal can also be a rolling exposure signal, enabling the pixels of each pixel row of the pixel array to continuously perform exposure reading operations through the acquisition window.

[0036] Figure 2 It is shown as a schematic diagram of a pixel unit in an image sensor. As Figure 2 shown, each pixel unit includes a photoelectric conversion element (e.g., a photodiode PD) and a pixel circuit (shown as the transistors within the dashed box in the figure). The photodiode can be a buried photodiode (PPD) applied in the current image sensor. In an application example, the pixel circuit includes a reset transistor (RST), a source follower transistor (SF), and a pixel selection transistor (RS), which are connected to as Figure 2The transfer transistor (TX) and photodiode shown in the figure. In an application example of a stacked structure, the pixel circuit includes a reset transistor, a source follower transistor, and a pixel selection transistor disposed on a first circuit chip, and further includes a transfer transistor disposed on a second circuit chip. The photodiode in the second circuit chip is connected to other transistors in the first circuit chip based on the transfer transistor. In a further application example, the pixel circuit may further include a gain control transistor (DCG) connected between a floating diffusion region (FD) and the reset transistor. During operation, the photoelectric conversion element generates photo charges in response to incident light during exposure. The transfer transistor connects a transfer signal, which controls the transfer transistor to transfer the charges accumulated in the photoelectric conversion element to the floating diffusion region. The reset transistor is connected between the power supply voltage and the floating diffusion region, and resets the sensor pixel circuit in response to a reset signal. The floating diffusion region is connected to the gate of the source follower transistor. The source follower transistor is connected between the power supply voltage and the pixel selection transistor, responds to the potential of the floating diffusion region and outputs it. The pixel selection transistor connects the source follower transistor and the bit line, and realizes pixel selection and reading in response to a pixel selection control signal.

[0037] However, in the existing CMOS image sensor design, the signal amplitude output from the pixel unit in the pixel array to the column line often has problems of being too high or too low, which ultimately affects the imaging quality. In addition, the coupling interference of the horizontal traces in the pixel array in the existing design will also affect the output of the column line, so that the output signal of the column line of the selected row will also be affected by other pixel signals, and the power supply / ground current of the pixel circuit is unstable. Therefore, it is necessary to solve the problems such as the signal amplitude of the column line output exceeding the limit in the prior art. The present utility model can effectively improve the above problems through the design of the overall array and operation of the image sensor.

[0038] Embodiment 1:

[0039] Please refer to Figure 3 and Figure 4 As shown, this embodiment provides an image sensor, including: a pixel array and a voltage clamping circuit. Among them, the pixel array includes a plurality of pixel units arranged in an array, and each pixel unit has a corresponding output bit line Bitline, and the voltage clamping circuit is coupled to the output bit line Bitline.

[0040] In one implementation, as Figure 3 and Figure 4 shown, the voltage clamping circuit includes: a start control module 110, a voltage transfer module 120, and an output module 130, where:

[0041] The start control module 110 is used to provide a start voltage, and the start voltage includes but is not limited to the power supply voltage VDD.

[0042] The control terminal of the voltage transfer module 120 receives the transfer voltage Vclamp, which is used to generate a clamping voltage under the control of the transfer voltage Vclamp. Among them, the first terminal of the voltage transfer module 120 is coupled to the startup control module 110 to receive the startup voltage so that the voltage transfer module 120 can start working, and the second terminal is used to output the clamping voltage. Among them, in this embodiment, the voltage magnitude control of the voltage on the output bit line Bitline is realized based on the transfer voltage Vclamp of the control terminal of the voltage transfer module 120.

[0043] The control terminal of the output module 130 receives the output control signal Vc. The first terminal is coupled to the second terminal of the voltage transfer module 120, and the second terminal is coupled to the output bit line Bitline, which is used to output the clamping voltage to the output bit line Bitline. Among them, in this embodiment, the selection of whether the voltage clamping circuit is turned on is realized based on the output control signal Vc of the control terminal of the output module 130, and then the output bit line that needs voltage regulation is selected.

[0044] As an example, the voltage transfer module 120 includes at least one voltage transfer crystal. As Figure 3 shown, the voltage transfer module 120 includes one voltage transfer transistor, as Figure 4 shown, the voltage transfer module 120 includes two parallel voltage transfer transistors. Of course, it can also be multiple parallel voltage transfer transistors.

[0045] Among them, the control terminal of each voltage transfer transistor receives the transfer voltage Vclamp, the first terminal is coupled to the startup control module 110, and the second terminal is coupled to the first terminal of the output module 130. For example, the voltage transfer transistor can be a source follower transistor SF, and in a specific implementation, it is an NMOS transistor. In addition, Figure 4 shows two voltage transfer transistors M4 and M5, both of which can be source follower transistors SF. Among them, when there are multiple voltage transfer transistors, the voltage transfer transistors are arranged in parallel to respectively receive the startup voltage provided by the startup control module 110 and finally output to the output module 130.

[0046] As an example, the output module 130 includes a selection output transistor RS, Figure 4 shows the selection output transistor M6. The control terminal of the selection output transistor RS receives the output control signal Vc, and the first terminal is coupled to the second terminal of the voltage transfer module 120, such as the first terminal is coupled to the second terminal of the voltage transfer transistor (such as the source follower transistor SF), and the second terminal is coupled to the output bit line Bitline. For example, the selection output transistor RS can be a pixel selection transistor, and in a specific implementation, it is an NMOS transistor.

[0047] As Figure 3As shown, for the startup control module, in one implementation, the startup control module 110 includes:

[0048] A third clamping voltage providing node FD3, coupled to the first end of the voltage transfer module 120, such as the third clamping voltage providing node FD3 is coupled to the first end of the voltage transfer transistor;

[0049] A third voltage providing module, the third voltage providing module includes at least one supply transistor, the supply transistor is coupled between the third voltage source VDD and the third clamping voltage providing node FD3; wherein, when there is one supply transistor, it can correspond to the reset transistor RST of the pixel unit; further, when there are multiple, the supply transistors are arranged in series. The control ends of the supply transistors and the second end of the series structure are coupled to the third voltage source VDD, and the first end of the series structure is coupled to the third clamping voltage providing node FD3; wherein, Figure 3 In the voltage clamping circuit shown, the third voltage providing module of the startup control module 110 includes two series-connected supply transistors. For example, the two supply transistors can be the gain control transistor DCG and the reset transistor RST respectively. In a specific implementation, both are NMOS transistors.

[0050] Such as Figure 4 As shown, in another implementation, the startup control module 110 includes:

[0051] A first clamping voltage providing node FD1, coupled to the first end of the voltage transfer module 120, such as the first clamping voltage providing node FD1 is coupled to the first end of the voltage transfer transistor M4;

[0052] A first voltage providing module, the first voltage providing module includes a first transistor M1, the first transistor M1 is coupled between the first voltage source and the first clamping voltage providing node FD1. Further optionally, the control end of the first transistor M1 is coupled to the first voltage source, the first end is coupled to the voltage source providing node provided by the second voltage providing module, and the second end is coupled to the first clamping voltage providing node FD1; wherein, in one example, the first transistor M1 can be the gain control transistor DCG, and in a specific implementation, it is an NMOS transistor;

[0053] A second clamping voltage providing node FD2, coupled to the first end of the voltage transfer module 120, such as the second clamping voltage providing node FD2 is coupled to the first end of the voltage transfer transistor M5;

[0054] The second voltage supply module includes a second transistor M2 and a third transistor M3 connected in series, which are coupled between a second voltage source and a second clamping voltage supply node FD2. The second transistor M2 and the third transistor M3 can be a gain control transistor and a reset transistor respectively. In a specific implementation, both of them are NMOS transistors. In addition, the second voltage source and the first voltage source can be the same voltage source, both being PIXVDD. Of course, in other examples, the two can be different, and different node voltage source potentials can be provided correspondingly.

[0055] In an example, the control terminal of the first transistor M1 is coupled to the first voltage source PIXVDD, the first terminal is coupled to the first clamping voltage supply node FD1, and the second terminal of the first transistor M1 is coupled to a shared node between the second terminal of the second transistor M2 and the first terminal of the third transistor M1. The control terminals of the second transistor M2 and the third transistor M3 are both coupled to the second voltage source PIXVDD. The first terminal of the second transistor M2 is further coupled to the second clamping voltage supply node FD2, and the second terminal of the third transistor M3 is further coupled to the second voltage source PIXVDD.

[0056] In an example, a shared connection structure 111 is further provided between the first clamping voltage supply node FD1 and the second clamping voltage supply node FD2. The shared connection structure 111 can be a metal interconnecting line to achieve electrical conduction between the two nodes. In other examples, the shared connection structure 111 can also be multiple metal interconnecting lines and switches connected in series between the metal interconnecting lines to control whether there is electrical conduction between adjacent ones through the switches.

[0057] As an example, as Figure 3 shown, the voltage clamping circuit further includes a virtual photosensing module 140. The virtual photosensing module 140 includes a photoelectric conversion unit PD, a transmission unit TX, and a floating diffusion unit FD3 connected in sequence. Among them, the floating diffusion unit FD3 is coupled to the start voltage supply node (such as the third clamping voltage supply node) of the start control module and the start voltage receiving node (such as the first terminal of the voltage transfer transistor) of the voltage transfer module 120. Among them, the numbers of the photoelectric conversion unit PD and the transmission unit TX can be set according to actual situations.

[0058] As Figure 4 shown, the virtual photosensing module 140 can also include multiple virtual photosensing sub-modules. Figure 4Two virtual photosensor sub-modules 140_1 and 140_2 are shown, corresponding to the floating diffusion nodes FD1 and FD2 respectively. Among them, the number of photoelectric conversion units PD and transmission units TX in each sub-module can be set according to the actual situation. The above arrangement is beneficial to realizing the correspondence between the virtual photosensor module 140 and the photosensor module of the pixel unit, so that the virtual photosensor module of the voltage clamping circuit and the photosensor module of the pixel unit can be fabricated simultaneously. Further, each transistor and node in the voltage clamping circuit can correspond one-to-one and be the same as each transistor and node in the pixel circuit of the pixel unit, and its own function can be realized through different electrical connections when controlling signals.

[0059] It should be noted that, as shown in Figures 5 to 7 , the photosensor module in the pixel unit can have various design methods. For example, Figure 5 shows a non-shared pixel unit design, Figure 6 shows a 2×2 shared pixel unit design, Figure 7 shows a 2×4 shared pixel unit design. Among them, Figure 5 has one photoelectric conversion element PD, corresponding to one transmission transistor TX, and has one floating diffusion node FD. Therefore, it is preferable to apply the voltage clamping circuit in Figure 3 to the image sensor composed of this pixel unit; Figure 6 has four photoelectric conversion elements PDa to PDd, corresponding to four transmission transistors TXa to TXd, and has one floating diffusion node FD. Therefore, it is preferable to apply the voltage clamping circuit in Figure 3 to the image sensor composed of this pixel unit, and it is further preferable to design the photoelectric conversion element and the transmission transistor as four; Figure 7 a shared group of structures in has eight photoelectric conversion elements, two groups of photoelectric conversion elements PD1 to PD4, corresponding to eight transmission transistors, and has two floating diffusion nodes FD. Therefore, it is preferable to apply the voltage clamping circuit in Figure 4 to the image sensor composed of this pixel unit. In this example array, two of the three pixel units share the reset transistor RST and the pixel selection transistor RS respectively, and further the gain control transistor DCG can be shared.

[0060] As an example, the image sensor includes a pixel area and an auxiliary circuit area. The pixel array is arranged in the pixel area, and the voltage clamping circuit is arranged in the auxiliary circuit area. The positional relationship between the pixel area and the auxiliary circuit area can be designed according to actual needs. Among them, multiple voltage clamping circuits are arranged in an array, and are correspondingly set and coupled to the corresponding output bit lines with the pixel units of the pixel array to realize voltage control of pixel unit data output.

[0061] In a specific example, the arrangement array of the voltage clamping circuit includes at least two rows, such as four rows; further, each column of the arrangement array corresponds one-to-one with the columns of the pixel array formed by pixel units, so as to control the output bit lines corresponding to the columns of the corresponding pixel array based on at least two voltage clamping circuits in the same column.

[0062] As an example, the image sensor includes a virtual area, and the auxiliary circuit area is arranged in the virtual area. Optionally, the image sensor further includes a black pixel area, and the virtual area is located between the pixel area and the black pixel area. That is, the arrangement of the voltage clamping circuit can be implemented in the virtual area based on the existing design of the image sensor, without wasting chip area. The pixels in the virtual area can be the existing design of the image sensor for isolation or sacrifice, etc.

[0063] As an example, the layout and structure of the transistors of the voltage clamping circuit are the same as those of the transistors of the pixel circuit in the pixel unit. Among them, the start voltage providing node of the start control module and the start voltage receiving node of the voltage transfer module are coupled to the node corresponding to the floating diffusion unit of the pixel unit.

[0064] Specifically, in this example, the number and arrangement of the transistors of the voltage clamping circuit are the same as those of the transistors of the pixel circuit in the pixel unit. Therefore, the voltage clamping circuit can be prepared based on the same mask plate as the pixel unit. That is, the voltage clamping circuit and the pixel unit can jointly form an array arranged periodically, which can improve the overall consistency of the device and simplify the manufacturing process. In addition, the functions required by each can be achieved through different upper-layer wiring connections. Among them, corresponding to the floating diffusion node FD of the pixel unit, the voltage clamping circuit has a start voltage providing node, which also serves as the start voltage receiving node of the voltage transfer module to finally realize the control of the output bit line. Among them, the transistor design of the voltage clamping circuit, for example, can be the same as Figure 5 the non-shared pixel unit design shown, and can also be the same as Figure 6 the 2×2 shared pixel unit design shown, and can also be the same as Figure 7 the 2×4 shared pixel unit design shown. The two can include corresponding identical transistors. Further, the voltage clamping control of the output bit line is realized through the control of the potential connections of the ends of the transistors.

[0065] As an example, the voltage clamping circuit and the pixel unit are prepared on the same semiconductor substrate based on the same process or the two are prepared on different semiconductor substrates. Among them, the voltage clamping circuit and the pixel unit can be prepared on one semiconductor substrate. Of course, the two can also be separately prepared on different wafers.

[0066] Specifically, the voltage clamping circuit and the pixel unit can be fabricated on a semiconductor substrate. For corresponding and consistent structures, they can be fabricated based on the same mask. For example, the overall array, i.e., the pixel array, can be set to include an m-row voltage clamping circuit (clamp pixel) array and an n-row pixel unit (normal pixel) array. Among them, the front-end of the voltage clamping circuit (clamp pixel) array is the same as that of the pixel unit array (normal pixel), while the back-end is different (BEOL). For example, the gate of the source follower transistor (SF) (voltage transfer transistor) of the corresponding pixel unit of the voltage clamping circuit (clamp pixel) is connected to the voltage control signal (transfer voltage) clamp Vref in the row direction, and has a corresponding control voltage for bit line voltage control. The gate of the pixel selection transistor (RS) (selection output transistor) of the corresponding pixel unit of the voltage clamping circuit (clamp pixel) is connected to the output control signal clamp en (with a corresponding enable voltage for enabling, the output control signal); this can achieve the function of physically redundant (dummy) pixels, with the least impact on the optical and electrical characteristics of the pixel unit (normal pixel).

[0067] As an example, the image sensing further includes a control circuit. The control circuit includes a first driving stage and a second driving stage. The first driving stage corresponds to the pixel selection unit of the pixel unit to at least turn off the pixel selection unit, and the second driving stage corresponds to the output module of the voltage clamping circuit to at least turn off the output module.

[0068] Specifically, in this example, the control circuit of the image sensor with a voltage clamping circuit is designed. The first driving stage and the second driving stage are set to respectively control the gate control signal of the pixel selection transistor in the pixel unit and the output control signal in the output unit of the voltage clamping circuit, so as to effectively control the conduction and turn-off of the corresponding circuits. In addition, the design of these multiple driving stages is also beneficial to the flexible fabrication of the corresponding transistors in the pixel unit array and the voltage clamping circuit array. For example, the front-end of the voltage clamping circuit is fabricated based on the pixel circuit. The threshold of the pixel selection transistor (RS) of the pixel unit is relatively low, and it is difficult to effectively turn off using AGND and requires a negative voltage to turn off. Therefore, the circuit that generates the output control signal of the output module of the voltage clamping circuit can modify the driving stage (the first driving stage) of the pixel selection transistor in the pixel unit to obtain a driving stage (the second driving stage) dedicated to the output control signal of the output module of the voltage clamping circuit, so as to obtain the control selection ability of negative voltage turn-off and strong driving ability. Of course, the second driving stage can be modified based on the first driving stage or fabricated separately, as long as the corresponding required turn-off is achieved.

[0069] Please refer to Figure 8As shown, by way of example, each output bitline includes at least two voltage clamping circuits, and the at least two voltage clamping circuits correspond to voltage control in different stages of pixel unit operation.

[0070] By way of example, the voltage clamping circuit includes at least two of a reset clamping circuit, an image clamping circuit, a transfer clamping circuit, and a selection clamping circuit. In one example, the voltage clamping circuit includes four clamping circuits: a reset clamping circuit, an image clamping circuit, a transfer clamping circuit, and a selection clamping circuit. It can be implemented by an array composed of four rows of clamping circuits, and each output bitline corresponds to four co-column clamping circuits; where:

[0071] The reset clamping circuit is used to perform voltage control in the reset signal readout stage of the pixel unit based on the transfer voltage and the output control signal; for example, the first row of Clamp pixel is the row of the reset clamping circuit, and the corresponding transfer voltage and output control signal are clamp vref1 and clamp en1 respectively;

[0072] The image clamping circuit is used to perform voltage control in the image signal readout stage of the pixel unit based on the transfer voltage and the output control signal; for example, the second row of Clamp pixel is the row of the image clamping circuit, and the corresponding transfer voltage and output control signal are clamp vref2 and clamp en2 respectively;

[0073] The transfer clamping circuit is used to perform voltage control in the transfer stage of the image signal of the pixel unit based on the transfer voltage and the output control signal; for example, the third row of Clamp pixel is the row of the transfer clamping circuit, and the corresponding transfer voltage and output control signal are clamp vref3 and clamp en3 respectively; it takes effect when the bitline voltage is disturbed by the TX switch, and plays a role in preventing excessive disturbance of the bitline and rapid establishment;

[0074] The selection clamping circuit is used to perform voltage control in the stage where the pixel selection unit of the pixel unit is disabled and the image signal is not transferred based on the transfer voltage and the output control signal. For example, the m-th row of Clamp pixel is the row of the selection clamping circuit, and the corresponding transfer voltage and output control signal are Clamp vref m and Clamp en m respectively. In this example, m is selected as the fourth row of Clamp pixel is the row of the selection clamping circuit; it is enabled during the period when RS is not opened, which can prevent the voltage on the output bitline from being pulled to a very low voltage by the tail current source when the unselected row is not selected at this time. If it is pulled down, the re-establishment will be slow, so it also plays a role in rapid establishment.

[0075] Please refer to Figure 9 As shown, a specific operation example of a pixel unit and a voltage clamping circuit is provided, where:

[0076] For the currently selected row (Normal pixel), the exposure ends at time t1. At this time, the pixel selection transistor rs is not yet turned on, the transfer transistor tx is in the off state. Further, the conversion gain transistor dcg can be in the on state, and the reset transistor rst can be in the on state;

[0077] At time t2, the pixel selection transistor rs is turned on to start signal reading;

[0078] In one implementation, at time t3, the conversion gain transistor dcg is turned off. Correspondingly, the reset transistor rst can be turned on or off, and the reset signal Vrst is read out. At this time, the floating diffusion node FD of the pixel unit has the reset potential Vrst, and the output bitline bitline has the output potential corresponding to Vrst;

[0079] In other implementations, at time t3, it can also be that the reset transistor rst is turned off. Correspondingly, the conversion gain transistor dcg can be turned on or off, and the reset signal Vrst is read out;

[0080] At times t4 and t5, the transfer transistor tx is turned on for a predetermined time and then turned off, and the image signal obtained through the photoelectric conversion element is transferred to the floating diffusion point FD of the pixel unit. At this time, the floating diffusion node FD of the pixel unit has the image potential Vsig, and the output bitline bitline has the output potential corresponding to Vsig;

[0081] Among them, in one example, the predetermined time for turning on the transfer transistor tx can also correspond to the simultaneous turning off of the pixel selection transistor rs, which can help reduce the influence of the process of turning on and off the transfer transistor tx on the potential of the output bitline bitline. The predetermined time is set based on the operation of the image sensor according to actual requirements;

[0082] At time t6, the reset transistor rst and the conversion gain transistor dcg are turned on, and the potential of the floating diffusion node FD of the pixel unit returns to the reset state; then, at time t7, the pixel selection transistor rs is turned off.

[0083] In addition, it should be noted that for the operations of the conversion gain transistor dcg and the reset transistor rst, different readout requirements can be expected and controlled with reference to the operations of traditional image sensors. For example, the reset signal and the image signal at different gains (high gain HCG and low gain LCG) can be read out correspondingly.

[0084] Continue to refer to Figure 9 As shown, for the currently selected row (Normal pixel), the specific operation of the corresponding voltage clamping circuit (Clamppixel) can be:

[0085] At the end of the exposure at time t1, at this time, the output control signal rst clamp en of the reset clamping circuit is not enabled, the output control signal sig clamp en of the image clamping circuit is not enabled, and the output control signal transclamp en of the transfer clamping circuit is not enabled;

[0086] Among them, the output control signal pix clamp en of the selection clamping circuit is enabled, and the output bit line corresponding to the operation row is voltage-controlled through the corresponding transfer voltage pixclamp vref;

[0087] At time t2, the pixel selection transistor rs of the corresponding pixel unit is turned on, and the output control signal pix clamp en of the selection clamping circuit enables the low level to turn off the selection clamping circuit;

[0088] At time t3, the floating diffusion stage FD reset signal provided in the corresponding pixel unit changes the potential of the floating diffusion stage FD, the output control signal rst clamp en of the reset clamping circuit is enabled, and the output bit line corresponding to the operation row is voltage-controlled through the corresponding transfer voltage rstclamp vref;

[0089] At time t4, the transfer transistor tx in the corresponding pixel unit is turned on, the image signal provided to the floating diffusion stage FD in the corresponding pixel unit changes the potential of the floating diffusion stage FD additionally, the output control signal rst clamp en of the reset clamping circuit enables the low level to turn off the reset clamping circuit, the output control signal transclamp en of the transfer clamping circuit is enabled, and the output bit line corresponding to the operation row is voltage-controlled through the corresponding transfer voltage trans clamp vref;

[0090] At time t5, the transfer transistor tx in the corresponding pixel unit is turned off, the output control signal trans clamp en of the transfer clamping circuit enables the low level to turn off the transfer clamping circuit, the output control signal sigclamp en of the image clamping circuit is enabled, and the output bit line corresponding to the operation row is voltage-controlled through the corresponding transfer voltage sig clamp vref;

[0091] At time t6, the potential of the floating diffusion node FD in the corresponding pixel unit is restored to the reset state, and the output control signal sig clamp en of the image clamping circuit enables the low level to turn off the image clamping circuit;

[0092] At time t7, the pixel selection transistor rs of the corresponding pixel unit is turned off, the output control signal pix clamp en of the selection clamping circuit is enabled, and the output bit line corresponding to the operation row is voltage-controlled through the corresponding transfer voltage pix clamp vref.

[0093] Embodiment 2:

[0094] Please refer to Figures 8 to 10 As shown, this embodiment also provides a control method for an image sensor, which can be applied to the image sensor described in any of the above solutions. The control method includes the following steps:

[0095] Provide a pixel selection signal to read out the selected pixel unit; that is, control the image sensor during the signal readout stage of the pixel unit. The selected pixel unit can be defined according to the existing design.

[0096] Provide an output control signal and a transfer voltage to the voltage clamping circuit to control the voltage of the output bit line of the preset pixel unit based on the clamping voltage. Specifically, the signal of the selected pixel unit is read out via the output bit line bitline during the readout stage, which may include the reset signal and the image signal corresponding to the selected pixel unit. In this stage, the voltage clamping circuit is started, the transfer voltage is provided to the voltage transfer module, and the output control signal is provided to the output module, so that the clamping voltage can be received and the corresponding clamping voltage is provided to the currently selected output bit line bitline, making the voltage on the output bit line bitline ideal.

[0097] As an example, different voltage clamping circuits are controlled for voltage control at different stages of pixel unit operation; in this example, different clamping voltage controls can be performed at different stages of the signal readout process of the pixel unit. For example, the reset clamping circuit can be used for control during the reset signal readout stage, the image clamping circuit can be used for control during the image signal readout stage, and the transfer clamping circuit can be used for control during the stage when the image signal is transferred to the floating diffusion node. For details, please refer to Figure 8 and Figure 9 description.

[0098] As an example, the control method of the image sensor further includes: providing a pixel selection cut-off signal to the pixel unit. During the pixel selection cut-off stage, an output control signal and a transfer voltage are provided to the voltage clamping circuit. When the pixel selection unit of the pixel unit is not enabled and the image signal is not transferred, the voltage of the output bit line of the selected pixel unit is controlled based on the clamping voltage.

[0099] Specifically, the image sensor may further include a non-reading stage, and the voltage of the corresponding output bitline can also be controlled during the non-reading stage. For example, during the exposure stage, the global reset stage before exposure, and the idle stage, etc., the corresponding output bitline can be controlled. Further, during the above non-reading stage, a selective clamping circuit can be used for control, providing an output control signal and a transfer voltage to the selective clamping circuit. In addition, it should be noted that during the transfer process before the corresponding image signal is read out, the pixel selection transistor also undergoes a closing process, as Figure 9 shown by the dashed line where the pixel selection transistor rs in the middle closes. In this example, it can be considered as the reading stage, which is understandable to those skilled in the art.

[0100] As an example, during the image signal readout phase of the pixel unit, the magnitude of the transfer voltage provided by the voltage clamping circuit is positively correlated with the analog gain of the image signal quantization; in this example, a method for controlling the clamping voltage during the image signal readout phase is provided, and the clamping voltage of the voltage clamping circuit is adjusted based on the selected analog gain. For example, in the 1× gain mode, the power supply voltage VDD of the currently selected pixel unit in the reset state is 2.8V. When the reset transistor is set to a low level, the reset signal Vrst of the floating diffusion node FD is approximately 2.4V. After being output by the source follower transistor SF, the reset signal Vrst of the output bitline is approximately 2.1V (Vrst at bitline); when the transfer transistor tx is turned on and the electrons accumulated by the photodiode PD during the exposure process are transferred to the floating diffusion node FD, the image signal Vsig of the floating diffusion node FD is approximately 1.2V. After being output to the column line bitline by the source follower transistor SF, the image signal Vsig is approximately 1.05V (Vsig at bitline). Then, in the 1× gain mode, the quantization signal of the analog-to-digital conversion circuit is Vcds = Vrst - Vsig = 2.1 - 1.05 = 1.05V. Under the condition that its quantization range is [0, 1.05V], when the gain is set to 1x, the voltage control signal sig vref clamp of the image clamping circuit is set to 0.8 (corresponding to the clamping voltage provided to the output bitline); thus, effective clamping of the bitline signal level can be achieved, and the level of the bitline is prevented from being lower than 0.8V (assuming the threshold of the source follower transistor of the unselected row pixel is 0). According to the above implementation process, when the quantization amplification circuit is set to a 2x gain, the quantization range of the analog-to-digital conversion circuit of the image sensor is [0, 0.525V], the lowest quantization signal value of the corresponding bitline is 1.575V, and the voltage control signal sig vref clamp of the image clamping circuit can be set to 1.2V; the changes caused by the gains of the remaining quantization amplification circuits can be deduced by analogy. The quantization range of the analog-to-digital conversion circuit of the image sensor is obtained under the corresponding analog gain, and the lowest quantization signal value of the corresponding bitline is obtained. A value smaller than the lowest quantization signal value of the corresponding bitline is selected. For example, when the quantization amplification circuit is set to a 4x gain, the voltage control signal sig vref clamp of the image clamping circuit can be set to 1.5V.

[0101] As an example, during at least one of the reset signal readout phase, the image signal transfer phase, and the phase when the pixel selection unit is disabled and the image signal is not transferred, the transfer voltage provided by the voltage clamping circuit remains consistent under different analog gains of the image signal quantization.

[0102] Specifically, in the above stages, regardless of the gain mode selected by the analog circuit for signal quantization, the same clamping voltage is set. Among them, the analog gain can be set according to actual requirements using the design and operation of existing image sensors. For example, in the reset signal readout stage, a reset clamping circuit is used, and the corresponding voltage control signal rst clampvref is set to 1.85V at various gains; in the image signal transfer stage before image signal readout, a transfer clamping circuit is used, and the corresponding voltage control signal trans clamp vref is set to 2.2V at various gains; in the non-readout stage, a selection clamping circuit is used, and the corresponding voltage control signal pix clamp vref is set to 2.0V at various gains.

[0103] In addition, in the reset signal readout stage, the control method of the transfer voltage can also be that the magnitude of the transfer voltage is positively correlated with the analog gain of image signal quantization.

[0104] Embodiment 3:

[0105] The present utility model also provides an electronic device, including the image sensor described in any one of the above solutions. The electronic device can be a security monitoring device, a vehicle-mounted electronic device, a mobile phone camera, a machine vision device, etc. Based on the image sensor of the present utility model, high-quality image information can be obtained, and it can also be used for an infrared utilization device.

[0106] In summary, for the image sensor and the electronic device of the present utility model, by improving the structure of the image sensor and designing a voltage clamping circuit for the corresponding output bit line, the transfer voltage provided by the control end can be converted into a clamping voltage to the output bit line based on the design of the voltage transfer module. This application can simplify the structural design, improve the clamping control accuracy, and can also control different clamping voltages at different stages of the operation of the image sensor, improve the control flexibility, and provide the final imaging quality. Therefore, the present utility model effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0107] The above embodiments are only illustrative of the principles and effects of the present utility model, and are not used to limit the present utility model. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present utility model. All equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present utility model should still be covered by the claims of the present utility model.

Claims

1. An image sensor, characterized in that: The image sensor comprises: A pixel array, comprising a plurality of pixel units arranged in an array; A voltage clamp circuit, coupled to an output bit line of the pixel unit, comprises: A starting control module, used for providing a starting voltage; a voltage transfer module, the control end of which receives the transfer voltage, the voltage transfer module is used to generate a clamping voltage based on the transfer voltage, wherein a first end of the voltage transfer module is coupled to the startup control module for receiving the startup voltage, and a second end of the voltage transfer module is used to output the clamping voltage; and The output module has a control end receiving an output control signal, a first end coupled to the second end of the voltage transfer module, and a second end coupled to an output bit line, and is used to output the received clamping voltage to the output bit line.

2. The image sensor according to claim 1, wherein: The voltage transfer module includes at least one voltage transfer transistor, the control end of each voltage transfer transistor receives the transfer voltage to generate the clamping voltage, the first end is coupled to the startup control module, and the second end is coupled to the first end of the output module, wherein, when there are multiple voltage transfer transistors, each of the voltage transfer transistors is arranged in parallel to respectively receive the startup voltage provided by the startup control module; and / or, the output module includes an output selection transistor, the control end receives the output control signal, the first end is coupled to the second end of the voltage transfer module, and the second end is coupled to the output bit line.

3. The image sensor according to claim 1, wherein: The startup control module includes: A first clamping voltage providing node coupled to a first terminal of the voltage transfer module; a first voltage providing module, the first voltage providing module comprising a first transistor, the first transistor being coupled between a first voltage source and the first clamping voltage providing node; A second clamping voltage providing node coupled to the first end of the voltage transfer module; A second voltage providing module, comprising a second transistor and a third transistor connected in series, wherein the series structure is coupled between a second voltage source and the second clamping voltage providing node; wherein the first end of the first transistor is coupled to the first clamping voltage supply node, the first end of the second transistor is coupled to the second clamping voltage supply node, and the first end of the third transistor and the second end of the second transistor are connected to form the series structure; The control terminal and the second terminal of the third transistor, the control terminal and the second terminal of the first transistor, and the control terminal of the second transistor are all coupled to the same or different voltage source potentials; Alternatively, the startup control module includes: A third clamping voltage providing node coupled to the first end of the voltage transfer module; a third voltage supply module, the third voltage supply module comprising at least one supply transistor, the supply transistor being coupled between a third voltage source and the third clamping voltage supply node, wherein when there are a plurality of the supply transistors, the supply transistors are arranged in series; The control end of each supply transistor and the second end of the third voltage providing module are coupled to the third voltage source, and the first end is coupled to the third clamping voltage providing node.

4. The image sensor according to claim 3, wherein: The control end of the first transistor is coupled to a first voltage source, the second end of the first transistor is coupled to a shared node between the second end of the second transistor and the first end of the third transistor, the control end of the second transistor, the control end of the third transistor and the second end of the third transistor are all coupled to a second voltage source, and the first voltage source and the second voltage source are the same or different voltage sources.

5. The image sensor according to claim 3, wherein: A shared connection structure is also provided between the first clamping voltage supply node and the second clamping voltage supply node.

6. The image sensor according to claim 1, wherein: The voltage clamping circuit also includes a virtual photosensor module, which includes a photoelectric conversion unit, a transmission unit and a floating diffusion unit coupled in sequence, wherein the floating diffusion unit is coupled to a startup voltage providing node of the startup control module and a startup voltage receiving node of the voltage transfer module.

7. The image sensor according to claim 6, wherein: The virtual photosensitive module includes a plurality of sub-virtual photosensitive modules, each of which corresponds to a sub-floating diffusion node, wherein each sub-floating diffusion node is coupled to a different start-up voltage providing node of the start-up control module and a different start-up voltage receiving node of the voltage transfer module.

8. The image sensor according to claim 1, wherein: The image sensor includes a pixel area and an auxiliary circuit area, the pixel array is arranged in the pixel area, and the voltage clamping circuit is arranged in the auxiliary circuit area, wherein a plurality of the voltage clamping circuits are arranged in an array, and the voltage clamping circuit is arranged corresponding to the pixel unit of the pixel array and coupled to the corresponding output bit line.

9. The image sensor according to claim 8, wherein: The layout and structure of the transistors of the voltage clamping circuit are consistent with those of the transistors of the pixel circuit in the pixel unit, wherein the startup voltage supply node of the startup control module and the startup voltage receiving node of the voltage transfer module are coupled to the node corresponding to the floating diffusion unit of the pixel unit; and / or, the voltage clamping circuit and the pixel unit are prepared in the same semiconductor substrate based on the same process or both are prepared in different semiconductor substrates; and / or, the image sensor includes a virtual area, the auxiliary circuit area is arranged in the virtual area, and the voltage clamping circuit is set based on the virtual area pixels of the virtual area; and / or, the array of the voltage clamping circuit includes at least two rows of the voltage clamping circuit rows, and the voltage clamping circuit columns in the array of the voltage clamping circuit correspond one-to-one to the pixel unit columns in the pixel array.

10. The image sensor according to claim 1, wherein: The image sensor also includes a control circuit, which includes a first driving stage and a second driving stage, wherein the first driving stage corresponds to a pixel selection unit of the pixel unit to at least turn off the pixel selection unit, and the second driving stage corresponds to the output module of the voltage clamping circuit to at least turn off the output module.

11. The image sensor according to any one of claims 1 to 10, characterized in that: At least two voltage clamping circuits are included corresponding to each of the output bit lines, wherein the at least two voltage clamping circuits control the voltage of the output bit line corresponding to different stages of the operation of the pixel unit.

12. The image sensor according to claim 11, wherein: The voltage clamp circuit includes at least two voltage clamp circuits of a reset clamp circuit, an image clamp circuit, a transfer clamp circuit and a selection clamp circuit to correspond to voltage control at different stages of operation of the pixel unit, wherein: The reset clamp circuit is used to perform voltage control at the reset signal readout stage of the pixel unit based on the transfer voltage and the output control signal; the image clamp circuit is used to perform voltage control at the image signal readout stage of the pixel unit based on the transfer voltage and the output control signal; the transfer clamp circuit is used to perform voltage control at the transfer stage of the image signal of the pixel unit based on the transfer voltage and the output control signal; and, The selection clamp circuit is used to perform voltage control based on the transfer voltage and the output control signal when the pixel selection unit of the pixel unit is not enabled and the image signal is not transferred.

13. An electronic device, characterized in that: The electronic device comprises the image sensor as claimed in any one of claims 1-12.

Images