Electronic equipment ventilation computer testing device

Abstract

The utility model discloses a computer testing device for ventilation of electronic equipment, which comprises a case, the case is provided with an AEVC testing equipment panel, and a JA pin row, a JB pin row, a valve feedback circuit for testing equipment valve position signals and a logic processing circuit are arranged in the case; the JA pin row is used for realizing AEVC control signal output, and the JB pin row is used for realizing feedback signal and analog signal input; the AEVC test equipment panel is divided into operation areas according to functions, and the JA pin row, the JB pin row, the valve feedback circuit and the logic processing circuit are electrically connected with operation parts of the operation areas on the AEVC test equipment panel through lines. According to the utility model, the independent test of the AEVC can be realized, the successful development can establish the complete test of the ventilation computer of the electronic equipment, so that the high-efficiency and high-quality maintenance of the component becomes possible, the investment cost of a large amount of outsourcing equipment can be saved, the domestic replacement test is realized, and the safety test requirement of the component is met.

Description

Technical Field

[0001] The utility model relates to the technical field of test equipment, in particular to a ventilation computer test device for electronic equipment. Background Art

[0002] An Avionics Equipment Ventilation Computer (AEVC) controls the ventilation of the aircraft's avionics bay and monitors all equipment under its control. The main functions are as follows:

[0003] - Define and monitor the control of 6 valves and 2 fans based on the aircraft skin temperature, engine ON data algorithm, ground-air conditions or special configurations.

[0004] - Monitor various equipment involved in the system operation and indicate any final failures.

[0005] - Test these equipment items.

[0006] - Monitor an optional cooling electronic equipment ventilation computer test device and indicate any final failures

[0007] The Avionics Equipment Ventilation Computer is the main control computer for controlling the valves and fans and giving alarms in the avionics bay of an A320 aircraft. It is installed in the cockpit and there is only one. The pressure switches and temperature sensors in the system send the status information of the relevant system to the AEVC, and the cabin pressure controller and the Landing Gear Control and Interface Unit (LGCIU) send supplementary information to the AEVC. For the domestic maintenance and support of the avionics equipment ventilation computer, it is still highly monopolized by OEM manufacturers at present, resulting in high maintenance costs and long maintenance cycles, bringing huge operation and cost pressures to domestic aviation users. Content of the Utility Model

[0008] In view of this, the purpose of the utility model is to provide a ventilation computer test device for electronic equipment, which can realize the independent test of the AEVC.

[0009] The purpose of the utility model is achieved by the following technical solutions:

[0010] This electronic device ventilation computer test device includes a chassis, which is provided with an AEVC test device panel. Inside the chassis, there are a JA pin row, a JB pin row, a valve feedback circuit for the test device flap position signal, and a logic processing circuit. The JA pin row is used to output the AEVC control signal, and the JB pin row is used to input the feedback signal and analog signal. The AEVC test device panel is divided into operation areas according to functions, including a power switch area, a discrete switch control area, a flap and fan indicator area, a flap open or close signal output area, and a flap open or close feedback signal area. Each operation area uses one or more operation components such as indicators, jacks, and switches. The JA pin row, JB pin row, valve feedback circuit, and logic processing circuit are electrically connected to the operation components of each operation area on the AEVC test device panel through lines.

[0011] Further, the first pin, eighth pin, eleventh pin, fourteenth pin, eighteenth pin, and twenty-first pin of the JA pin row are respectively connected to 28V DC. The second pin to the seventh pin, ninth pin to the tenth pin, twelfth pin to the thirteenth pin, and twentieth pin of the JA pin row are respectively grounded after being connected in series with a resistor and a forward-connected light-emitting diode. The fifteenth pin is grounded after being connected in series with a forward-connected diode, a resistor, and a forward-connected light-emitting diode. The sixteenth pin and seventeenth pin are respectively connected to 28V DC after being connected with a resistor and a reverse-connected light-emitting diode. The nineteenth pin is grounded after being connected in series with a forward-connected diode, a resistor, and a forward-connected light-emitting diode. The twenty-second and twenty-third pins are directly grounded.

[0012] Further, the first pin of the JB pin row is connected to the GND terminal through the first switch, the second pin through the second switch, the third pin through the third switch, the fourth pin through the fourth switch, the fifth pin through the fifth switch, the sixth pin through the sixth switch, and the seventh pin through the seventh switch respectively. The common contact of these seven pins is connected to the stationary contact of the second switchable switch VB; the eighth pin is connected to the first stationary contact of the first switchable switch VA, and a live door A open position feedback sampling point AO is provided on this line; the ninth pin is connected to the second stationary contact of the first switchable switch VA, and a live door A closed position feedback sampling point AF is provided on this line; the tenth pin is connected to the first stationary contact of the second switchable switch VB, and a live door B open position feedback sampling point BO is provided on this line; the thirteenth pin is connected to the second stationary contact of the second switchable switch VB, and a live door B closed position feedback sampling point BF is provided on this line; the eleventh pin is connected to the second stationary contact of the third switchable switch VC, and a live door C closed position feedback sampling point CF is provided on this line; the twelfth pin is connected to the second stationary contact of the third switchable switch VC, and a live door C open position feedback sampling point CO is provided on this line; the fourteenth pin is connected to the GND terminal through the eighth switch, and a live door B half-open position feedback sampling point BP is provided on this line; the fifteenth pin is connected to the first stationary contact of the fourth switchable switch VD, and a live door D open position feedback sampling point DO is provided on this line; the seventeenth pin is connected to the second stationary contact of the fourth switchable switch VD, and a live door D closed position feedback sampling point DF is provided on this line; the sixteenth pin is connected to the first stationary contact of the fifth switchable switch VE, and a live door E open position feedback sampling point EO is provided on this line; the twentieth pin is connected to the second stationary contact of the fifth switchable switch VE, and a live door E closed position feedback sampling point EF is provided on this line; the eighteenth pin is connected to the GND terminal through the tenth switch; the nineteenth pin is connected to the GND terminal through the ninth switch;

[0013] The twenty-first pin is connected to the first stationary contact of the sixth switchable switch VF, and a live door F open position feedback sampling point FO is provided on this line; the twenty-second pin is connected to the first stationary contact of the sixth switchable switch VF, and a live door F closed position feedback sampling point FF is provided on this line; the twenty-third pin is connected to the GND terminal through the eleventh switch, the twenty-fourth pin through the twelfth switch, the twenty-fifth pin through the thirteenth switch, the twenty-sixth pin through the fourteenth switch, and the twenty-seventh pin through the fifteenth switch respectively;

[0014] The twenty-eighth to thirty-second pins are respectively connected to 28V DC through a series connection of a resistor and a light-emitting diode with reverse connection. Among them, the twenty-eighth pin is connected to the GND terminal through the sixteenth switch; the twenty-ninth pin is connected to the GND terminal through the seventeenth switch; the thirtieth pin is connected to the GND terminal through the eighteenth switch; the thirty-first pin is connected to the GND terminal through the nineteenth switch; the thirty-second pin is connected to the GND terminal through the twentieth switch; the thirty-third pin and the thirty-fifth pin are respectively connected to 28V DC through a series connection of a resistor and a light-emitting diode with reverse connection; the thirty-fourth pin is connected to the GND terminal through a series connection of a resistor and a light-emitting diode with forward connection.

[0015] Further, the valve feedback circuit includes the first triode Q1 to the thirteenth triode Q13. The collectors of the first to sixth triodes are all connected together. The emitters of the first to sixth triodes are all connected together and then grounded; the collectors of the seventh to thirteenth triodes, the twelfth to thirteenth triodes are all connected together. The emitters of the seventh to thirteenth triodes are all connected together and then grounded. The collector of the eleventh triode is connected to the external power supply Vcc.

[0016] Further, the logic processing circuit includes a power supply chip U3, a first logic gate circuit chip U1, a second logic gate circuit chip U2, and the first to sixth inverters. The Vin pin of the power supply chip U3 is connected to 28V DC, and a first capacitor is connected in series between the Vin pin and the GND pin of U3. The positive electrode of the first capacitor is connected to the Vin pin, and the negative electrode of the first capacitor is connected to the GND pin. The common connection point of the first capacitor and the GND pin is set as point O, and point O is grounded.

[0017] The base of the first triode Q1 is connected to the input terminal of the first inverter U3A, and the base of the second triode Q2 is connected to the output terminal of the first inverter U3A. At the same time, the input terminal of the first inverter is also connected to the Q0 output pin of the second logic gate circuit chip U2; the base of the third triode Q3 is connected to the input terminal of the second inverter U3B, and the base of the fourth triode Q4 is connected to the output terminal of the second inverter U3B. At the same time, the input terminal of the second inverter is also connected to the Q1 output pin of the second logic gate circuit chip U2; the base of the fifth triode Q5 is connected to the input terminal of the third inverter U3C, and the base of the sixth triode Q6 is connected to the output terminal of the third inverter U3C. At the same time, the input terminal of the third inverter is also connected to the Q2 output pin of the second logic gate circuit chip U2; the base of the seventh triode Q7 is connected to the input terminal of the fourth inverter U3D, and the base of the eighth triode Q8 is connected to the output terminal of the fourth inverter U3D. At the same time, the input terminal of the fourth inverter is also connected to the Q3 output pin of the second logic gate circuit chip U2

[0018] The base of the thirteenth triode Q13 is connected to the output terminal of the fifth inverter U3E, and the base of the twelfth diode Q12 is connected to the input terminal of the fifth inverter U3E. At the same time, the input terminal of the fifth inverter U3E is also connected to the Q0 output pin of the first logic gate circuit chip U1; the base of the eleventh diode Q11 is connected to the Q1 output pin of the first logic gate circuit chip U1; the base of the ninth triode Q9 is connected to the input terminal of the sixth inverter U3F, and the base of the thirteenth triode Q10 is connected to the output terminal of the sixth inverter U3F. The input terminal of the sixth inverter U3F is also connected to the Q3 output pin of the first logic gate circuit chip U1;

[0019] Further, the S0 pin of the first logic gate circuit chip U1 is used to receive the control output signal P3-3 for opening the valve B, the R0 pin of the chip U1 is used to receive the control output signal P3-4 for closing the valve B, the S1 pin and the R2 pin of the first logic gate circuit chip U1 are used to receive the control output signal P3-5 for half-opening the valve B, the S3 pin of the chip U1 is used to receive the control output signal P3-6 for opening the valve A, and the R3 pin of the chip U1 is used to receive the control output signal P3-7 for closing the valve A; among them, the S0 pin, the S3 pin, and the R3 pin are also respectively connected to the common connection point of the first capacitor and the GND pin, that is, point O, after being connected in series with a resistor; the R0 pin, the S1 pin, and the S2 pin are connected in series with a resistor and then connected to point O after being connected, and the R3 pin is also connected to the EN pin through a switch KA;

[0020] Further, the S0 pin of the second logic gate circuit chip U2 is used to receive the control output P3-8 for closing the valve C, the R0 pin of the chip U2 is used to receive the control output signal P3-9 for opening the valve C, the S1 pin of the second logic gate circuit chip U2 is used to receive the control output signal P3-10 for opening the valve D, the R1 pin of the chip U2 is used to receive the control output signal P3-11 for closing the valve D, the S2 pin of the second logic gate circuit chip U2 is used to receive the control output signal P3-12 for opening the valve D, and the R2 pin of the chip U2 is used to receive the control output signal P3-13 for closing the valve D; the S3 pin of the second logic gate circuit chip U2 is used to receive the control output signal P3-14 for opening the valve F, and the R3 pin of the chip U2 is used to receive the control output signal P3-15 for closing the valve F; wherein, the S0 pin, R0 pin, S1 pin, R1 pin, S2 pin, R2 pin, S3 pin, and R3 pin of the second logic gate circuit chip U2 are also respectively connected to the O point and grounded after being connected in series with a resistor; the S3 pin of the chip U2 is also connected to the EN pin of the chip U2 through a switch KF.

[0021] The beneficial effects of the present utility model are as follows:

[0022] Through the present utility model, the independent test of the AEVC can be realized. Its successful development can establish a complete test for the electronic equipment ventilation computer, making it possible to achieve efficient and high-quality maintenance of this component, saving a large amount of investment costs for purchased equipment, realizing domestic substitution testing, and meeting the requirements of component safety testing.

[0023] Other advantages, objectives, and features of the present utility model will be described to some extent in the subsequent description, and to some extent, will be obvious to those skilled in the art based on the study of the following text, or can be taught from the practice of the present utility model. The objectives and other advantages of the present utility model can be achieved and obtained through the following description. Description of the Drawings

[0024] In order to make the objectives, technical solutions, and advantages of the present utility model clearer, the present utility model will be further described in detail below in conjunction with the drawings, where:

[0025] Figure 1 It is a schematic diagram of the panel of the AEVC test equipment;

[0026] Figure 2 It is a schematic diagram of the circuit connection of the JA pin row;

[0027] Figure 3 It is a schematic diagram of the circuit connection of the JB pin row;

[0028] Figure 4Schematic diagram of the circuit connection for the valve feedback circuit and the logic processing circuit;

[0029] Figure 5 Schematic diagram of the test connection for the present invention. Specific embodiments

[0030] Hereinafter, with reference to the accompanying drawings, the preferred embodiments of the present invention will be described in detail. It should be understood that the preferred embodiments are only for explaining the present invention, rather than limiting the protection scope of the present invention.

[0031] The AEVC changes the system configuration (the combination of the opening and closing states of the valves and fans) according to the aircraft skin temperature and the aircraft's air / ground signal. That is to say, when the opening and closing of the valves and fans are in a certain state combination, the change of the aircraft skin temperature and the aircraft's air / ground signal input to the AEVC will cause the AEVC to change the current opening and closing of the valves and fans to another state combination. Therefore, the core idea of testing the AEVC is that the test equipment inputs the discrete quantities, temperature analog quantities, discrete quantities of the valve states in each CASE, and discrete quantities of other states of different configurations into the AEVC according to Table 1, and checks that the control signal output and ARINC429 data output of the AEVC should meet the requirements of the component maintenance manual.

[0032] The configuration of the present invention consists of the air / ground signal, the exhaust fan override input state, the blower override input state, the DITCHING input state, corresponding to the switches in the test equipment, and the switch grounding is effective.

[0033] The discrete quantity of the valve state is input by the switch in the test equipment (as shown in the attached drawing), and the switch grounding is effective. In the functional test, it needs to be set to the middle position, and the valve state feedback is completed by Q1 - Q13 of the valve feedback circuit. In special test items, such as the opening inhibition test of valves B and C, the maintenance input test, the in - flight maintenance inhibition test, and the storage backup test after long - term power interference, the state feedback of each valve needs to be fed back to the AEVC according to the following table as required.

[0034] Valve A position feedback Switch VA Valve B position feedback Switch VB Note: Valve B half-open position feedback Switch BP Valve C position feedback Switch VC Valve D position feedback Switch VD Valve E position feedback Switch VE Valve F position feedback Switch VF

[0035] The discrete quantities of other states include alarms, engine control, memory erasure, etc., as shown in the following table, and the switch grounding is effective.

[0036] Exhaust fan alarm Switch EXT Smoke alarm Switch SMOKE Blower 1 alarm Switch SOU 1 Blower 2 alarm Switch SOU 2 High temperature alarm Switch TEMP Ventilation unit fault alarm control Switch DVG Ventilation unit fault alarm control Switch DFG Engine 1 control Switch REAC1 Engine 2 control Switch REAC2 Ventilation unit low pressure alarm control Switch BPG Ventilation unit identification control Switch IDENT Self-check control Switch MAINT

[0037] The electronic device ventilation computer test device of this embodiment involves the automatic control test of 6 valves and 2 fans in the electronic cabin. The device includes a chassis, on which an AEVC test equipment panel is provided. Inside the chassis, there are JA pin rows, JB pin rows, a valve feedback circuit for testing the position signals of the valves, and a logic processing circuit; the JA pin row is used to output AEVC control signals, and the JB pin row is used to input feedback signals and analog signals; as Figure 1 shown, on the AEVC test equipment panel, the operation areas are divided according to functions, including a power switch area (POWER), a discrete switch control area (DISCRETEIN), a valve and fan indicator area (VA AND FA IND), a valve open or close signal output area (VA AND FAOUT), and a valve open or close feedback signal area (VALVE FEED). Each operation area uses one or more of the operation components such as indicators, jacks, and switches; the JA pin row, JB pin row, valve feedback circuit, and logic processing circuit are electrically connected to the operation components of each operation area on the AEVC test equipment panel through lines. The descriptions of the switches, test holes, and indicators on the AEVC test equipment panel are shown in the following table:

[0038]

[0039]

[0040]

[0041]

[0042]

[0043] As Figure 2 shown, in this embodiment, the first pin, eighth pin, eleventh pin, fourteenth pin, eighteenth pin, and twenty - first pin of the JA pin row are respectively connected to 28V DC. The second pin to the seventh pin, ninth pin to the tenth pin, twelfth pin to the thirteenth pin, and twentieth pin of the JA pin row are respectively grounded after being connected in series with a resistor and a forward - connected light - emitting diode. The fifteenth pin is grounded after being connected in series with a forward - connected diode, a resistor, and a forward - connected light - emitting diode. The sixteenth pin and seventeenth pin are respectively connected to 28V DC after being connected with a resistor and a reverse - connected light - emitting diode. The nineteenth pin is grounded after being connected in series with a forward - connected diode, a resistor, and a forward - connected light - emitting diode. The twenty - second and twenty - third pins are directly grounded.

[0044] Description of JA pins:

[0045]

[0046]

[0047] The first pin of the JB pin bank is connected to the GND terminal through the first switch, the second pin through the second switch, the third pin through the third switch, the fourth pin through the fourth switch, the fifth pin through the fifth switch, the sixth pin through the sixth switch, and the seventh pin through the seventh switch respectively. The common contact of these seven pins is connected to the stationary contact of the second switchable switch VB; the eighth pin is connected to the first stationary contact of the first switchable switch VA, and a feedback sampling point AO for the open position of the valve A is set on this line; the ninth pin is connected to the second stationary contact of the first switchable switch VA, and a feedback sampling point AF for the closed position of the valve A is set on this line; the tenth pin is connected to the first stationary contact of the second switchable switch VB, and a feedback sampling point BO for the open position of the valve B is set on this line; the thirteenth pin is connected to the second stationary contact of the second switchable switch VB, and a feedback sampling point BF for the closed position of the valve B is set on this line; the eleventh pin is connected to the second stationary contact of the third switchable switch VC, and a feedback sampling point CF for the closed position of the valve C is set on this line; the twelfth pin is connected to the second stationary contact of the third switchable switch VC, and a feedback sampling point CO for the open position of the valve C is set on this line; the fourteenth pin is connected to the GND terminal through the eighth switch, and a feedback sampling point BP for the half-open position of the valve B is set on this line; the fifteenth pin is connected to the first stationary contact of the fourth switchable switch VD, and a feedback sampling point DO for the open position of the valve D is set on this line; the seventeenth pin is connected to the second stationary contact of the fourth switchable switch VD, and a feedback sampling point DF for the closed position of the valve D is set on this line; the sixteenth pin is connected to the first stationary contact of the fifth switchable switch VE, and a feedback sampling point EO for the open position of the valve E is set on this line; the twentieth pin is connected to the second stationary contact of the fifth switchable switch VE, and a feedback sampling point EF for the closed position of the valve E is set on this line; the eighteenth pin is connected to the GND terminal through the tenth switch; the nineteenth pin is connected to the GND terminal through the ninth switch;

[0048] The twenty-first pin is connected to the first stationary contact of the sixth switchable switch VF, and a feedback sampling point FO for the open position of the valve F is set on this line; the twenty-second pin is connected to the first stationary contact of the sixth switchable switch VF, and a feedback sampling point FF for the closed position of the valve F is set on this line; the twenty-third pin is connected to the GND terminal through the eleventh switch, the twenty-fourth pin through the twelfth switch, the twenty-fifth pin through the thirteenth switch, the twenty-sixth pin through the fourteenth switch, and the twenty-seventh pin through the fifteenth switch respectively;

[0049] The twenty-eighth to thirty-second pins are respectively connected to 28V DC through a series connection of a resistor and a light-emitting diode connected in reverse. Among them, the twenty-eighth pin is connected to the GND terminal through the sixteenth switch; the twenty-ninth pin is connected to the GND terminal through the seventeenth switch; the thirtieth pin is connected to the GND terminal through the eighteenth switch; the thirty-first pin is connected to the GND terminal through the nineteenth switch; the thirty-second pin is connected to the GND terminal through the twentieth switch; the thirty-third pin and the thirty-fifth pin are respectively connected to 28V DC through a series connection of a resistor and a light-emitting diode connected in reverse; the thirty-fourth pin is connected to the GND terminal through a series connection of a resistor and a light-emitting diode connected in forward.

[0050] JB pin description:

[0051]

[0052]

[0053]

[0054] The valve feedback circuit includes the first triode Q1 to the thirteenth triode Q13. The collectors of the first to sixth triodes are all connected together. The emitters of the first to sixth triodes are all connected together and then grounded; the collectors of the seventh to thirteenth triodes and the twelfth to thirteenth triodes are all connected together. The emitters of the seventh to thirteenth triodes are all connected together and then grounded. The collector of the eleventh triode is connected to the external power supply Vcc.

[0055] As Figure 4 As shown, the logic processing circuit includes a power chip U3, a first logic gate circuit chip U1, a second logic gate circuit chip U2, and the first to sixth inverters. The Vin pin of the power chip U3 is connected to 28V DC, and a first capacitor is connected in series between the Vin pin and the GND pin of U3. The positive pole of the first capacitor is connected to the Vin pin, and the negative pole of the first capacitor is connected to the GND pin. The common connection point of the first capacitor and the GND pin is set as point O, and point O is grounded.

[0056] The base of the first triode Q1 is connected to the input terminal of the first inverter U3A, the base of the second triode Q2 is connected to the output terminal of the first inverter U3A, and at the same time, the input terminal of the first inverter is also connected to the Q0 output pin of the second logic gate circuit chip U2; the base of the third triode Q3 is connected to the input terminal of the second inverter U3B, the base of the fourth triode Q4 is connected to the output terminal of the second inverter U3B, and at the same time, the input terminal of the second inverter is also connected to the Q1 output pin of the second logic gate circuit chip U2; the base of the fifth triode Q5 is connected to the input terminal of the third inverter U3C, the base of the sixth triode Q6 is connected to the output terminal of the third inverter U3C, and at the same time, the input terminal of the third inverter is also connected to the Q2 output pin of the second logic gate circuit chip U2; the base of the seventh triode Q7 is connected to the input terminal of the fourth inverter U3D, the base of the eighth triode Q8 is connected to the output terminal of the fourth inverter U3D, and at the same time, the input terminal of the fourth inverter is also connected to the Q3 output pin of the second logic gate circuit chip U2

[0057] The base of the thirteenth triode Q13 is connected to the output terminal of the fifth inverter U3E, the base of the twelfth diode Q12 is connected to the input terminal of the fifth inverter U3E, and at the same time, the input terminal of the fifth inverter U3E is also connected to the Q0 output pin of the first logic gate circuit chip U1; the base of the eleventh diode Q11 is connected to the Q1 output pin of the first logic gate circuit chip U1; the base of the ninth triode Q9 is connected to the input terminal of the sixth inverter U3F, the base of the tenth triode Q10 is connected to the output terminal of the sixth inverter U3F, and the input terminal of the sixth inverter U3F is also connected to the Q3 output pin of the first logic gate circuit chip U1;

[0058] The S0 pin of the first logic gate circuit chip U1 is used to receive the control output signal P3-3 for opening the valve B, the R0 pin of the chip U1 is used to receive the control output signal P3-4 for closing the valve B, the S1 pin and the R2 pin of the first logic gate circuit chip U1 are used to receive the control output signal P3-5 for half-opening the valve B, the S3 pin of the chip U1 is used to receive the control output signal P3-6 for opening the valve A, and the R3 pin of the chip U1 is used to receive the control output signal P3-7 for closing the valve A; among them, the S0 pin, the S3 pin, and the R3 pin are also respectively connected to the common connection point of the first capacitor and the GND pin, that is, point O, after being connected in series with a resistor; the R0 pin, the S1 pin, and the S2 pin are connected in series with a resistor and then connected to point O, and the R3 pin is also connected to the EN pin through a switch KA;

[0059] The S0 pin of the second logic gate circuit chip U2 is used to receive the control output P3-8 for closing valve C, the R0 pin of the chip U2 is used to receive the control output signal P3-9 for opening valve C, the S1 pin of the second logic gate circuit chip U2 is used to receive the control output signal P3-10 for opening valve D, the R1 pin of the chip U2 is used to receive the control output signal P3-11 for closing valve D, the S2 pin of the second logic gate circuit chip U2 is used to receive the control output signal P3-12 for opening valve D, and the R2 pin of the chip U2 is used to receive the control output signal P3-13 for closing valve D; the S3 pin of the second logic gate circuit chip U2 is used to receive the control output signal P3-14 for opening valve F, and the R3 pin of the chip U2 is used to receive the control output signal P3-15 for closing valve F; wherein, the S0 pin, R0 pin, S1 pin, R1 pin, S2 pin, R2 pin, S3 pin, and R3 pin of the second logic gate circuit chip U2 are respectively connected to point O and grounded after being serially connected with a resistor; the S3 pin of the chip U2 is also connected to the EN pin of the chip U2 through a switch KF. In this embodiment, U1 uses a four-NOR RS latch, U2 uses a four-NOR RS latch, and U3 uses a six-inverter; the logic outputs of U1 and U2 are shown in the following table:

[0060] S R E Q X X 0 High resistance 0 0 1 Unchanged 1 0 1 1 0 1 1 0 1 1 1 Invalid

[0061] The control signal output and feedback check operations are as follows:

[0062] The control signal output and feedback of AEVC for valves A, C, D, E, and F are similar in logical processing. The following is the opening signal output and feedback check of AEVC for valve A. Valves C, D, E, and F can refer to valve A.

[0063] I. Valve A

[0064] (1) AEVC outputs an opening signal for valve A:

[0065] AEVC inputs a high level at the #9 pin (VAO P3-6) of the connector JA;

[0066] ↓

[0067] The indicator light VAO in the VA AND FA IND area of the test equipment panel is lit, indicating that AEVC outputs an opening signal for valve A;

[0068] At the same time, a logic 1 (high level) is input at the 14th pin of U1 by P3-6; Note: When the S and R pins of U1 input logic 1 at the same time, the output is invalid

[0069] ↓

[0070] The 1st pin (P3-31) of U1 outputs a logic 1 (high level);

[0071] ↓

[0072] The indicator light VA in the VALVE STATE area of the test equipment panel is lit by P3-31, indicating that the valve A is in the open state;

[0073] P3-31 inputs a high level at AA11 (the base of transistor Q9) through a resistor, Q9 conducts, and the pin VAPOSO (P3-28) of AEVC is grounded through Q9, feeding back the open state of the valve A to AEVC;

[0074] P3-31 inputs a low level at AA12 (the base of transistor Q10) through U3 and a resistor, and Q10 is cut off.

[0075] (2) AEVC outputs a closing signal for valve A:

[0076] AEVC inputs a high level at the #10 pin (VAO P3-7) of the connector JA;

[0077] ↓

[0078] The indicator light VAF in the VA AND FA IND area of the test equipment panel is lit, indicating that AEVC outputs a closing signal for valve A;

[0079] At the same time, P3-7 inputs logic 1 (high level) at the 15th pin of U1;

[0080] Note: When logic 1 is input to both the S and R pins of U1, the output is invalid;

[0081] ↓

[0082] The 1st pin (P3-31) of U1 outputs logic 0 (low level);

[0083] ↓

[0084] The low level of P3-31 cannot light the indicator light VA in the VALVE STATE area of the test equipment panel, indicating that the valve A is in the closed state;

[0085] P3-31 inputs a low level at AA11 (the base of transistor Q9) through a resistor, and Q9 is cut off

[0086] P3-31 inputs a high level at AA12 (the base of transistor Q10) through U3 and a resistor, Q10 conducts, and P3-29 is discretely grounded through Q10, feeding back the closed state of VA to AEVC.

[0087] II. Valve B

[0088] (1) AEVC outputs a closing signal for valve B:

[0089] AEVC inputs a high level at pin #7 (VAO P3-4) of connector JA;

[0090] ↓

[0091] The indicator light VBF in the VA AND FA IND area of the test equipment panel is lit, indicating that the AEVC output valve closing signal is displayed;

[0092] At the same time, logic 1 (high level) is input at pins 3, 7, and 12 of U1 by P3-4;

[0093] Note: The output is invalid when logic 1 is input at the S and R pins of U1 simultaneously;

[0094] ↓

[0095] Pin 2 of U1 outputs logic 0 (low level), that is, P3-32 is at low level;

[0096] Pin 9 of U1 outputs logic 0 (low level);

[0097] Pin 10 of U1 outputs logic 1 (high level);

[0098] ↓

[0099] The low level of P3-32 cannot light the indicator light VB in the VALVE STATE area of the test equipment panel, indicating that valve B is in the closed state;

[0100] The low level of P3-32 outputs a low level at AA9 (the base of Q12) through a resistor;

[0101] - The low level of P3-32 outputs a high level at AA10 (the base of Q13) through U3 and a resistor;

[0102] The logic 1 output from pin 10 of U1 outputs a high level at pins 12 and 13 of UA through a resistor;

[0103] ↓

[0104] AA10 (the base of Q13) inputs a high level and Q13 conducts;

[0105] - Pins 12 and 13 of UA input a high level and U4 conducts;

[0106] ↓

[0107] The pin VBPOSF (P3-27) of AEVC is grounded through U4 and Q13, feeding back the closed state of valve B to AEVC;

[0108] AEVC outputs a valve B opening signal

[0109] - AEVC inputs a high level at pin #6 (VAO P3-3) of connector JA;

[0110] ↓

[0111] Light up the indicator light VBO in the VA AND FA IND area of the test equipment panel to display the AEVC output valve opening signal;

[0112] At the same time, input logic 1 (high level) to pin 4 of U1 by P3-3;

[0113] Note: If logic 1 is input to the S and R pins of U1 at the same time, the output is invalid

[0114] ↓

[0115] The output of pin 2 of U1 is logic 1 (low level), that is, P3-32 is high level;

[0116] Since logic 0 (low level) is input to pins 11 and 12 of U1, the output of pin 10 of U1 remains logic 1 (high level);

[0117] ↓

[0118] Light up the indicator light VB in the VALVE STATE area of the test equipment panel by P3-32, indicating that valve B is in the open state;

[0119] P3-32 is high level and outputs high level at AA9 (base of Q12) through a resistor;

[0120] P3-32 high level outputs low level at AA10 (base of Q13) through U3 and a resistor;

[0121] The output of logic 1 of pin 10 of U1 outputs high level at pins 12 and 13 of UA through a resistor;

[0122] ↓

[0123] AA9 (base of Q12) inputs high level and Q12 conducts;

[0124] AA10 (base of Q13) inputs low level and Q13 cuts off;

[0125] Pins 12 and 13 of UA input high level and U4 conducts;

[0126] ↓

[0127] The pin VBPOSO (P3-27) of AEVC is grounded through U4 and Q12, and the open state of valve B is fed back to AEVC;

[0128] AEVC outputs a semi-open signal for valve B

[0129] AEVC inputs high level at pin #15 of connector JA (VAO P3-5);

[0130] ↓

[0131] Light up the indicator light VBP in the VA AND FA IND area of the test equipment panel to display the signal that the AEVC output valve B is half open;

[0132] At the same time, input logic 1 (high level) to pins 6 and 11 of U1 by P3-5;

[0133] Note: If logic 1 is input to the S and R pins of U1 simultaneously, the output is invalid

[0134] ↓

[0135] - Output logic 1 (high level) from pin 9 (AA13) of U1;

[0136] - Output logic 0 (low level) from pin 10 (QQ3) of U1;

[0137] ↓

[0138] AA13 (the base of transistor Q11) inputs a high level, Q11 conducts, and the pin VBPOSP (P3-30) of AEVC is grounded through Q11 to feedback the half-open state of valve B back to AEVC;

[0139] The test connection of the present utility model is as Figure 5 shown. The test device uses a 28V DC power supply. The power supply signal is input from the terminal block in the lower right corner of the rear panel. One end of the test cable is connected to the component AEVC, and the other end is connected to the test device. The cable is a point-to-point connection. This device can complete function tests such as power supply test, automatic test, load and overcurrent test, discrete function test, warning test, maintenance test, and output of the ARINC429 analyzer for AEVC.

[0140] In the above embodiments of the present utility model, the descriptions of each embodiment have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only illustrative. For example, the division of the units can be a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of units or modules can be in electrical or other forms.

[0141] The unit described as a separation component may or may not be physically separated. The component shown as a unit may or may not be a physical unit, that is, it may be located in one place or distributed over multiple units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0142] In addition, each functional unit in various embodiments of the present invention may be integrated in a processing unit, may exist separately as individual physical units, or two or more units may be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware.

[0143] It should be noted that the drawings of the present invention are only for illustrative purposes, showing only schematic diagrams rather than actual diagrams, and should not be construed as a limitation on the present invention; for better illustration of the embodiments of the present invention, some components in the drawings will be omitted, enlarged or reduced, which does not represent the size of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0144] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the present technical solution, and they should all be covered by the scope of the claims of the present invention.

Claims

1. Electronic equipment ventilation computer test device, characterized in that: The device includes a chassis, which is provided with an AEVC test equipment panel, and the chassis is internally provided with a JA pin row, a JB pin row, and a valve feedback circuit and a logic processing circuit for a valve position signal of the test equipment; the JA pin row is used to realize the AEVC control signal output, and the JB pin row is used to realize the feedback signal and analog signal input; the operation areas on the AEVC test equipment panel are divided according to functions, including a power switch area, a discrete switch control area, a valve and fan indicator light area, a valve open or close signal output area, and a valve open or close feedback signal area, and each operation area adopts one or more operation components selected from indicator lights, jacks, and switches; the JA pin row, the JB pin row, the valve feedback circuit, and the logic processing circuit are electrically connected to the operation components of each operation area on the AEVC test equipment panel through lines.

2. The electronic equipment ventilation computer test device according to claim 1, characterized in that: Pin 1, pin 8, pin 11, pin 14, pin 18 and pin 21 of the JA pin row are respectively connected to 28VDC, pins 2 to 7, pins 9 to 10, pins 12 to 13 and pin 20 of the JA pin row are respectively connected to ground via a resistor and a forward-connected light-emitting diode in series, pin 15 is connected to ground via a forward-connected diode, a resistor and a forward-connected light-emitting diode in series in sequence, pin 16 and pin 17 are connected to 28V DC via a resistor and a reverse-connected light-emitting diode in series, pin 19 is connected to ground via a forward-connected diode, a resistor and a forward-connected light-emitting diode in series in sequence, and pins 22 and 23 are directly grounded.

3. The electronic equipment ventilation computer test device according to claim 1 or 2, characterized in that: The first pin of the JB pin row is connected to the GND end through switch No. 1, the second pin is connected to switch No. 2, the third pin is connected to switch No. 3, the fourth pin is connected to switch No. 4, the fifth pin is connected to switch No. 5, the sixth pin is connected to switch No. 6, and the seventh pin is connected to switch No.

7. The common contact of these seven pins is connected to the static contact of the second switchable switch (VB); the eighth pin is connected to the static contact No. 1 of the first switchable switch (VA), and the valve A open position feedback sampling point (AO) is set on the circuit; the ninth pin is connected to the static contact No. 2 of the first switchable switch (VA), and the valve A closed position feedback sampling point (AF) is set on the circuit; the tenth pin is connected to the static contact No. 1 of the second switchable switch (VB), and the valve B open position feedback sampling point (BO) is set on the circuit; the thirteenth pin is connected to the static contact No. 2 of the second switchable switch (VB), and the valve B closed position feedback sampling point (BF) is set on the circuit; the eleventh pin is connected to the static contact No. 2 of the third switchable switch (VC), and the circuit The closed position feedback sampling point (CF) of valve C is arranged on the circuit; the twelfth pin is connected to the second static contact of the third switchable switch (VC), and the open position feedback sampling point (CO) of valve C is arranged on the circuit; the fourteenth pin is connected to the GND terminal through the eighth switch, and the half-open position feedback sampling point (BP) of valve B is arranged on the circuit; the fifteenth pin is connected to the first static contact of the fourth switchable switch (VD), and the open position feedback sampling point (DO) of valve D is arranged on the circuit; the seventeenth pin is connected to the second static contact of the fourth switchable switch (VD), and the closed position feedback sampling point (DF) of valve D is arranged on the circuit; the sixteenth pin is connected to the first static contact of the fifth switchable switch (VE), and the open position feedback sampling point (EO) of valve E is arranged on the circuit; the twentieth pin is connected to the second static contact of the fifth switchable switch (VE), and the closed position feedback sampling point (EF) of valve E is arranged on the circuit; the eighteenth pin is connected to the GND terminal through the tenth switch; the nineteenth pin is connected to the GND terminal through the nineteenth switch; The 21st pin is connected to the first static contact of the sixth switchable switch (VF), and a valve F open position feedback sampling point (FO) is provided on the circuit; the 22nd pin is connected to the first static contact of the sixth switchable switch (VF), and a valve F closed position feedback sampling point (FF) is provided on the circuit; the 23rd pin is connected to the GND terminal through the 11th switch, the 24th pin is connected to the 12th switch, the 25th pin is connected to the 13th switch, the 26th pin is connected to the 14th switch, and the 27th pin is connected to the 15th switch respectively; The 28th to 32nd pins are respectively connected to 28V DC through a resistor and a reverse-connected light-emitting diode in series, wherein the 28th pin is connected to the GND terminal through switch No. 16; the 29th pin is connected to the GND terminal through switch No. 17; the 30th pin is connected to the GND terminal through switch No. 18; the 31st pin is connected to the GND terminal through switch No. 19; the 32nd pin is connected to the GND terminal through switch No. 20; the 33rd and 35th pins are respectively connected to 28VDC through a resistor and a reverse-connected light-emitting diode in series; the 34th pin is connected to the GND terminal through a resistor and a forward-connected light-emitting diode in series.

4. The electronic equipment ventilation computer test device according to claim 3, characterized in that: The valve feedback circuit includes a first transistor (Q1) to a thirteenth transistor (Q13), wherein the collectors of the first to sixth transistors are connected together, and the emitters of the first to sixth transistors are connected together and then grounded; the collectors of the seventh to tenth transistors and the twelfth to thirteenth transistors are connected together, and the emitters of the seventh to thirteenth transistors are connected together and then grounded, and the collector of the eleventh transistor is connected to an external power supply Vcc.

5. The electronic equipment ventilation computer test device according to claim 4, characterized in that: The logic processing circuit includes a power chip U3, a first logic gate circuit chip U1, a second logic gate circuit chip U2, and a first inverter to a sixth inverter; the Vin pin of the power chip U3 is connected to 28V DC and a first capacitor is connected in series between the Vin pin and the GND pin of U3, the positive electrode of the first capacitor is connected to the Vin pin, and the negative electrode of the first capacitor is connected to the GND pin; the common point of the first capacitor and the GND pin is set as point O, and point O is grounded; The base of the first transistor (Q1) is connected to the input end of the first inverter (U3A), the base of the second transistor (Q2) is connected to the output end of the first inverter (U3A), and the input end of the first inverter is also connected to the Q0 output pin of the second logic gate circuit chip (U2); the base of the third transistor (Q3) is connected to the input end of the second inverter (U3B), the base of the fourth transistor (Q4) is connected to the output end of the second inverter (U3B), and the input end of the second inverter is also connected to the Q1 output pin of the second logic gate circuit chip (U2) The base of the fifth transistor (Q5) is connected to the input end of the third inverter (U3C), the base of the sixth transistor (Q6) is connected to the output end of the third inverter (U3C), and the input end of the third inverter is also connected to the Q2 output pin of the second logic gate circuit chip (U2); the base of the seventh transistor (Q7) is connected to the input end of the fourth inverter (U3D), the base of the eighth transistor (Q8) is connected to the output end of the fourth inverter (U3D), and the input end of the fourth inverter is also connected to the Q3 output pin of the second logic gate circuit chip (U2). The base of the thirteenth transistor (Q13) is connected to the output end of the fifth inverter (U3E), the base of the twelfth diode (Q12) is connected to the input end of the fifth inverter (U3E), and the input end of the fifth inverter (U3E) is also connected to the Q0 output pin of the first logic gate circuit chip (U1); the base of the eleventh diode (Q11) is connected to the Q1 output pin of the first logic gate circuit chip (U1); the base of the ninth transistor (Q9) is connected to the input end of the sixth inverter (U3F), the base of the thirteenth transistor (Q10) is connected to the output end of the sixth inverter (U3F), and the input end of the sixth inverter (U3F) is also connected to the Q3 output pin of the first logic gate circuit chip (U1).

6. The electronic equipment ventilation computer test device according to claim 5, characterized in that: The S0 pin of the first logic gate circuit chip (U1) is used to receive the control output signal (P3-3) for opening valve B, the R0 pin of the chip (U1) is used to receive the control output signal (P3-4) for closing valve B, the S1 pin and R2 pin of the first logic gate circuit chip (U1) are used to receive the control output signal (P3-5) for half-opening valve B, the S3 pin of the chip (U1) is used to receive the control output signal (P3-6) for opening valve A, and the R3 pin of the chip (U1) is used to receive the control output signal (P3-7) for closing valve A; wherein, the S0 pin, S3 pin, and R3 pin are also connected to the common point of the first capacitor and the GND pin, i.e., point O, after being connected in series with a resistor; the R0 pin, S1 pin, and S2 pin are connected to point O through a series resistor after being connected, and the R3 pin is also connected to the EN pin through a switch (KA).

7. The electronic equipment ventilation computer test device according to claim 5 or 6, characterized in that: The S0 pin of the second logic gate circuit chip (U2) is used to receive the control output signal (P3-8) of closing valve C, the R0 pin of the chip (U2) is used to receive the control output signal (P3-9) of opening valve C, the S1 pin of the second logic gate circuit chip (U2) is used to receive the control output signal (P3-10) of opening valve D, the R1 pin of the chip (U2) is used to receive the control output signal (P3-11) of closing valve D, the S2 pin of the second logic gate circuit chip (U2) is used to receive the control output signal (P3-12) of opening valve D, and the R2 pin of the chip (U2) is used to receive The valve D control output signal (P3-13) is closed; the S3 pin of the second logic gate circuit chip (U2) is used to receive the valve F control output signal (P3-14), and the R3 pin of the chip (U2) is used to receive the valve F control output signal (P3-15) is closed; wherein, the S0 pin, R0 pin, S1 pin, R1 pin, S2 pin, R2 pin, S3 pin, and R3 pin of the second logic gate circuit chip (U2) are also connected to point O and then grounded after being connected in series with a resistor; the S3 pin of the chip (U2) is also connected to the EN pin of the chip (U2) through a switch (KF).

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