Simulation circuit for micro short circuit of battery

Abstract

The utility model discloses an analog circuit for battery micro short circuit. The analog circuit comprises a master control circuit which is connected in parallel with two ends of an instrument to be tested; the frequency selection circuit is connected with the master control circuit through a first selection switch; the micro short circuit degree selection circuit is connected with the frequency selection circuit through a first phase inverter; wherein the frequency selection circuit comprises a first capacitor combination, the first capacitor combination comprises a plurality of capacitors with different capacitance values, and each capacitor corresponds to the occurrence frequency of a micro short circuit; the micro short circuit degree selection circuit comprises a second capacitor combination, a time delay circuit and a discharge circuit; the second capacitor combination is connected with the discharging circuit through the selective switch; the second capacitor combination comprises a plurality of capacitors with different capacitance values; each capacitor corresponds to the occurrence degree of a micro short circuit; the time-delay circuit is connected with the discharging circuit through a transistor. According to the micro short circuit simulation circuit provided by the utility model, the interval of the micro short circuit which is simulated for the first time can be accurately controlled without adding an extra synchronization mechanism between the micro short circuit simulation circuit and a battery micro short circuit tester; and meanwhile, the micro-short-circuit occurrence frequency and intensity can be simulated so as to facilitate adjustment.

Description

Technical Field

[0001] The utility model relates to the technical field of batteries, and particularly relates to a simulation circuit for battery micro-short circuit. Background Art

[0002] Battery micro-short circuit means that inside the battery, especially between the positive and negative electrodes of a single battery cell, there are some tiny defects such as dust and scratches mixed in. These tiny defects will form a tiny conductive path inside the battery. Different from a completely short-circuited battery, a battery with a micro-short circuit can still be used normally in a short time. However, compared with a normal battery, the performance of a battery with a micro-short circuit will decline rapidly.

[0003] Currently, the calibration device of the traditional battery micro-short circuit detector mainly relies on Figure 1 the circuit system shown in the figure, where Cx is the analog test object; Cm is the capacitor combination; Rm is the discharge resistor; S is the switching device; HV is the high-voltage circuit. When a high voltage is applied across Cx, S is closed for a short time and then disconnected. Cm is suddenly connected to the high-voltage circuit from the zero state, thus simulating the phenomenon of battery micro-short circuit.

[0004] The charging process of the battery can be divided into a constant current stage (CC) and a constant voltage (CV) stage. The battery micro-short circuit detector should have the ability to distinguish the interval where the micro-short circuit occurs. Also, the difference in the equivalent capacitance values between batteries will result in different durations of the CC (CV) stage for different batteries. In the traditional scheme, there is no synchronization mechanism between the high-voltage circuit and the micro-short circuit simulation circuit, making it difficult to control the position of the first micro-short circuit occurrence and the occurrence frequency of micro-short circuits during the test, which is not conducive to calibrating the detection ability of the battery micro-short circuit tester as a standard signal source.

[0005] In summary, there is a need to design a simulation circuit for battery micro-short circuit to solve the above problems in the prior art. Summary of the Utility Model

[0006] To solve the above problems in the prior art, the utility model provides a simulation circuit for battery micro-short circuit, which solves the problems of the lack of a synchronization mechanism with the high-voltage circuit in the existing micro-short circuit simulation circuit, and the inability to control the position of the first micro-short circuit occurrence, the occurrence frequency, and the degree of micro-short circuits during the test.

[0007] To achieve the above purpose, the utility model adopts the following technical solutions:

[0008] A simulation circuit for battery micro-short circuit, comprising:

[0009] A master control circuit, which is connected in parallel at both ends of the instrument under test;

[0010] A frequency selection circuit, which is connected to the master control circuit through a first selection switch;

[0011] A micro short - circuit degree selection circuit, which is connected to the frequency selection circuit through a first inverter;

[0012] Wherein, the frequency selection circuit includes a first capacitor combination, the first capacitor combination includes a plurality of capacitors with different capacitance values, and each capacitor corresponds to a micro short - circuit occurrence frequency;

[0013] The micro short - circuit degree selection circuit includes a second capacitor combination, a delay circuit and a discharge circuit; the second capacitor combination is connected to the discharge circuit through a selection switch; the second capacitor combination includes a plurality of capacitors with different capacitance values; each capacitor corresponds to a micro short - circuit occurrence degree;

[0014] The delay circuit is connected to the discharge circuit through a transistor.

[0015] In some embodiments of the present invention, the master control circuit includes a voltage - dividing circuit and an enable switch circuit. Wherein, the voltage - dividing circuit is connected to the positive input terminal of an operational amplifier; the enable switch circuit is connected to the negative input terminal of the operational amplifier; the output terminal of the operational amplifier is connected to the selectable terminal of a first selection switch.

[0016] In some embodiments of the present invention, the enable switch circuit includes a second selection switch and a plurality of resistors; the fixed terminal of the second selection switch is connected to a power supply through a resistor; the selectable terminal of the second selection switch is connected to a resistor combination; wherein, each resistor in the resistor combination corresponds to the first occurrence time of the micro short - circuit phenomenon.

[0017] In some embodiments of the present invention, the frequency selection circuit includes a third selection switch connected to the first capacitor combination, the third selection switch is connected to a power supply through a charge - discharge circuit; the frequency selection circuit further includes a triode, and the base of the triode is connected to the output terminal of the first inverter.

[0018] In some embodiments of the present invention, when the voltage of the first capacitor combination is greater than 2 / 3Vcc, the triode conducts, and the first inverter outputs a low level.

[0019] In some embodiments of the present invention, in the frequency selection circuit, the input terminal of the first inverter is further connected to a NAND gate, a flip - flop and a first selectable switch; when the first selection switch is connected to the ground terminal, the NAND gate outputs a high level, and the inverter outputs a low level.

[0020] In some embodiments of the present utility model, the micro-short circuit degree selection circuit further includes a relay. One end of the coil of the relay is connected to the output end of the first inverter, and the other end is connected to the emitter of the first PNP transistor. One end of the mechanical switch of the relay is connected to the high voltage side, and the other end is connected to the discharge circuit and the selection end of the fourth selection switch.

[0021] In some embodiments of the present utility model, in the discharge circuit, the discharge resistor is connected to the source electrode of the transistor. The gate and drain of the transistor are connected in parallel with a resistor.

[0022] In some embodiments of the present utility model, the delay circuit further includes a second inverter. The output end of the second inverter is also connected to the first capacitor through a resistor and a diode. The first capacitor is connected to the anode of the diode. The anode of this diode is also connected to the input end of the second inverter. The output end of the second inverter is respectively connected to the base of the first PNP transistor and the gate of the transistor through diodes.

[0023] In some embodiments of the present utility model, the base of the first PNP transistor is also connected to the second capacitor and then grounded. The base of the first PNP transistor is also connected to the emitter of the second PNP transistor through a resistor. The base of the second PNP transistor is connected to the output end of the second inverter. The collector of the second PNP transistor is grounded.

[0024] The technical solution of the present utility model has the following technical effects compared with the prior art:

[0025] 1. The analog circuit of micro-short circuit provided by the present utility model can accurately control the interval of the first simulated micro-short circuit occurrence without adding an additional synchronization mechanism between the battery micro-short circuit tester.

[0026] 2. At the same time, the number of times and the severity of the micro-short circuit occurrence can be simulated for easy adjustment.

[0027] 3. The analog circuit of micro-short circuit provided by the present utility model does not need to rely on digital control chips such as MCUs, the circuit is reliable and easy to maintain. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0029] Figure 1 It is a schematic diagram of a battery micro-short circuit simulation circuit in the prior art.

[0030] Figure 2 Schematic diagram of the analog circuit for the micro-short circuit of the battery in the embodiment.

[0031] Figure 3 Schematic diagram of the voltages at some nodes in the master control circuit and the frequency selection circuit in the embodiment.

[0032] Figure 4 Schematic diagram of the voltages at some nodes in the micro-short circuit degree selection circuit in the embodiment. Detailed implementation manners

[0033] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0034] In the description of the present application, it should be understood that the orientation or positional relationships indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present application.

[0035] The terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise stated, the meaning of "a plurality" is two or more.

[0036] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0037] In the present utility model, unless otherwise clearly defined and limited, the first feature being "above" or "below" the second feature may include direct contact between the first and second features, or may include the first and second features not being in direct contact but in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the horizontal height of the first feature is higher than that of the second feature. The first feature being "below", "beneath" and "underneath" the second feature includes the first feature being directly below and obliquely below the second feature, or merely indicating that the horizontal height of the first feature is less than that of the second feature.

[0038] The following disclosure provides many different embodiments or examples for implementing different structures of the present utility model. To simplify the disclosure of the present utility model, components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present utility model. In addition, the present utility model may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between various embodiments and / or settings discussed.

[0039] Referring to Figure 2 as shown, an analog circuit for simulating a micro-short circuit of a battery includes:

[0040] A master control circuit, which is connected in parallel across both ends of the instrument under test;

[0041] A frequency selection circuit, which is connected to the master control circuit through a first selection switch S1;

[0042] A micro-short circuit degree selection circuit, which is connected to the frequency selection circuit through a first inverter NG50;

[0043] Wherein, the frequency selection circuit includes a first capacitor combination CM1, and the first capacitor combination CM1 includes a plurality of capacitors with different capacitance values, and each capacitor corresponds to a micro-short circuit occurrence frequency;

[0044] The micro-short circuit degree selection circuit includes a second capacitor combination CM2, a delay circuit and a discharge circuit; the second capacitor combination is connected to the discharge circuit through a selection switch; the second capacitor combination CM2 includes a plurality of capacitors with different capacitance values; each capacitor corresponds to a micro-short circuit occurrence degree;

[0045] The delay circuit is connected to the discharge circuit through a transistor V2.

[0046] In some embodiments of the present utility model, the master control circuit includes a voltage dividing circuit and an enable switch circuit. Among them, the voltage dividing circuit is connected to the non-inverting input terminal of the operational amplifier U1; the enable switch circuit is connected to the inverting input terminal of the operational amplifier U1; the output terminal of the operational amplifier U1 is connected to the selectable terminal of the first selection switch S1.

[0047] In some embodiments of the present utility model, the enable switch circuit includes a second selection switch S2 and a plurality of resistors; the fixed terminal of the second selection switch S2 is connected to the power supply through a resistor; the selectable terminal of the second selection switch S2 is connected to a resistor combination; among them, each resistor in the resistor combination corresponds to the time when the first micro-short circuit phenomenon occurs.

[0048] Specifically, continue to refer to Figure 1 as shown in

[0049] Resistors R10, R11, and R12 are connected in series and then in parallel with Cx to form a high-voltage voltage dividing branch. The voltage across resistor R12 is the voltage after voltage division. The end of resistor R12 connected to resistor R11 is connected to the non-inverting input terminal of operational amplifier U1; one end of resistor R20 is connected to VCC, and the other end is respectively connected to the fixed terminal of S2 and the inverting input terminal of operational amplifier U1; the selectable terminal of S2 is respectively connected to resistors R21 and R22, and the other ends of resistors R21 and R22 are grounded; the output terminal of operational amplifier U1 is connected to the selectable terminal of the first selection switch S1. The other selectable terminal of the first selection switch S1 is grounded, and the fixed terminal of the first selection switch S1 is connected to the input terminals of AN50 and AN53.

[0050] In some embodiments of the present utility model, the frequency selection circuit includes a third selection switch S3 connected to the first capacitor combination CM1. The third selection switch S3 is connected to the power supply through a charge and discharge circuit; the frequency selection circuit further includes a triode N1, and the base of the triode N1 is connected to the output terminal of the first inverter NG50.

[0051] When the voltage of the first capacitor combination CM1 is greater than 2 / 3Vcc, the triode N1 conducts, and the first inverter NG50 outputs a low level.

[0052] In some embodiments of the present utility model, in the frequency selection circuit, the input terminal of the first inverter NG50 is further connected to a flip-flop and a first selection switch S1 through a NAND gate; when the first selection switch S1 is connected to the ground terminal, the NAND gate outputs a high level, and the first inverter NG50 outputs a low level.

[0053] Specifically, one end of resistor R23 is connected to VCC and resistor R50, and the other end is respectively connected to resistor R24, the anode of diode D1 and the collector of triode N1; the other end of resistor R24 is connected to the cathode of diode D2; the cathode of diode D1 is connected to the anode of diode D2, the inverting input terminal of operational amplifier U50, the non-inverting input terminal of operational amplifier U51, and the fixed terminal of the third selection switch S3; the selectable terminal of the third selection switch S3 is connected to the first capacitor combination CM1, and the other end of the first capacitor combination CM1 is grounded; the other end of resistor R50 is connected to resistor R51 and the non-inverting input terminal of operational amplifier U50; the other end of resistor R51 is connected to resistor R52 and the non-inverting input terminal of operational amplifier U51; the other end of resistor R52 is connected to the emitter of N1 and grounded.

[0054] The NAND gate AN 50 and the NAND gate AN 51 form an RS flip-flop. The output terminal of operational amplifier U50 is connected to the input terminal of NAND gate AN 50, the output terminal of operational amplifier U51 is connected to the input terminal of NAND gate AN 51, the output terminal of the resistor RS flip-flop is connected to the other input terminal of NAND gate AN 53, and the output terminal of NAND gate AN 53 is connected to the input terminal of the first inverter NG50 and resistor R53; the other end of resistor R53 is connected to the base of N3.

[0055] In some embodiments of the present invention, the micro-short circuit degree selection circuit further includes a relay. One end of the coil of the relay is connected to the output terminal of the first inverter, and the other end is connected to the emitter of the first PNP triode; one end of the mechanical switch of the relay is connected to the high voltage side, and the other end is connected to the discharge circuit and the selectable terminal of the fourth selection switch.

[0056] In some embodiments of the present invention, in the discharge circuit, the discharge resistor is connected to the source of the transistor; the gate and drain of the transistor are connected in parallel with a resistor.

[0057] Specifically, the output terminal of the first inverter NG50 is connected to the control coil of the relay SW1 and resistor R36. The other end of resistor R36 is connected to the anode of diode D3. The other end of the control coil of the relay SW1 is connected to the emitter of the first PNP triode P3. The mechanical switch of the relay SW1 is in the off state in the reset state. One end of the relay SW1 is connected to the high voltage side of HV, and the other end is connected to resistor R32 and the fixed terminal of S4. The other end of resistor R32 is connected to the source of V2. Resistor R32 functions as the discharge resistor of the second capacitor combination CM2 to ensure that the selected capacitor is in the zero state before the second capacitor combination CM2 is connected to the high voltage. The 3 terminal of S4 is connected to the second capacitor combination CM2, and the other end of the second capacitor combination CM2 is grounded.

[0058] Since the incorporation of the capacitors in the second capacitor combination CM2 into high voltage is equivalent to a short circuit instantaneously, the current flowing through the relay SW1 is relatively large. Therefore, it is preferable to use a mechanical switch to implement this function. A semiconductor with a switching function will limit the current flow, which is not conducive to simulating the phenomenon of a micro short circuit.

[0059] In some embodiments of the present invention, a second inverter NG1 is further included in the delay circuit. The output terminal of the second inverter NG1 is also connected to the first capacitor C1 through a resistor and a diode; the first capacitor C1 is connected to the anode of the diode; the anode of this diode is also connected to the input terminal of the second inverter NG1. The output terminal of the second inverter NG1 is respectively connected to the base of the first PNP transistor and the gate of the transistor V2 through diodes.

[0060] In some embodiments of the present invention, the base of the first PNP transistor is also grounded after being connected to the second capacitor; the base of the first PNP transistor is also connected to the emitter of the second PNP transistor through a resistor; the base of the second PNP transistor is connected to the output terminal of the second inverter NG1; the collector of the second PNP transistor is grounded.

[0061] In some embodiments of the present invention, in the reset state, the output terminal of the first inverter NG50 outputs a low level, the output terminal of the second inverter NG1 outputs a high level, the voltage at the first capacitor C1 terminal is 0V, the second capacitor C2 is in a fully charged state, the first PNP transistor P3 and the second PNP transistor P4 are in a cut-off state, and the transistor V2 is in a conducting state.

[0062] Specifically, the cathode of the diode D3 is connected to the first capacitor C1, the resistor R31, and the input terminal of the second inverter NG1. The other ends of the first capacitor C1 and the resistor R31 are grounded. The output terminal of the second inverter NG1 is connected to the resistor R35, the anode of the diode D5, and the base of the second PNP transistor P4. The other end of the resistor R35 is connected to the anode of the diode D4. The cathode of the diode D4 is connected to the second capacitor C2, the resistor R34, and the base of the first PNP transistor P3. The other end of the second capacitor C2 is grounded. The other end of the resistor R34 is connected to the cathode of the diode D5, the emitter of the second PNP transistor P4, the resistor R33, and the gate of the transistor V2. The collector of the second PNP transistor P4, the drain of the transistor V2, and the other end of the resistor R33 are grounded.

[0063] Refer to Figure 2As shown, the function of the first selection switch S1 is the main control switch. When its selectable terminal is grounded, the NAND gate AN53 outputs a high level, the second inverter NG0 outputs a low level, the relay SW1 is in the reset state, the voltage across the capacitor terminal connected to the circuit in the first capacitor combination CM1 is 0, and the micro-capacitor in the second capacitor combination CM2 is in the zero state. After the fixed terminal of the first selection switch S1 is connected to the output terminal of the operational amplifier U1, when U HV *Resistance R12 / (Resistance R10 + Resistance R11 + Resistance R12) > VCC * Resistance R21 / (Resistance R21 + Resistance R22), the output voltage V of the first inverter NG50 1G is at a high level, and the 2nd and 3rd terminals of the S diode D conduct. Conventionally, the resistance values of the resistance R50, the resistance R51, and the resistance R52 are equal. When the voltage across the capacitor terminal connected to the circuit in the first capacitor combination CM1 rises to greater than 2 / 3Vcc, N1 conducts, the first inverter NG50 outputs a low level, the second capacitor combination CM2 and the resistance R3 form a loop, and the capacitor connected to the circuit in the second capacitor combination CM2 is discharged to 0V. When the voltage of the first capacitor combination CM1 drops to less than 1 / 3VCC, N1 cuts off, and the above process is repeated.

[0064] The capacitance value of the capacitor connected to the circuit in the first capacitor combination CM1 determines the switching frequency of the relay SW1 and the transistor V2. This frequency determines the frequency of occurrence of the simulated micro-short circuit during the period when a high voltage is applied across Cx. The larger the capacitance value, the lower the frequency of occurrence of the simulated micro-short circuit. The resistance connected to the selectable terminal of the second selection switch S2 determines the time point when the first simulated micro-short circuit occurs. The capacitance value of the capacitor connected to the circuit in the second capacitor combination CM2 determines the severity of the simulated micro-short circuit. The larger the capacitance value, the greater the severity of the simulated micro-short circuit.

[0065] To ensure the consistency of the severity of the micro-short circuit, it is necessary to ensure that the duration of each connection of the micro-capacitor in the second capacitor combination CM2 to the high voltage is strictly equal, and the amount of charge charged into the selected capacitor of the second capacitor combination CM2 after connecting to the high voltage is equal. Therefore, it is necessary to ensure that during its discharge period, its terminal voltage will drop to 0, and its discharge resistance R32 should preferably be a low-resistance and high-power resistor.

[0066] The charging and discharging timing of the second capacitor combination CM2 needs to be strictly controlled. The principle is to ensure that the transistor V2 can be turned on for discharge only after the second capacitor combination CM2 is disconnected from the high voltage, and the relay SW1 can be turned on only after the transistor V2 is turned off. The above is to ensure that the resistance R32 and the transistor V2 will not pass a large current for a long time. Due to the uncontrollable mechanical action delay of the mechanical relay, in order to ensure a certain dead time between the actions of the charging control switch and the discharging control switch of the second capacitor combination CM2, the transistor V2 should preferably be a fast-acting electronic switch.

[0067] Refer toFigure 4 As shown, to implement the above functions, a dedicated transistor V2 and a relay SW1 drive circuit need to be set. In the reset state, the first inverter NG50 outputs a low level, the second inverter NG1 outputs a high level, the voltage at the end of the first capacitor C1 is 0, the second capacitor C2 is in a fully charged state, the first PNP transistor P3 and the second PNP transistor P4 are cut off, and the transistor V2 is turned on. When the system starts, that is, at time k0, the first inverter NG50 outputs a high level, and the first capacitor C1 starts to charge. When it is charged to the switching threshold voltage of the second inverter NG1, that is, at time k1, the second inverter NG1 outputs a low level, the second PNP transistor P4 is turned on, the transistor V2 is cut off, and the second capacitor C2 starts to discharge along the path of the resistor R34 and the second PNP transistor P4. The voltage of the second capacitor C2 drops. At time k2, the output current of the collector of the first PNP transistor P3 reaches the operating threshold of the control coil of the relay SW1, and the relay SW1 is turned on. The second capacitor combination CM2 is connected to high voltage; at time k3, the output of the first inverter NG50 flips to a low level, the control coil of the relay SW1 loses power, and the second capacitor combination CM2 is disconnected from high voltage; the first capacitor C1 starts to discharge along the resistor R31. At time k4, the voltage of the first capacitor C1 drops to the switching threshold voltage of the second inverter NG1, the second inverter NG1 outputs a high level, the second PNP transistor P4 is cut off, the transistor V2 is turned on, and the second capacitor combination CM2 starts to discharge; at the same time, the second capacitor C2 starts to charge. After a period of time, the first PNP transistor P3 is cut off. After the second capacitor C2 is fully charged, the entire circuit returns to the reset state.

[0068] In the description of the above embodiments, the specific features, structures, materials, or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0069] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A battery micro-short circuit simulation circuit, characterized in that: include: The master control circuit is connected in parallel at both ends of the instrument under test; A frequency selection circuit connected to the master control circuit via a first selection switch; A micro-short circuit degree selection circuit, which is connected to the frequency selection circuit through a first inverter; Wherein, the frequency selection circuit includes a first capacitor combination, the first capacitor combination includes a plurality of capacitors with different capacitance values, each capacitor corresponding to a micro-short circuit occurrence frequency; The micro-short circuit degree selection circuit includes a second capacitor combination, a delay circuit and a discharge circuit; the second capacitor combination is connected to the discharge circuit through a selection switch; the second capacitor combination includes a plurality of capacitors with different capacitance values; each capacitor corresponds to a micro-short circuit occurrence degree; The delay circuit is connected to the discharge circuit through a transistor.

2. A battery micro-short circuit simulation circuit according to claim 1, characterized in that: The master control circuit includes a voltage divider circuit and an enable switch circuit, wherein the voltage divider circuit is connected to the non-inverting input terminal of the operational amplifier; the enable switch circuit is connected to the inverting input terminal of the operational amplifier; and the output terminal of the operational amplifier is connected to the selectable terminal of the first selection switch.

3. A battery micro-short circuit simulation circuit according to claim 2, characterized in that: The enabling switch circuit includes a second selection switch and multiple resistors; the fixed end of the second selection switch is connected to the power supply through a resistor; the selectable end of the second selection switch is connected to a resistor combination; wherein each resistor in the resistor combination corresponds to the time when the micro short circuit phenomenon first occurs.

4. A battery micro-short circuit simulation circuit according to claim 1, characterized in that: The frequency selection circuit includes a third selection switch connected to the first capacitor combination, and the third selection switch is connected to the power supply through the charging and discharging circuit; the frequency selection circuit also includes a transistor, and the base of the transistor is connected to the output end of the first inverter.

5. A battery micro-short circuit simulation circuit according to claim 4, characterized in that: When the voltage of the first capacitor combination is greater than 2 / 3 Vcc, the transistor is turned on, and the first inverter outputs a low level.

6. A battery micro-short circuit simulation circuit according to claim 1, characterized in that: In the frequency selection circuit, the input end of the first inverter is also connected to the trigger and the first selectable switch through a NAND gate; when the first selector switch is connected to the ground end, the NAND gate outputs a high level and the inverter outputs a low level.

7. A battery micro-short circuit simulation circuit according to claim 1, characterized in that: The micro-short circuit degree selection circuit also includes a relay, one end of the coil of the relay is connected to the output end of the first inverter, and the other end is connected to the emitter of the first PNP transistor; one end of the mechanical switch of the relay is connected to the high voltage side, and the other end is connected to the discharge circuit and the selection end of the fourth selection switch.

8. A battery micro-short circuit simulation circuit according to claim 1, characterized in that: In the discharge circuit, the discharge resistor is connected to the source of the transistor; the gate and drain of the transistor are connected in parallel with the resistor.

9. A battery micro-short circuit simulation circuit according to claim 1, characterized in that: The delay circuit also includes a second inverter, the output end of which is also connected to the first capacitor through a resistor and a diode; the first capacitor is connected to the anode of the diode; the anode of the diode is also connected to the input end of the second inverter, and the output end of the second inverter is respectively connected to the base of the first PNP transistor and the gate of the transistor through a diode.

10. A battery micro-short circuit simulation circuit according to claim 9, characterized in that: The base of the first PNP transistor is also connected to the second capacitor and then grounded; the base of the first PNP transistor is also connected to the emitter of the second PNP transistor through a resistor; the base of the second PNP transistor is connected to the output end of the second inverter; and the collector of the second PNP transistor is grounded.

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