Multi-channel signal acquisition system

Abstract

The utility model relates to the technical field of electronic circuits, and discloses a multichannel signal acquisition system. The system comprises a processor and a plurality of signal acquisition modules. The processor is configured with a general input / output interface and a serial peripheral interface; each signal acquisition module is respectively provided with a dial-up module, is connected with the universal input / output interface and the serial peripheral interface, accesses dial-up signals generated by the dial-up module, accesses control signals output by the processor through the universal input / output interface, and is started when the control signals and the corresponding dial-up signals are accessed; and serial interaction with the processor is carried out through the serial peripheral interface during starting. According to the embodiment of the invention, the complexity of signal chip selection operation can be reduced, and a processor can perform multichannel signal acquisition by using a small number of peripheral interfaces.

Description

Technical Field

[0001] This application relates to the technical field of electronic circuits, and particularly to a multi-channel signal acquisition system. Background Art

[0002] When using a sensor to acquire signals, an analog-to-digital converter is required to convert the analog signals acquired by the sensor into digital signals so that the signals acquired by the sensor can be processed by a processor.

[0003] In related technologies, the number of peripheral interfaces configured by a processor is limited, and some processors are insufficient to match large-scale data acquisition or monitor multiple signal sources simultaneously. To solve this technical problem, corresponding signal chip selection operations are added, enabling the processor to perform multi-channel signal acquisition with a small number of peripheral interfaces.

[0004] However, the current signal chip selection operations rely on complex hardware switches or are controlled by software, which may require additional setup and debugging steps, making the system configuration more complex and difficult to operate. Summary of the Utility Model

[0005] The purpose of this application is to provide a multi-channel signal acquisition system that can reduce the complexity of signal chip selection operations, enabling the processor to perform multi-channel signal acquisition with a small number of peripheral interfaces.

[0006] An embodiment of this application provides a multi-channel signal acquisition system, including:

[0007] A processor configured with general-purpose input / output interfaces and serial peripheral interfaces; and

[0008] A plurality of signal acquisition modules, each configured with a DIP switch module, connected to the general-purpose input / output interfaces and the serial peripheral interfaces, accessing the DIP signals generated by the DIP switch module and the control signals output by the processor through the general-purpose input / output interfaces, starting when the control signals and the corresponding DIP signals are accessed, and serially interacting with the processor through the serial peripheral interfaces when starting.

[0009] In some embodiments, the DIP switch module includes a DIP switch and a plurality of opto-isolation circuits; the DIP switch, the opto-isolation circuits, and the signal acquisition module are connected in sequence, and when the DIP switch is in the corresponding gear position, the corresponding opto-isolation circuit is powered on to generate the corresponding DIP signal.

[0010] In some embodiments, the signal acquisition module includes a decoding sub-module, a switching sub-module, and a signal acquisition sub-module;

[0011] The decoding sub-module is connected to the general-purpose input / output interface, accesses the control signal through the general-purpose input / output interface, generates a corresponding decoding signal and outputs it;

[0012] The switch sub-module is connected to the decoding sub-module and the DIP switch module, accesses the decoding signal and the DIP switch signal generated by the DIP switch module, generates a corresponding switch signal and outputs it;

[0013] The signal acquisition sub-module is connected to the serial peripheral interface and the switch sub-module, accesses the switch signal to start or take offline, and serially interacts with the processor through the serial peripheral interface when starting.

[0014] In some embodiments, the signal acquisition sub-module includes a trigger, a digital isolator, an analog-to-digital converter, and several sensors;

[0015] The analog-to-digital converter is connected to each of the sensors;

[0016] The trigger is connected to the slave select line of the serial peripheral interface and the switch sub-module, uses the switch signal as the clock signal and the signal output by the slave select line as the enable signal, and outputs a corresponding trigger signal;

[0017] The digital isolator is connected to the trigger, the analog-to-digital converter, the serial clock line, the host input line, and the host output line of the serial peripheral interface, accesses the trigger signal to start or take offline the analog-to-digital converter, and enables the analog-to-digital converter to serially interact with the processor when the analog-to-digital converter starts.

[0018] In some embodiments, the trigger is a 74HCT374 series chip.

[0019] In some embodiments, the digital isolator is an NSi8241W1 series chip.

[0020] In some embodiments, the analog-to-digital converter is an AD7689 series chip.

[0021] In some embodiments, the decoding sub-module is an SN74HC138D series chip.

[0022] In some embodiments, the switch sub-module is a CD74HC4067M series chip.

[0023] Advantages of the present application: The general input / output interfaces and serial peripheral interfaces of the processor are shared by each signal acquisition module. Each signal acquisition module is respectively configured with a DIP switch module. The signal acquisition module starts when the control signal and the corresponding DIP switch signal are accessed, and serially interacts with the processor through the serial peripheral interface at startup. Since each signal acquisition module is respectively configured with a DIP switch module, each signal acquisition module starts when receiving the corresponding control signal and the corresponding DIP switch signal. When the processor outputs the control signal to start the signal acquisition module, it is also necessary for the DIP switch module corresponding to the signal acquisition module to generate the DIP switch signal to start the current signal acquisition module before the signal acquisition module can be started. There is no need to allocate respective peripheral interfaces for each signal acquisition module. Only one set of general input / output interfaces and one set of serial peripheral interfaces are needed to control multiple groups of signal acquisition modules, so as to reduce the complexity of signal chip selection operation and enable the processor to perform multi-channel signal acquisition with a small number of peripheral interfaces. Description of the Drawings

[0024] Figure 1 FIG. is a schematic structural diagram of a multi-channel signal acquisition system provided by an embodiment of the present application.

[0025] Figure 2 FIG. is a schematic structural diagram of a DIP switch module provided by an embodiment of the present application.

[0026] Figure 3 FIG. is a schematic structural diagram of a signal acquisition module provided by an embodiment of the present application. Detailed Embodiments

[0027] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0029] Refer to Figure 1, in one embodiment, the multi-channel signal acquisition system includes a processor 100 and a number of signal acquisition modules 200. Among them, the processor 100 is configured with a general-purpose input / output interface (a group of four general-purpose input / output interfaces in total, namely GPIO1 to GPIO4, the same below) and a serial peripheral interface (with a slave select line SPI_CS, a serial clock line SPI_SCLK, a host input line SPI_MISO, and a host output line SPI_MISI, the same below). Each signal acquisition module 200 is respectively configured with a DIP switch module 300. Each signal acquisition module 200 is connected to the general-purpose input / output interface and the serial peripheral interface. The signal acquisition module 200 accesses the DIP switch signal generated by the DIP switch module 300 and the control signal output by the processor 100 through the general-purpose input / output interface, starts when accessing the control signal and the corresponding DIP switch signal, and serially interacts with the processor 100 through the serial peripheral interface when starting.

[0030] In this embodiment, the multi-channel signal acquisition system is composed of one processor 100 and eight signal acquisition modules 200. Each signal acquisition module 200 has four acquisition channels respectively. Each signal acquisition module 200 is respectively configured with a DIP switch module 300, that is, the number of DIP switch modules 300 is also eight. Each signal acquisition module 200 is respectively connected to the general-purpose input / output interface of the processor 100. The processor 100 outputs control signals for starting or shutting down through the general-purpose input / output interface. It should be noted that in other embodiments, the number of signal acquisition modules 200 can also be other numbers, such as one, two, or three, etc., which are not limited in this application.

[0031] In actual application, the processor 100 receives external control instructions to output control signals through the general-purpose input / output interface. The DIP switch module 300 generates DIP switch signals according to its current gear state. The signal acquisition module 200 accesses the DIP switch signals generated by the DIP switch module 300 and the control signals output by the processor 100, starts when receiving the corresponding control signals and the corresponding DIP switch signals, performs sensing acquisition when starting, and serially interacts with the processor 100 through the serial peripheral interface to transmit the acquired sensing signals to the processor 100. Among them, the signal acquisition module 200 starts when receiving the corresponding control signals and the corresponding DIP switch signals. On the one hand, the processor 100 outputs a control signal to start the signal acquisition module 200 through the general-purpose input / output interface, and each signal acquisition module 200 obtains this control signal through the general-purpose input / output interface. On the other hand, the DIP switch module 300 configured in each signal acquisition module 200 generates a DIP switch signal to start the current signal acquisition module 200. When the signal acquisition module 200 receives the control signal to start the signal acquisition module 200 and the DIP switch signal to start the current signal acquisition module 200, the signal acquisition module 200 starts and performs sensing acquisition. Conversely, the signal acquisition module 200 shuts down.

[0032] It can be understood that since each signal acquisition module is respectively configured with a DIP switch module 300, each signal acquisition module is activated when receiving the corresponding control signal and the corresponding DIP switch signal. That is to say, when the processor 100 outputs the control signal to activate the signal acquisition module 200, it is also necessary for the DIP switch module 300 corresponding to the signal acquisition module 200 to generate the DIP switch signal to activate the current signal acquisition module 200. It is not necessary to allocate respective peripheral interfaces for each signal acquisition module. Only by using the same set of general-purpose input / output interfaces and the same set of serial peripheral interfaces can the control of multiple groups of signal acquisition modules 200 be realized, so as to reduce the complexity of signal chip selection operation, enabling the processor 100 to perform multi-channel signal acquisition with a small number of peripheral interfaces.

[0033] Referring to Figure 1 and Figure 2 , in a specific embodiment, the DIP switch module 300 includes a DIP switch 310 and a plurality of opto-isolation circuits 320. Among them, the DIP switch 310, the opto-isolation circuit 320, and the signal acquisition module 200 are connected in sequence. When the DIP switch 310 is in the corresponding gear position, the corresponding opto-isolation circuit 320 is powered on to generate the corresponding DIP switch signal.

[0034] Specifically, the number of gears of the DIP switch 310 is greater than or equal to the number of signal acquisition modules 200. The DIP switch 310 is connected to a DC voltage. When the DIP switch 310 is turned to the corresponding gear, one or more corresponding opto-isolation circuits 320 are triggered to turn on, so as to output the corresponding DIP signal to the signal acquisition module 200. For example, the DIP module 300 may be configured with four groups of opto-isolation circuits 320, and the number of gears of the DIP switch 310 is eight. One group of signal acquisition modules 200 may be configured to start when the DIP switch 310 is turned to the first gear and the processor 100 outputs a control signal to start the signal acquisition module 200. The triggering relationship between the DIP switch 310 and the opto-isolation circuit 320 may be that when the DIP switch 310 is turned to the first gear, the first group of opto-isolation circuits 320 are turned on while the other opto-isolation circuits 320 are turned off; when the DIP switch 310 is turned to the second gear, the second group of opto-isolation circuits 320 are turned on while the other opto-isolation circuits 320 are turned off; when the DIP switch 310 is turned to the third gear, the third group of opto-isolation circuits 320 are turned on while the other opto-isolation circuits 320 are turned off; when the DIP switch 310 is turned to the fourth gear, the fourth group of opto-isolation circuits 320 are turned on while the other opto-isolation circuits 320 are turned off; when the DIP switch 310 is turned to the fifth gear, the first and second groups of opto-isolation circuits 320 are turned on while the other opto-isolation circuits 320 are turned off; when the DIP switch 310 is turned to the sixth gear, the first and third groups of opto-isolation circuits 320 are turned on while the other opto-isolation circuits 320 are turned off; when the DIP switch 310 is turned to the seventh gear, the first and fourth groups of opto-isolation circuits 320 are turned on while the other opto-isolation circuits 320 are turned off; when the DIP switch 310 is turned to the eighth gear, the second and third groups of opto-isolation circuits 320 are turned on while the other opto-isolation circuits 320 are turned off.

[0035] Referring in combination to Figure 1 and Figure 3 In a specific embodiment, the signal acquisition module 200 includes a decoding sub-module 210, a switching sub-module 220, and a signal acquisition sub-module 230. Among them, the decoding sub-module 210 is connected to the general-purpose input / output interface. The decoding sub-module 210 accesses the control signal through the general-purpose input / output interface, generates the corresponding decoding signal and outputs it. The switching sub-module 220 is connected to the decoding sub-module 210 and the DIP module 300. The switching sub-module 220 accesses the decoding signal and the DIP signal generated by the DIP module 300, generates the corresponding switching signal and outputs it. The signal acquisition sub-module 230 is connected to the serial peripheral interface and the switching sub-module 220. The signal acquisition sub-module 230 accesses the switching signal to start or go offline, and serially interacts with the processor 100 through the serial peripheral interface when starting.

[0036] Specifically, the decoding submodule 210 accesses the control signal through the general input and output interface and decodes the control signal, generates a corresponding decoding signal and outputs it to the switch submodule 220. The switch submodule 220 accesses the decoding signal and the dial signal generated by the dial module 300. When the control signal corresponding to the decoding signal is the control signal of the start signal acquisition module 200 and the dial signal of the current signal acquisition module 200 is accessed, the switch submodule 220 outputs the switch signal of starting the signal acquisition submodule 230 to the signal acquisition submodule 230, so that the signal acquisition submodule 230 is started. Otherwise, the switch signal of taking the signal acquisition submodule 230 offline is output to the signal acquisition submodule 230. The started signal acquisition submodule 230 performs sensor acquisition and interacts serially with the processor 100 through the serial peripheral interface.

[0037] More specifically, the signal acquisition submodule 230 includes a trigger 231, a digital isolator 232, an analog-to-digital converter 233, and a plurality of sensors 234. The analog-to-digital converter 233 is connected to each sensor 234, the trigger 231 is connected to the slave selection line SPI_CS of the serial peripheral interface and the switch submodule 220, the trigger 231 uses the switch signal as the clock signal and the signal output from the slave selection line SPI_CS as the enable signal, and outputs the corresponding trigger signal, the digital isolator 232 is connected to the trigger 231, the analog-to-digital converter 233, and the serial clock line SPI_SCLK, the host input line SPI_MISO, and the host output line SPI_MISI of the serial peripheral interface, the digital isolator 232 receives the trigger signal to start or shut down the analog-to-digital converter 233, and when the analog-to-digital converter 233 is started, the analog-to-digital converter 233 is serially interacted with the processor 100.

[0038] Specifically, when the switch submodule 220 outputs a switch signal to start the signal acquisition submodule 230, the trigger 231 generates a corresponding trigger signal according to the switch signal and the signal output by the slave selection line SPI_CS, so that the digital isolator 232 performs serial interaction with the processor 100 through the trigger 231 and the serial clock line SPI_SCLK, the host input line SPI_MISO and the host output line SPI_MISI of the serial peripheral interface. Among them, the trigger signal includes the signal output by the slave selection line SPI_CS, and the digital isolator 232 triggers one or more groups of channels of the analog-to-digital converter 233 to start according to the trigger signal to obtain the corresponding sensor signal of one or more sensors 234 and perform analog-to-digital conversion. The digital isolator 232 obtains the digital signal converted by the digital simulator and transmits it back to the processor 100 through serial interaction.

[0039] In the above embodiment, the trigger 231 is a 74HCT374 series chip.

[0040] In the above embodiments, the digital isolator 232 is an NSi8241W1 series chip.

[0041] In the above embodiments, the analog-to-digital converter 233 is an AD7689 series chip.

[0042] In the above embodiments, the decoding sub-module 210 is an SN74HC138D series chip.

[0043] In the above embodiments, the switch sub-module 220 is a CD74HC4067M series chip.

[0044] In summary, for the multi-channel signal acquisition system provided by the embodiments of the present application, each signal acquisition module shares the general input / output interface and the serial peripheral interface of the processor. Each signal acquisition module is respectively configured with a DIP switch module. The signal acquisition module is started when the control signal and the corresponding DIP switch signal are connected, and when starting, it serially interacts with the processor through the serial peripheral interface. Since each signal acquisition module is respectively configured with a DIP switch module, and each signal acquisition module is started when receiving the corresponding control signal and the corresponding DIP switch signal. When the processor outputs the control signal to start the signal acquisition module, it is also necessary for the DIP switch module corresponding to the signal acquisition module to generate the DIP switch signal to start the current signal acquisition module, so as to start the signal acquisition module. There is no need to allocate respective peripheral interfaces for each signal acquisition module. Only by using the same set of general input / output interfaces and the same set of serial peripheral interfaces, the control of multiple groups of signal acquisition modules can be realized, so as to reduce the complexity of the signal chip selection operation, and enable the processor to perform multi-channel signal acquisition with a small number of peripheral interfaces.

[0045] The preferred embodiments of the embodiments of the present application have been described above with reference to the accompanying drawings. However, this does not limit the scope of the rights of the embodiments of the present application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall fall within the scope of the rights of the embodiments of the present application.

Claims

1. A multi-channel signal acquisition system, characterized in that: include: A processor configured with a general purpose input and output interface and a serial peripheral interface; as well as Several signal acquisition modules are respectively configured with a dial module, connected to the universal input and output interface and the serial peripheral interface, accessing the dial signal generated by the dial module and accessing the control signal output by the processor through the universal input and output interface, starting when accessing the control signal and the corresponding dial signal, and interacting serially with the processor through the serial peripheral interface when starting.

2. The multi-channel signal acquisition system according to claim 1, characterized in that: The dial module includes a dialer and several optocoupler isolation circuits; the dialer, the optocoupler isolation circuit and the signal acquisition module are connected in sequence, and when the dialer is in a corresponding gear position, the corresponding optocoupler isolation circuit is powered on to generate the corresponding dial signal.

3. The multi-channel signal acquisition system according to claim 1, characterized in that: The signal acquisition module includes a decoding submodule, a switch submodule and a signal acquisition submodule; The decoding submodule is connected to the universal input / output interface, receives the control signal through the universal input / output interface, generates a corresponding decoding signal and outputs it; The switch submodule is connected to the decoding submodule and the dial module, receives the decoding signal and the dial signal generated by the dial module, generates a corresponding switch signal and outputs it; The signal acquisition submodule is connected to the serial peripheral interface and the switch submodule, receives the switch signal to start or go offline, and interacts serially with the processor through the serial peripheral interface during startup.

4. The multi-channel signal acquisition system according to claim 3, characterized in that: The signal acquisition submodule includes a trigger, a digital isolator, an analog-to-digital converter and several sensors; The analog-to-digital converter is connected to each of the sensors; The trigger is connected to the slave selection line of the serial peripheral interface and the switch submodule, uses the switch signal as a clock signal and the signal output from the slave selection line as an enable signal, and outputs a corresponding trigger signal; The digital isolator is connected to the trigger, the analog-to-digital converter and the serial clock line, the host input line and the host output line of the serial peripheral interface, and receives the trigger signal to start or shut down the analog-to-digital converter, so that the analog-to-digital converter and the processor interact serially when the analog-to-digital converter is started.

5. The multi-channel signal acquisition system according to claim 4, characterized in that: The trigger is a 74HCT374 series chip.

6. The multi-channel signal acquisition system according to claim 4, characterized in that: The digital isolator is a NSi8241W1 series chip.

7. The multi-channel signal acquisition system according to claim 4, characterized in that: The analog-to-digital converter is an AD7689 series chip.

8. The multi-channel signal acquisition system according to claim 3, characterized in that: The decoding submodule is a SN74HC138D series chip.

9. The multi-channel signal acquisition system according to claim 3, characterized in that: The switch submodule is a CD74HC4067M series chip.

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