Charge pump circuit with wide working power supply range and chip

Abstract

The utility model provides a charge pump circuit with a wide working power supply range and a chip. The circuit is realized through a plurality of charge pump cores which are connected in parallel, each charge pump core comprises multiple stages of charge pump circuit modules, capacitors can be integrated in a chip, and the circuit can stably work under low power supply voltage. The control signal input end of the charge pump core receives a plurality of phase difference control signals, so that the at least two charge pump cores can output the load at the same time, thereby providing stable output voltage and enhancing loading capacity. According to the utility model, through the design of the charge pump nuclear circuit, the dependence on external capacitance is reduced, the overall cost is reduced, and meanwhile, through the design of the multi-stage charge pump circuit module and the optimization of the phase difference of control signals, the problem that the output voltage of the charge pump is unstable under low power supply voltage in the prior art is solved; and the reliability and the stability of the chip are obviously improved.

Description

Technical Field

[0001] The utility model relates to the field of power circuits, in particular to a charge pump circuit and a chip with a wide working power supply range. Background Art

[0002] In the field of power circuits, lower chip internal resistance is one of the goals pursued by designers. In order to solve this problem, the current design of the drive circuit has gradually changed from the P-channel upper bridge arm plus the N-channel lower bridge arm to the configuration of dual N-channel power tubes. Because the electron mobility is higher than the hole mobility, the design of the dual N-channel power tube has a lower layout area than the design of the P-channel upper bridge arm plus the N-channel lower bridge arm under the same chip internal resistance, thereby significantly reducing the manufacturing cost of the chip.

[0003] However, the current dual N-channel power tube design on the market has the following two disadvantages:

[0004] First, the designers of dual N-channel power tubes currently on the market often need to use capacitors outside the chip to meet design requirements. Although this solution reduces the manufacturing cost of the chip, the final cost increases due to the use of capacitors outside the chip. At the same time, the need for additional capacitors will increase the difficulty of chip application design.

[0005] Second, the current dual N-channel power tube design schemes on the market often use the power supply voltage as the charging voltage of the charge pump, and the charge pump is generally a two-stage charge pump. However, when the power supply voltage is low, the output voltage of the charge pump is not easy to reach the theoretical design value due to the influence of the switch threshold voltage, parasitic effects, switch losses and charge losses, resulting in excessive internal resistance of the N-channel power tube, which makes the chip fail. Utility Model Content

[0006] The utility model provides a charge pump circuit in a chip with a wide operating power supply range. The module can integrate capacitors in the chip and can work stably under low power supply voltage. To achieve the purpose of the utility model, the utility model adopts the following scheme: A charge pump circuit with a wide operating power supply range, characterized in that it includes:

[0007] A plurality of charge pump cores are provided in each charge pump core, wherein a multi-stage charge pump circuit module is provided, wherein the multi-stage charge pump circuit module includes a plurality of charge pump charge and discharge enable switches to realize the switching of the charging circuit or the boost circuit of the multi-stage charge pump circuit module; each charge pump core is provided with a charge pump charge and discharge enable switch control module to control the switching of the charge pump charge and discharge enable switches in the corresponding charge pump core; the output ends of each charge pump core are connected in common as the output ends of the charge pump circuit with a wide working power supply range, so that at least two charge pump cores can output to the load.

[0008] Further, the number of the charge pump cores is not less than four; optionally, the number of the charge pump cores is four.

[0009] Further, the charge pump core includes a multi-stage charge pump circuit module and a charge and discharge enabling control module;

[0010] The multi-stage charge pump circuit module includes a first capacitor, a second capacitor, a third capacitor, a first diode, and a charge and discharge enabling switch; the charge and discharge enabling switch includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch;

[0011] The input ends of the third switch, the fifth switch, the seventh switch, and the eighth switch serve as the first power reference end of the charge pump core and are connected to the positive power supply;

[0012] The output end of the third switch is connected to the input end of the first switch and one end of the first capacitor; the other end of the first capacitor is connected to the input end of the fourth switch, the output end of the fifth switch, and the output end of the sixth switch; the output end of the first switch is connected to one end of the second capacitor and the input end of the sixth switch;

[0013] The output end of the seventh switch is connected to the other end of the second capacitor and the input end of the second switch; the output end of the second switch is connected to one end of the third capacitor and the input end of the sixth switch;

[0014] The output end of the eighth switch is connected to the other end of the third capacitor and the positive pole of the first diode; the negative pole of the first diode is the output end of the charge pump core;

[0015] The output end of the fourth switch serves as the second power reference end of the charge pump core and is connected to the negative power supply;

[0016] The input end of the charge and discharge enabling switch control module is the control signal input end of the charge pump core; the charging control end of the charge and discharge enabling switch control end is used to switch the charging circuit of the charge pump core, and the control ends of the third switch, the fourth switch, the sixth switch, the seventh switch, and the eighth switch are commonly connected as the charging control end of the charge pump core; the boosting control end of the charge and discharge enabling switch control end is used to switch the boosting circuit of the charge pump core, and the boosting control end is connected to the control ends of the first switch, the second switch, and the fifth switch.

[0017] Further, the charge and discharge enabling switch control module includes a first inverter and a second inverter; the input end of the first inverter is the input end of the charge and discharge enabling switch control module, and the output end is connected to the input end of the second inverter and serves as the charging control end of the charge and discharge enabling switch control module; the output end of the second inverter is the boosting control end of the charge and discharge enabling switch control module.

[0018] Optionally, the charge and discharge enable switches are all N-channel transistors, and the threshold voltage of the N-channel transistors does not exceed the high-level reference terminal voltage of the charge pump core; the control terminal of the charge and discharge enable switch is the gate of the N-channel transistor.

[0019] Furthermore, the chip-internal charge pump circuit with a wide operating power supply range provided by the present invention further includes a reference voltage circuit;

[0020] The reference voltage circuit includes a first resistor, a second diode, a first transistor, a current source, and a charge pump core;

[0021] The first power supply reference terminal of the charge pump core, the positive electrode of the second diode, and one end of the first resistor are connected to a high level;

[0022] The other end of the first resistor is connected to the gate of the first transistor and the negative electrode of the current source;

[0023] The positive electrode of the current source is grounded;

[0024] The second power supply reference terminal of the charge pump core is connected to the source of the first transistor. The control signal input terminal of the charge pump core is used to receive a control signal, and the output terminal of the charge pump circuit is connected to the negative electrode of the second diode;

[0025] The first transistor is a P-type MOSFET, and the drain of the first transistor is grounded.

[0026] The present invention further includes a chip integrated with the charge pump circuit with a wide operating power supply range.

[0027] By integrating capacitors in the chip, the present invention reduces the dependence on external capacitors and lowers the overall cost; the multi-stage charge pump circuit module design and the phase difference configuration of the control signal improve the stability of the output voltage; the design of the reference voltage circuit enables the charge pump to operate stably at a low power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 The connection schematic diagram of the charge pump core according to the embodiment of the present invention is as shown;

[0029] Figure 2 The circuit diagram of the charge pump core according to the embodiment of the present invention;

[0030] Figure 3 The circuit diagram of the charge pump charging state according to the embodiment of the present invention;

[0031] Figure 4 The circuit diagram of the charge pump boosting state according to the embodiment of the present invention;

[0032] Figure 5Structural diagram of the boost circuit according to the embodiment of the present utility model;

[0033] Figure 6 Schematic diagram of the charge pump control signal with a 90° phase difference according to the embodiment of the present utility model. Detailed implementation manners

[0034] The embodiments of the present utility model will be described in detail below. The examples of the embodiments are shown in the drawings. The example implementation manners can be implemented in various forms and should not be construed as limited to the examples described herein. On the contrary, these implementation manners are provided to make the present utility model more comprehensive and complete, and to fully convey the concept of the example implementation manners to those skilled in the art. The same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present invention and should not be construed as a limitation of the present invention.

[0035] In the description of the present utility model, it should be noted that, unless otherwise clearly defined and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0036] In this embodiment, the number of charge pump cores is not less than four, and the phase difference of the control signals applied to the charge pump cores is adjusted according to the number of charge pump cores. When the number of charge pump cores is N, the phase difference of the control signals is 360° / N, so that at least two charge pump cores can output to the load simultaneously.

[0037] Since only small capacitors with a capacitance range of 10 pF - 1000 pF can be fabricated in the chip of the present utility model, multiple charge pump cores need to be connected in parallel in the chip to output VCP to provide sufficient load-carrying capacity. In this embodiment, a charge pump circuit with a wide operating power supply range is composed of four identical charge pump cores CP[0] - CP[3] connected in parallel, as Figure 1 shown, the control signal input ends of the charge pump cores are sequentially connected to four control signals CTRL_CP[3:0] with a phase difference of 90° from each other. The phase difference of the control signals is as Figure 6As shown, the phase difference between control signals CTRL_CP[3] and CTRL_CP[2] is 90 degrees; the phase difference between control signals CTRL_CP[2] and CTRL_CP[1] is 90 degrees; the phase difference between control signals CTRL_CP[1] and CTRL_CP[0] is 90 degrees; the phase difference between control signals CTRL_CP[0] and CTRL_CP[3] is 90 degrees. By inputting four control signals with a 90° phase difference from each other, at least two charge pump cores can stably output to the load simultaneously, improving the load-carrying capacity of the chip.

[0038] In this embodiment, the control signal realizes the switching between the charging state and the boosting state of the charge pump core by controlling the charge and discharge enable switch in the charge pump core. In this embodiment, the implementation manner of the switch is an N-type MOSFET. When the gate of the NMOS is at a high level, the switch is turned on; when the gate of the NMOS is at a low level, the switch is turned off. Since the NMOS needs a gate-source voltage greater than its threshold voltage to conduct, the above high level needs to be greater than the value of the NMOS threshold voltage. Therefore, when the reference high level VS_CP of the charge pump core is equal to the power supply voltage, the control terminal voltage (control signals CTRL_CP[3:0]) of the switch needs to be greater than the power supply voltage to conduct.

[0039] In this embodiment, the circuit diagram of the charge pump core is as Figure 2 shown. The circuit structures of the four charge pump cores are exactly the same. Therefore, taking the charge pump core CP[3] as an example, the charge pump core CP[3] includes a multi-stage charge pump circuit module and a charge and discharge enable control module. The multi-stage charge pump circuit module includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a first diode D1, and a charge and discharge enable switch; the charge and discharge enable switch includes a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a fifth switch K5, a sixth switch K6, a seventh switch K7, and an eighth switch K8; the charge and discharge enable switch control module includes a first inverter INV1 and a second inverter INV2.

[0040] When the control signal CTRL_CP[3] is at a low level, as Figure 3As shown, the control signal CTRL_CP[3] passes through the first inverter INV1 to obtain a high-level output. The high-level output of the first inverter INV1 passes through the second inverter INV2 to obtain a low-level output. The high-level output of the first inverter INV1 turns on switches K3, K4, K6, K7, and K8. The low-level output of the second inverter INV2 turns off switches K1, K2, and K5. At this time, one end of the first capacitor C1, the second capacitor C2, and the third capacitor C3 in the charge pump core is connected to the positive power supply, and the other end of the above capacitors is connected to the negative power supply. The charge pump core is in a charging state. The positive voltage of the first capacitor C1, the second capacitor C2, and the third capacitor C3 is VC_CP, and the negative voltage is VS_CP. The voltage difference of the capacitor can be expressed as VS_CP - VC_CP.

[0041] When the control signal CTRL_CP[3] is at a high level, as Figure 3 shown, the control signal CTRL_CP[3] passes through the first inverter INV1 to obtain a low-level output. The low-level output of the first inverter INV1 turns off switches K3, K4, K6, K7, and K8. The low-level output obtained by the first inverter INV1 passes through the second inverter INV2 to obtain a high-level output, which turns on switches K1, K2, and K5. At this time, the first capacitor C1, the second capacitor C2, and the third capacitor C3 in the charge pump core are connected in series. The positive electrode of the first capacitor C1 is connected to the positive power supply, the negative electrode of the third capacitor C3 is connected to the positive electrode of the first diode D1, and the negative electrode of the first diode D1 is the output terminal of the charge pump core. Since the voltage difference across the capacitor does not change suddenly, the positive voltage of the first capacitor C1 is VS_CP, the negative voltage of the first capacitor C1 is VS_CP + VS_CP - VC_CP, and the voltage difference of the first capacitor C1 is VS_CP - VC_CP. Similarly, the positive voltage of the second capacitor C2 is obtained as VS_CP + VS_CP - VC_CP, the negative voltage is VS_CP + 2(VS_CP - VC_CP), and the voltage difference of the second capacitor C2 is VS_CP - VC_CP. Similarly, the positive voltage of the third capacitor C3 is obtained as VS_CP + 2(VS_CP - VC_CP), the negative voltage is VS_CP + 3(VS_CP - VC_CP), and the voltage difference of the third capacitor C3 is VS_CP - VC_CP. The negative voltage of the third capacitor C3 is used as the output VO_CP of the charge pump core after passing through the second diode D2. Therefore, the output voltage of the charge pump core is:

[0042] VO_CP = VS_CP + 3(VS_CP - VC_CP) - Vdio

[0043] where Vdio is the forward conduction voltage of the second diode D2, VC_CP is the voltage of the negative power supply, and VS_CP is the voltage of the positive power supply.

[0044] Through the design of the charge pump core, the present utility model integrates capacitors within the chip, reducing the dependence on external capacitors and lowering the overall cost.

[0045] In this embodiment, the reference voltage circuit is as Figure 5 shown. When the charge pump core 104 is not working, the output voltage of the reference voltage circuit: VCP = VS - Vdio, where Vdio is the forward conduction voltage of the second diode 105.

[0046] When the charge pump core 104 is working, the current I generated by the current source 102 flows through the first resistor 101, so the first resistor 101 generates a voltage drop IR. By reasonably setting the value of the voltage drop IR of the first resistor 101, that is, the voltage applied to the gate of the first transistor 103, the first transistor 103 is turned on. The first transistor 103 is a P-type MOSFET. After the first transistor 103 is turned on, the source voltage of the first transistor 103 is limited to: VS - IR + VGS, and this voltage is the second power supply reference terminal VC_CP of the charge pump circuit 104, where VS is the power supply voltage, and VS is the first power supply reference terminal voltage VS_CP of the charge pump core; VGS is the gate-source voltage of the first transistor 103.

[0047] In this embodiment, the current source 102 is implemented in the form of a current mirror, and the overdrive voltage of the current mirror is designed as Vov. The lowest operating voltage at the input of the current source 102 can be obtained as Vov. On the premise of not considering the internal boost loss of the charge pump circuit 104, by setting the voltage drop IR of the first resistor 101, the lowest operating voltage of the power supply VS can be obtained as Vov + IR. Setting Vov as 0.2V and IR as 2.5V, the lowest operating voltage of the power supply VS is obtained as 2.7V. 2.7V is a common design value in integrated circuits. Therefore, the present utility model can enable the chip to operate stably in the low-voltage environment of conventional integrated circuits.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not restrictive. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the purpose and scope of the technical solutions of the present invention, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A charge pump circuit with a wide operating power supply range, characterized in that: include: A plurality of charge pump cores, each of which is provided with a multi-stage charge pump circuit module, wherein the multi-stage charge pump circuit module includes a plurality of charge pump charge and discharge enable switches to realize the switching of the charging circuit or the boost circuit of the multi-stage charge pump circuit module; each charge pump core is provided with a charge pump charge and discharge enable switch control module for controlling the switching of the charge pump charge and discharge enable switch in the corresponding charge pump core; The number of the charge pump cores is not less than four; The output ends of the charge pump cores are connected in common as the output ends of the charge pump circuit with a wide operating power supply range, so that at least two charge pump cores can output to the load.

2. A charge pump circuit with a wide operating power supply range according to claim 1, characterized in that: The number of the charge pump cores is four.

3. The charge pump circuit with a wide operating power supply range according to claim 2, characterized in that: The charge pump core includes a multi-stage charge pump circuit module and a charge and discharge enable control module; The multi-stage charge pump circuit module includes a first capacitor, a second capacitor, a third capacitor, a first diode, and a charge and discharge enable switch; the charge and discharge enable switch includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch; The input ends of the third switch, the fifth switch, the seventh switch and the eighth switch are used as the first power supply reference end of the charge pump core and are connected to the positive electrode of the power supply; The output end of the third switch is connected to the input end of the first switch and one end of the first capacitor; the other end of the first capacitor is connected to the input end of the fourth switch, the output end of the fifth switch and the output end of the sixth switch; the output end of the first switch is connected to one end of the second capacitor and the input end of the sixth switch; The output end of the seventh switch is connected to the other end of the second capacitor and the input end of the second switch; the output end of the second switch is connected to one end of the third capacitor and the input end of the sixth switch; The output end of the eighth switch is connected to the other end of the third capacitor and the anode of the first diode; the cathode of the first diode is the output end of the charge pump core; The output end of the fourth switch is used as the second power supply reference end of the charge pump core and is connected to the negative pole of the power supply; The input end of the charge and discharge enable switch control module is the control signal input end of the charge pump core; the charging control end of the charge and discharge enable switch control end is used to switch the charging circuit of the charge pump core, and the control ends of the third switch, the fourth switch, the sixth switch, the seventh switch and the eighth switch are connected in common as the charging control end of the charge pump core; the boost control end of the charge and discharge enable switch control end is used to switch the boost circuit of the charge pump core, and the boost control end is connected to the control ends of the first switch, the second switch and the fifth switch.

4. The charge pump circuit with a wide operating power supply range according to claim 3, characterized in that: The charge and discharge enable switch control module includes a first inverter and a second inverter; the input end of the first inverter is the input end of the charge and discharge enable switch control module, and the output end is connected to the input end of the second inverter and serves as the charging control end of the charge and discharge enable switch control module; the output end of the second inverter is the boost control end of the charge and discharge enable switch control module.

5. The charge pump circuit with a wide operating power supply range according to claim 4, characterized in that: The charge and discharge enabling switches are all N-channel transistors; the control end of the charge and discharge enabling switch is the gate of the N-channel transistor.

6. The charge pump circuit with a wide operating power supply range according to claim 1, characterized in that: Also included is a reference voltage circuit; The reference voltage circuit includes a first resistor, a second diode, a first transistor, a current source and a charge pump core; The high level reference terminal of the charge pump core, the anode of the second diode and one end of the first resistor are connected to a high level; The other end of the first resistor is connected to the gate of the first transistor and the negative electrode of the current source; The positive electrode of the current source is grounded; The low level reference terminal of the charge pump core is connected to the source of the first transistor, the control signal input terminal of the charge pump core is used to receive the control signal, and the output terminal of the charge pump circuit is connected to the cathode of the second diode; The first transistor is a P-type MOSFET, and a drain of the first transistor is grounded.

7. A chip, characterized in that: A charge pump circuit with a wide operating power supply range as claimed in any one of claims 1 to 6 is integrated.

Images