Semiconductor structure, image sensor and electronic equipment
By setting first and second types of capacitors with angles of 45° to 90° on the semiconductor substrate of the image sensor, collecting charges overflowed by the pixel unit are solved, and the problems of insufficient dynamic range and motion artifacts of the CIS image sensor are improved, and the performance of the image sensor is improved.
Patent Information
- Application Number
- CN202421351556.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-13
- Publication Date
- 2025-06-17
- Estimated Expiration
- 2034-06-13
AI Technical Summary
The existing CIS image sensors have insufficient dynamic range when storing a large amount of signal charges, which can easily lead to "overexposure" of the image, and motion artifacts will occur when multiple exposures are exposed to obtain high dynamic range images.
A capacitor layer is provided on the semiconductor substrate, including the first type of capacitor and the second type of capacitor. The two extend at an angle X (45°≤X≤90°) to collect charges overflowed by pixel units and alleviate the wafer warping problem caused by excessive stress in a single direction of the semiconductor substrate.
Relieve stress through overflow capacitors in different extension directions, improve the performance of the image sensor, avoid image overexposure, retain details of the highlighted picture, and reduce motion artifacts.
Smart Images
Figure CN222996967U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of imaging, and particularly to a semiconductor structure, an image sensor including the semiconductor structure, and an electronic device including the image sensor. Background Art
[0002] In the field of image sensors, the higher the dynamic range value, the more details can be captured in a large dynamic range scene. However, CIS image sensors usually cannot store a large amount of signal charges in photodiodes, so the dynamic range is insufficient, which is likely to cause the problem of "overexposure" of images. Currently, multiple exposures are often used to obtain high-dynamic-range images, but multiple exposures will cause a time lag problem between multiple images, resulting in motion artifacts. In recent years, an additional trench capacitor is added beside the original photosensitive capacitor on the semiconductor substrate. When the photosensitive charges exceed the maximum limit that the photosensitive element can originally bear, the excess charges will flow into this added trench capacitor to avoid overexposure, and at the same time, the details of the high-brightness image can be retained, thereby improving the dynamic range of the image. Summary of the Utility Model
[0003] In view of this, the utility model provides a semiconductor structure for an image sensor, including: a semiconductor substrate provided with a plurality of pixel units distributed in a row direction and a column direction, the pixel units including pixel blocks arranged in an n×n structure and having the same color, where n is an integer greater than or equal to 2; a capacitor layer located above the semiconductor substrate, the capacitor layer being provided with a plurality of overflow capacitors corresponding to the pixel units to collect the charges overflowing from the pixel units; wherein, the overflow capacitor includes a first type of capacitor and a second type of capacitor arranged adjacent to each other, the extending direction of the first type of capacitor forms an angle X with the extending direction of the second type of capacitor, and 45°≤X≤90°.
[0004] Optionally, the extending direction of the first type of capacitor is parallel to the column direction in which the pixel units are arranged, and the extending direction of the second type of capacitor is parallel to the row direction in which the pixel units are arranged.
[0005] Optionally, the extending direction of the first type of capacitor is parallel to the diagonal direction of the pixel unit, and the extending direction of the second type of capacitor is parallel to the other diagonal direction of the pixel unit.
[0006] Optionally, the extending direction of the first type of capacitor is perpendicular to the extending direction of the second type of capacitor.
[0007] Optionally, the extending direction of the first type of capacitor passes through the center point of the second type of capacitor, and the extending direction of the second type of capacitor passes through the center point of the first type of capacitor.
[0008] Optionally, along one of the row direction or the column direction, the first type of capacitors and the second type of capacitors are alternately arranged.
[0009] Optionally, along the row direction and the column direction, the first type of capacitors and the second type of capacitors are alternately arranged.
[0010] Optionally, along the direction from the center to the edge of the semiconductor structure, the angle X between the extending directions of the first type of capacitors and the second type of capacitors gradually increases.
[0011] The present application also provides an image sensor including the above semiconductor structure.
[0012] The present application also provides an electronic device including the above image sensor.
[0013] Compared with the prior art, the present utility model has at least the following prominent advantages:
[0014] In the present utility model, by providing the first type of capacitors and the second type of capacitors with different extending directions, the stress directions of the two types of overflow capacitors are different, thereby alleviating the problem of wafer warping caused by excessive stress in a single direction of the semiconductor substrate, and improving the performance of the image sensor. Description of the Drawings
[0015] Figure 1 is a pixel circuit with an overflow capacitor C DCG in the prior art;
[0016] Figure 2 is a schematic cross-sectional structure diagram of a semiconductor structure provided by the present application;
[0017] Figure 3 is a schematic arrangement diagram of the first type of capacitors and the second type of capacitors provided by an embodiment of the present utility model;
[0018] Figure 4 is a top view of a semiconductor structure provided by the present application;
[0019] Figure 5 is a top view of another semiconductor structure provided by the present application;
[0020] Figure 6 is a top view of another semiconductor structure provided by the present application;
[0021] Figure 7 is a top view of another semiconductor structure provided by the present application;
[0022] Figure 8 is a top view of another semiconductor structure provided by the present application;
[0023] Figure 9 It is a top view of another semiconductor structure provided by this application.
[0024] Element Label Explanation
[0025] 1 Semiconductor structure
[0026] 10 Semiconductor substrate
[0027] 20 Capacitance layer
[0028] 30 Optical structure layer
[0029] 210 Overflow capacitance
[0030] 220 First type of capacitance
[0031] 230 Second type of capacitance
[0032] 211 First metal electrode
[0033] 212 Second metal electrode
[0034] 213 Insulation region Detailed implementation manners
[0035] The following uses specific specific examples to illustrate the implementation manners of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application.
[0036] When detailing the embodiments of this application, for the convenience of description, the cross-sectional views showing the device structure will be enlarged locally not in accordance with the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of this application here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.
[0037] For the convenience of description, spatial relationship terms such as "beneath", "below", "lower than", "under", "above", "on", etc. may be used herein to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can also be one or more intervening layers.
[0038] In the context of the present application, the structure in which the described first feature is "above" the second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0039] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present application. Therefore, only the components related to the present application are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0040] Figure 1 is a pixel circuit with an overflow capacitor C in the prior art. As shown in the figure, the pixel circuit includes a photosensitive element PD, a transfer transistor TX, a floating diffusion point FD, an overflow control transistor DFD, an overflow capacitor C DCG . The cathode of the photosensitive element PD is connected to the first end of the transfer transistor TX, the anode of the photosensitive element PD is grounded, the second end of the transfer transistor TX, the first end of the overflow control transistor DFD, and the controlled end of the source follower transistor SF are all coupled to the floating diffusion point FD. The first end of the reset transistor RST, the second end of the overflow control transistor DFD, and the first end of the overflow capacitor C DCG are connected. The second end of the overflow capacitor C DCG is grounded. The second end of the reset transistor RST and the first end of the source follower transistor SF are both connected to the positive power supply terminal VDD. The second end of the source follower transistor SF is connected to the first end of the row selection transistor RS. The second end of the row selection transistor RS constitutes the signal output terminal of the pixel circuit and is used to output the corresponding pixel signal PIXEL. In practical applications, when the number of photoelectrons converted by the photosensitive element PD exceeds the maximum limit that can be originally carried, the excess photoelectrons will flow into the adjacent overflow capacitor C DCG , rather than being "overexposed" due to overflow. In this way, the highlight information in the shooting scene can be better retained by the sensor, and the output film is also closer to the light and shadow scene in reality. DCG
[0041] However, when forming the overflow capacitor C DCG , the etching and filling of the deep trench will seriously affect the warping of the wafer, resulting in the inability to operate the wafer process and even the breakage of the wafer. Currently, the traditional overflow capacitor C DCG blocks stress by adding a dielectric layer, which actually increases the photomask and will increase the process cost and process time in the wafer process.
[0042] To solve this problem, the present application provides a new 3D overflow capacitor structure pattern to alleviate and disperse the stress problem caused by deep trench etching and filling.
[0043] Please refer to Figure 2 and Figure 3 , Figure 2 is a schematic cross-sectional view of a semiconductor structure for an image sensor provided by an embodiment of the utility model, Figure 3 Schematic diagram of the arrangement of the first type of capacitor and the second type of capacitor provided by the embodiment of the utility model. As shown in the figure, the semiconductor structure 1 includes:
[0044] A semiconductor substrate 10 is provided with a plurality of pixel units 100 distributed in a row direction X and a column direction Y; and the pixel unit 100 includes pixel blocks 101 arranged in an n×n structure and having the same color, wherein n is an integer greater than or equal to 2; Figure 4 In the semiconductor structure shown, n=2, that is, a pixel unit 100 includes four pixel blocks 101 arranged in a 2×2 structure and having the same color. In other embodiments, Figure 8 In the semiconductor structure shown, n=3, that is, a pixel unit 100 includes nine pixel blocks 101 arranged in a 3×3 structure and having the same color;
[0045] Specifically, an optical structure layer 30 is also provided under the semiconductor substrate 10. Generally speaking, the pixel unit captures photogenerated charges to obtain the intensity value of light. At the same time, in order to be able to distinguish colors and improve photosensitivity, the optical structure layer 30 includes a microlens and a color filter located between the pixel unit and the microlens to transmit light of a specific color and focus external light onto the pixel block of the pixel unit to increase the photosensitivity. In the pixel unit arranged in an n×n structure, a microlens can be provided under each pixel block according to actual needs, or a microlens can be provided under each pixel unit, that is, multiple pixel blocks of the same color share one microlens.
[0046] The capacitor layer 20 is located above the semiconductor substrate 10. The capacitor layer 20 is provided with a plurality of overflow capacitors 210 corresponding to the pixel units 100 to collect the charges overflowed from the pixel units 100.
[0047] It can be understood that the capacitor layer 20 is provided with a plurality of overflow capacitors 210 corresponding to the pixel units 100. The corresponding here refers to the position correspondence, that is, an overflow capacitor 210 is provided at the center position above each pixel unit 100; for example, Figure 2 As shown, when the pixel unit 100 includes four pixel blocks 101 arranged in a 2×2 structure and having the same color, an overflow capacitor 210 is correspondingly arranged at the center position below two adjacent pixel blocks 101.Figure 2 As for the structure of the overflow capacitor 210, it includes a first metal electrode 211, a second metal electrode 212, and an insulating region 213 located therebetween. That is, the overflow capacitor is a MIM (Metal Insulator Metal) capacitor. To increase the capacitance density and reduce parasitic effects, an additional layer is usually added between the upper and lower metal layers, and the upper and lower metal layers are connected through vias. This can reduce the distance between the electrode plates, thereby increasing the capacitance value.
[0048] With reference to Figure 2 and Figure 3 , the overflow capacitor 210 includes a first type of capacitor 220 and a second type of capacitor 230 arranged adjacent to each other. The extending direction of the first type of capacitor 220 forms an angle X with the extending direction of the second type of capacitor 230, and 45° ≤ X ≤ 90°.
[0049] In the present utility model, by providing the first type of capacitor 220 and the second type of capacitor 230 with different extending directions, the stress directions of the two overflow capacitors are different, thereby alleviating the problem of wafer warping caused by excessive stress in a single direction of the semiconductor structure, and improving the performance of the image sensor.
[0050] In some embodiments, as shown in Figure 4 and Figure 5 , the extending direction of the first type of capacitor 220 is parallel to the column direction Y in which the pixel units 100 are arranged, and the extending direction of the second type of capacitor 230 is parallel to the row direction X in which the pixel units are arranged.
[0051] Optionally, the extending direction of the first type of capacitor 220 is perpendicular to the extending direction of the second type of capacitor 230, that is, the row direction X and the column direction Y in which the pixel units 100 are arranged are also perpendicular to each other.
[0052] Further optionally, the extending direction of the first type of capacitor 220 passes through the center point of the second type of capacitor 230, and the extending direction of the second type of capacitor 230 passes through the center point of the first type of capacitor 220.
[0053] Since the volume of the MIM capacitor is relatively large, by designing the extending direction of the first type of capacitor 220 and the extending direction of the second type of capacitor 230 to be perpendicular to each other and the extending directions respectively pass through the center points, the distance between adjacent overflow capacitors in the row direction X and the column direction Y is increased as much as possible, reducing the influence of mutual crosstalk between adjacent overflow capacitors.
[0054] In the embodiments of the present application, the extending direction of the overflow capacitor is parallel to the row direction and the column direction in which the pixel units are arranged, and the extending directions of the first type of capacitor 220 and the second type of capacitor 230 are perpendicular to each other and pass through the center point, so that the distance between adjacent overflow capacitors in the row direction and the column direction is increased as much as possible, reducing the influence of crosstalk. At the same time, the overflow capacitors with different extending directions relieve the stress borne by the wafer in a single direction, solving the problem of wafer warping caused by excessive stress in a single direction of the semiconductor structure, thereby improving the performance of the image sensor.
[0055] In some other embodiments, such as Figure 6 and Figure 7 shown, the extending direction of the first type of capacitor 220 is parallel to the diagonal direction of the pixel unit 100, and the extending direction of the second type of capacitor 230 is parallel to the other diagonal direction of the pixel unit 100.
[0056] Optionally, the extending direction of the first type of capacitor 220 is perpendicular to the extending direction of the second type of capacitor 230.
[0057] Since the volume of the MIM capacitor is relatively large, by designing the extending directions of the first type of capacitor 220 and the second type of capacitor 230 to be perpendicular to each other and the extending directions respectively pass through the center point, the distance between adjacent overflow capacitors in the row direction and the column direction is increased as much as possible, reducing the influence of crosstalk between adjacent overflow capacitors. At the same time, currently, in order to pursue a higher resolution of the image sensor, the size of the pixel unit is getting smaller and smaller. Setting the overflow capacitor 210 to be parallel to the diagonal direction of the pixel unit can make the most of the space of the pixel unit to set the overflow capacitor, improving the design freedom of the overflow capacitor.
[0058] In the embodiments of the present application, the extending directions of the first type of capacitor 220 and the second type of capacitor 230 are set to the diagonal directions of the pixel unit 100, and the extending directions of the first type of capacitor 220 and the second type of capacitor 230 are perpendicular. While reducing the crosstalk between adjacent overflow capacitors, the design freedom of the overflow capacitor is improved. The overflow capacitors with different extending directions relieve the stress borne by the wafer in a single direction, solving the problem of wafer warping caused by excessive stress, thereby improving the performance of the image sensor.
[0059] The embodiments of the present application also provide several arrangement methods of the overflow capacitors. In some embodiments, such as Figure 4 、 Figure 6 and Figure 8As shown, based on the above embodiments, along one of the row direction X or the column direction Y, the first type of capacitor 220 and the second type of capacitor 230 are alternately arranged. That is, the overflow capacitor arrangement in each row or each column is the same, and in each row or column with the same corresponding overflow capacitor arrangement, the first type of capacitor 220 and the second type of capacitor 230 are alternately arranged, so that the stress directions of the two types of overflow capacitors are different, thereby alleviating the stress borne by the wafer in a single direction and solving the problem of wafer warping caused by excessive stress, so as to improve the performance of the image sensor.
[0060] In some other embodiments, such as Figure 5 and Figure 7 As shown, based on the above embodiments, along the row direction X and the column direction Y, the first type of capacitor 220 and the second type of capacitor 230 are alternately arranged. That is, the overflow capacitor arrangements in adjacent rows and adjacent columns are different, and in each row or column of the corresponding overflow capacitors, the first type of capacitor 220 and the second type of capacitor 230 are alternately arranged. This overflow capacitor arrangement can not only alleviate the stress borne by the wafer in a single direction, but also enable each overflow capacitor to obtain sufficient redundant space, while reducing the influence of the too-close distance between adjacent overflow capacitors and increasing the design freedom of the overflow capacitors.
[0061] In some embodiments, along the direction from the center to the edge of the semiconductor structure, the angle X between the extension direction of the first type of capacitor 220 and the extension direction of the second type of capacitor 230 gradually increases. As Figure 9 shown, the semiconductor structure is provided with three groups of the first type of capacitor and the second type of capacitor. Among them, the angle between the extension direction of the first type of capacitor 220 and the extension direction of the second type of capacitor 230 at the edge position is 90°, the angle between the extension direction of the first type of capacitor 220 and the extension direction of the second type of capacitor 230 at the center position is 45°, and the angle between the extension direction of the first type of capacitor 220 and the extension direction of the second type of capacitor 230 between the center and the edge is 60°. For an image sensor chip, the stress distribution it receives is small at the center and large at the edge, and the stress at the four corners is the largest. By gradually increasing the angle X between the extension direction of the first type of capacitor 220 and the extension direction of the second type of capacitor 230 along the direction from the center to the edge of the semiconductor structure, the arrangement of the overflow capacitors can be designed according to its stress distribution characteristics, thereby reducing the stress of the image sensor and improving the performance.
[0062] The present application also provides an image sensor including the above semiconductor structure. The above semiconductor structure is provided with overflow capacitors with different extension directions, thereby alleviating the stress borne by the wafer in a single direction and solving the problem of wafer warping caused by excessive stress in a single direction of the semiconductor structure, so as to improve the performance of the image sensor.
[0063] The present application also provides an electronic device including the above image sensor.
[0064] The above content is a further detailed description of the present utility model in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present utility model is only limited to these descriptions. For those of ordinary skill in the technical field to which the present utility model belongs, without departing from the concept of the present utility model, several simple deductions or substitutions can still be made, which should all be regarded as belonging to the protection scope of the present utility model.
Claims
1. A semiconductor structure for an image sensor, characterized in that: include: A semiconductor substrate is provided with a plurality of pixel units distributed in a row direction and a column direction, wherein the pixel units include pixel blocks arranged in an n×n structure and having the same color, wherein n is an integer greater than or equal to 2; A capacitor layer, located above the semiconductor substrate, wherein the capacitor layer is provided with a plurality of overflow capacitors corresponding to the pixel units to collect the charges overflowed from the pixel units; The overflow capacitor includes a first type of capacitor and a second type of capacitor that are adjacently arranged, an extension direction of the first type of capacitor and an extension direction of the second type of capacitor form an angle X, and 45°≤X≤90°.
2. The semiconductor structure according to claim 1, wherein: An extension direction of the first type of capacitor is parallel to a column direction of the pixel units, and an extension direction of the second type of capacitor is parallel to a row direction of the pixel units.
3. The semiconductor structure according to claim 2, wherein: An extension direction of the first type of capacitor is parallel to a diagonal direction of the pixel unit, and an extension direction of the second type of capacitor is parallel to another diagonal direction of the pixel unit.
4. The semiconductor structure according to claim 2 or 3, characterized in that: An extension direction of the first type of capacitor is perpendicular to an extension direction of the second type of capacitor.
5. The semiconductor structure according to claim 4, characterized in that An extension direction of the first type of capacitor passes through a center point of the second type of capacitor, and an extension direction of the second type of capacitor passes through a center point of the first type of capacitor.
6. The semiconductor structure according to claim 4, wherein: Along one of the row direction or the column direction, the first type of capacitors and the second type of capacitors are alternately arranged.
7. The semiconductor structure according to claim 4, wherein: Along the row direction and the column direction, the first type of capacitors and the second type of capacitors are alternately arranged.
8. The semiconductor structure according to claim 1, wherein: Along the direction from the center to the edge of the semiconductor structure, an angle X between an extension direction of the first type of capacitor and an extension direction of the second type of capacitor gradually increases.
9. An image sensor, characterized in that: The invention comprises a semiconductor structure for an image sensor as claimed in any one of claims 1 to 8.
10. An electronic device, characterized in that: Comprising the image sensor as claimed in claim 9.