Detection circuit capable of quickly responding to different PWM duty ratios

Abstract

The utility model discloses a detection circuit for rapidly responding to different PWM duty ratios, the circuit comprises a single-chip microcomputer, a DSP, a power amplifier and a PWM signal processing circuit, when the power amplifier is distorted, PWM signals with different duty ratios are output, the PWM signals are converted into waveform signals with corresponding distortion degrees through the PWM signal processing circuit, a gain reduction strategy is executed through the determination of the DSP, and the PWM signals are converted into waveform signals with corresponding distortion degrees through the DSP. The design is used for solving the problems that under the application that a power amplifier chip is not provided with distortion degree setting, the time consumed by a task processed by using an MCU is too long, so that a DSP cannot execute a distortion strategy in time, the distortion of power amplifier output is too large, and sound output is not ideal. Under the condition that function requirements are met, a hardware PWM fast processing circuit is used for notifying a DSP to execute a distortion strategy, the function requirements can be met, and the processing time is optimized.

Description

Technical Field

[0001] The utility model belongs to the technical field of in - vehicle infotainment systems, and particularly relates to a detection circuit for quickly responding to different PWM duty cycles. Background Technique

[0002] Currently, for the scheme of setting the distortion - free degree of the digital power amplifier in the in - vehicle infotainment system, most often the MCU reads the PWM signal output by the WARN pin of the power amplifier chip, or the analog level signal converted from the PWM signal output by the WARN pin of the power amplifier chip. When the PWM duty cycle reaches the set output threshold, the DSP is notified to perform the distortion strategy control through the IIC or GPIO of the MCU. However, when the MCU processes the above two schemes, due to the delay in the processing tasks, the distortion strategy control of the power amplifier cannot respond in a timely manner, resulting in distorted sound output and an unsatisfactory listening experience. The two schemes for which the MCU is responsible for detection and processing are as follows (as shown in the attachment Figure 1 ): Power amplifier distortion output PWM signal -> MCU determination -> IIC / GPIO notify DSP for processing -> Power amplifier output distortion reduction, Power amplifier distortion output PWM signal -> Convert to analog level signal -> MCU determination -> IIC / GPIO notify DSP for processing -> Power amplifier output distortion reduction. Summary of the Utility Model

[0003] The utility model relates to a circuit design for rapid response of in - vehicle PWM, which is applicable to solving the problem that in the application where the power amplifier chip does not have a distortion - free degree setting, through the design of the hardware circuit, the output signal of the power amplifier is directly processed and then the DSP is notified to achieve rapid response of the DSP to the distortion strategy control. This scheme overcomes the drawback of the delay brought by the existing scheme that notifies the DSP to respond and execute the distortion strategy after being processed by the MCU, and the control is more rapid and the effect is more ideal. To achieve the above - mentioned purpose, the technical scheme of the utility model is as follows: A detection circuit for quickly responding to different PWM duty cycles, the circuit includes a single - chip microcomputer, a DSP, a power amplifier, and a PWM signal processing circuit. When the power amplifier is distorted, it outputs PWM signals with different duty cycles, which are converted into waveform signals corresponding to the distortion degree through the PWM signal processing circuit, and the DSP determines and executes the gain reduction strategy to reduce the output signal of the power amplifier and synchronously reduce the distortion degree.

[0004] As an improvement of the utility model, the PWM signal processing circuit includes a PWM output signal of the power amplifier, a circuit for converting the PWM to an analog level signal VA, a VREF circuit set by a comparator, and a level conversion circuit.

[0005] As an improvement of the present utility model, the VREF circuit set by the comparator includes using the host of the in-vehicle infotainment system to provide a stable voltage. After filtering through the first capacitor, it serves as the source of the VREF input to the inverting terminal of the comparator. The required threshold is set through the voltage division circuit of the first resistor, the second resistor, and the second capacitor.

[0006] As an improvement of the present utility model, the circuit for converting the PWM to the analog level signal VA includes the Warn output voltage of the power amplifier chip. When the power amplifier is distorted, it outputs PWM waveforms Vwarn with different duty cycles. The resistor R10, the resistor R11, the capacitor C3, and the internal power supply V4 form an analog level conversion circuit to convert the PWM to the analog level VA. The resistor R3 connects the analog level conversion circuit to the non-inverting terminal of the comparator to provide the signal VA to be compared.

[0007] As an improvement of the present utility model, the capacitor C4 in the circuit serves as the power supply filter of the comparator X1 to ensure the stability of the power supply of the comparator X1. The resistor R4 serves as the output pull-up of the comparator X1 to provide a high-level drive. The comparator X1 realizes the rapid high-low level flip by comparing the magnitudes of VA and VREF.

[0008] As an improvement of the present utility model, the level conversion circuit includes a MOS transistor. The output of the comparator X1 is connected to the drain of the MOS transistor in the level conversion circuit. The gate of the MOS transistor is connected to the internal power supply V3. The source of the MOS transistor is pulled up to the internal power supply V3 through R9. When the comparator X1 outputs a low level, the MOS transistor is turned on by pulling down the source of the MOS transistor through the body diode, and VOUT outputs a low level. When the comparator X1 outputs a high level, the MOS transistor is cut off, and VOUT is pulled up to V3 through R9 to output a high level.

[0009] As an improvement of the present utility model, the VREF circuit set by the comparator further includes the seventh resistor R7 which is used to adjust the set value of VREF to achieve the setting of the second threshold. The MCU_IO controls the on and off of the triode Q1 to realize the parallel connection or not of the second resistor R2 and the seventh resistor R7. The fifth resistor R5 and the sixth resistor R6 are matching circuits for the switch circuit of the triode Q1.

[0010] Compared with the prior art, the beneficial effects of the present utility model are as follows: This design is used to solve the problem that in the application where the power amplifier chip does not have a distortion degree setting, the task time for the MCU to process is too long, resulting in the DSP being unable to execute the distortion strategy in a timely manner, bringing excessive distortion in the power amplifier output and unsatisfactory sound output. Under the condition of meeting the functional requirements, a hardware PWM fast processing circuit is used to notify the DSP to execute the distortion strategy, which can not only meet the functional requirements but also optimize the processing time. Under the customer's time requirement for distortion processing, the effect improvement brought by the hardware PWM fast processing circuit is an effective improvement scheme for the rapid execution of the distortion strategy. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is the MCU processing circuit solution in the prior art;

[0012] Figure 2 is the PWM processing circuit solution in the present utility model;

[0013] Figure 3 is the PWM processing circuit design in the present utility model;

[0014] Figure 4 is the simulation data when the duty cycle of the output PWM high level is relatively high, the output remains high level, and the DSP does not respond to the strategy;

[0015] Figure 5 is the simulation data when the duty cycle of the output PWM high level is relatively small, the output remains low level, and the DSP continuously responds to the strategy;

[0016] Figure 6 is that when the duty cycle of the output PWM high level is near the set value, the output level changes between high and low, and the DSP responds to the strategy. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] The following further clarifies the present utility model in conjunction with the drawings and specific embodiments. It should be understood that the following specific embodiments are only used to illustrate the present utility model and not to limit the scope of the present utility model.

[0018] Embodiment: This embodiment relates to a circuit design for fast response of in-vehicle PWM. Based on the existing design scheme, replacing the MCU processing mechanism with a hardware circuit can solve the drawback of untimely distortion processing in the existing design. When the power amplifier reaches the set distortion level, the WARN pin outputs a PWM waveform with a corresponding duty cycle, which is converted into an analog level. Then, it is compared with the set voltage threshold. Through a comparator, the output signal is quickly transformed, and after level conversion by a MOS, it is provided to the DSP for signal attenuation to achieve the operation of quickly reducing the audio output of the power amplifier, ensuring that the distortion level is stable within the set threshold and avoiding problems caused by untimely distortion processing. By changing the size of the set threshold, the adjustment of different PWM duty cycle responses can be achieved, thus adjusting the distortion level.

[0019] As Figure 2 shown, it mainly consists of a single-chip microcomputer, a DSP, a power amplifier, and a PWM signal processing circuit. When the power amplifier is distorted, it outputs PWM signals with different duty cycles. After being converted into waveform signals corresponding to the distortion level by the PWM signal processing circuit, the DSP executes a gain reduction strategy based on the determination to reduce the output signal of the power amplifier and synchronously reduce the distortion level. The execution of the DSP distortion strategy ensures that the distortion is stable within the set value range of the PWM signal processing circuit, thereby achieving the purpose of quickly controlling the distortion level.

[0020] In this embodiment, the PWM signal processing circuit mainly consists of several parts, including the PWM output signal of the power amplifier, the circuit for converting PWM to the analog level signal VA, the VREF circuit set by the comparator, and the level conversion circuit, etc.

[0021] As shown in the appendix Figure 3 shown, the in-vehicle infotainment system host provides a stable V1, which is used as the source of the input VREF to the inverting terminal of the comparator after being filtered by C1. The required threshold is set through the voltage division circuit of R1, R2, and C2. R7 is used to adjust the set value of VREF to achieve the setting of the second threshold. The MCU_IO controls the on and off of Q1 to realize the parallel connection or not of R2 and R7. R5 and R6 are matching circuits applied to the Q1 switching circuit.

[0022] V5 is the Warn output of the power amplifier chip. When the power amplifier is distorted, it outputs a PWM waveform Vwarn with different duty cycles, and through R10, R11, C3, and the internal power supply V4, an analog level conversion circuit is formed to convert PWM into the analog level VA. V4 and V3 are internal 3.3V power supplies. R3 connects the analog level conversion circuit to the non-inverting terminal of the comparator to provide the signal VA to be compared.

[0023] C4 is used as the power filter for comparator X1 to ensure the stable power supply of comparator X1. R4 is used as the output pull-up of comparator X1 to provide the drive of high level. Comparator X1 realizes fast high and low level inversion by comparing the magnitudes of VA and VREF.

[0024] The output of comparator X1 is connected to the drain of level conversion circuit M1. The gate of M1 is connected to internal power supply V3. The source of M1 is pulled up to internal power supply V3 through R9. When the output of comparator X1 is at low level, M1 is turned on by pulling down the source of M1 through the body diode, and VOUT outputs low level. When the output of comparator X1 is at high level, M1 is cut off, and VOUT is pulled up to V3 through R9 to output high level.

[0025] The output level of VOUT notifies the DSP. The DSP reads the level change of VOUT to perform distortion strategy control. The audio output gain of the DSP is reduced to achieve the attenuation of the power amplifier output, and finally the distortion degree is stabilized within the set threshold range.

[0026] The flip speed of the comparator is rapid, so the hardware conversion time is better than the MCU processing time. Through the loop feedback of the power amplifier, PWM processing circuit, and DSP's response to the distortion strategy, the control of the distortion degree is quickly achieved.

[0027] Figures 4 to 6 For simulation data, as Figure 4 shown, when the duty cycle of the high level of the output PWM is relatively high, the output remains at high level, and the DSP does not respond to the strategy; as Figure 5 shown, when the duty cycle of the high level of the output PWM is relatively small, the output remains at low level, and the DSP continuously responds to the strategy; as Figure 6 shown, when the duty cycle of the high level of the output PWM is near the set value, the output level changes between high and low, and the DSP responds to the strategy.

[0028] In this embodiment, MCU_IO: The MCU controls high and low levels; VCC: The power supply voltage of the comparator; VDD: The power supply voltage of the DSP; Vwarn: The PWM signal output by the power amplifier distortion; VA: The analog level signal converted from the PWM signal; VREF: The threshold voltage set corresponding to the distortion degree; Vout: The PWM signal output corresponding to the set threshold; MCU: Microcontroller; DSP: Digital audio processor; PWM: Pulse width modulation; IIC: Serial communication bus; WARN: Alarm signal; GPIO: General-purpose input / output.

[0029] It should be noted that the above content only illustrates the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. For those of ordinary skill in the art of this technology, without departing from the principle of the present invention, several improvements and refinements can still be made, and these improvements and refinements all fall within the protection scope of the claims of the present invention.

Claims

1. A detection circuit that quickly responds to different PWM duty cycles, characterized in that: The circuit includes a single-chip microcomputer, a DSP, a power amplifier and a PWM signal processing circuit. When the power amplifier is distorted, it outputs PWM signals with different duty cycles, which are converted into waveform signals with corresponding distortion through the PWM signal processing circuit. The gain reduction strategy is executed through the judgment of the DSP to reduce the output signal of the power amplifier and reduce the distortion synchronously.

2. A detection circuit for quickly responding to different PWM duty cycles according to claim 1, characterized in that: The PWM signal processing circuit includes a power amplifier output signal PWM, a circuit for converting the PWM into an analog level signal VA, a VREF circuit set by a comparator, and a level conversion circuit.

3. A detection circuit for quickly responding to different PWM duty cycles according to claim 2, characterized in that: The VREF circuit set by the comparator includes using the vehicle infotainment system host to provide a stable voltage, which is used as the source of the VREF input to the reverse end of the comparator after filtering through the first capacitor, and setting the required threshold through a voltage divider circuit of the first resistor, the second resistor and the second capacitor.

4. A detection circuit for quickly responding to different PWM duty cycles according to claim 2, characterized in that: The circuit for converting the PWM analog level signal VA includes the Warn output voltage of the power amplifier chip, and outputs a PWM waveform Vwarn with different duty cycles when the power amplifier is distorted. An analog level conversion circuit is formed by resistor R10, resistor R11, capacitor C3 and internal power supply V4 to realize the conversion of PWM to analog level VA. Resistor R3 connects the analog level conversion circuit to the same direction end of the comparator to provide a signal to be compared VA.

5. The detection circuit for quickly responding to different PWM duty cycles according to claim 1, characterized in that: In the circuit, capacitor C4 is used as a power supply filter for comparator X1 to ensure the stability of the power supply of comparator X1. R4 is used as an output pull-up for comparator X1 to provide a high-level drive. Comparator X1 achieves rapid high-low level flipping by comparing the size of VA and VREF.

6. A detection circuit for quickly responding to different PWM duty cycles according to claim 2, characterized in that: The level conversion circuit includes a MOS tube, the output of the comparator X1 is connected to the drain of the MOS tube of the level conversion circuit, the gate of the MOS tube is connected to the internal power supply V3, and the source of the MOS tube is pulled up to the internal power supply V3 through R9, so that when the comparator X1 outputs a low level, the MOS tube pulls down the source of the MOS tube through the body diode to realize that the MOS tube is turned on, and VOUT outputs a low level. When the comparator X1 outputs a high level, the MOS tube is cut off, and VOUT is pulled up to V3 through R9 to output a high level.

7. The detection circuit for quickly responding to different PWM duty ratios according to claim 3, characterized in that: The VREF circuit set by the comparator also includes a seventh resistor R7 which is used to adjust the setting value of VREF to achieve the second threshold setting. The MCU_IO controls the on and off of the transistor Q1 to achieve whether the second resistor R2 is connected in parallel with the seventh resistor R7. The fifth resistor R5 and the sixth resistor R6 are matching circuits applied to the transistor Q1 switch circuit.

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