Semiconductor device

Abstract

The utility model provides a semiconductor device. The semiconductor device comprises a heterojunction structure, a grid electrode, a source electrode, a drain electrode and a heat dissipation layer. The heterojunction structure comprises a channel layer and a barrier layer located on one side of the channel layer. The grid electrode, the source electrode and the drain electrode are all located on the side, away from the channel layer, of the barrier layer. The heat dissipation layer is located on the side, away from the barrier layer, of the channel layer, the heat dissipation layer comprises a plurality of heat dissipation columns arranged at intervals, and the material of the heat dissipation layer is a single crystal material or a polycrystalline material.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor device. Background Art

[0002] GaN-based high electron mobility transistors (HEMTs) have advantages such as high electron mobility, high power density, high temperature resistance, and low noise, and are often used in high-power amplifiers, low-noise amplifiers, mixers, and oscillator circuits to enhance signal transmission and reception capabilities, and are widely used in fields such as radar, communication, meteorological satellites, and radio navigation.

[0003] The bending performance of existing GaN-based high electron mobility transistors is poor, which limits their application in flexible devices such as portable wearable devices. Summary of the Utility Model

[0004] An embodiment of this application provides a semiconductor device. The semiconductor device includes:

[0005] A heterojunction structure, the heterojunction structure including a channel layer and a barrier layer located on one side of the channel layer;

[0006] A gate, a source, and a drain, located on the side of the barrier layer away from the channel layer;

[0007] A heat dissipation layer, located on the side of the channel layer away from the barrier layer, the heat dissipation layer including a plurality of heat dissipation columns arranged at intervals, and the material of the heat dissipation layer being a single crystal material or a polycrystalline material.

[0008] In one embodiment, the semiconductor device further includes a metal layer located on the side of the heat dissipation layer away from the channel layer, and the orthographic projection of the metal layer on the channel layer covers the channel layer.

[0009] In one embodiment, the semiconductor device further includes a bonding layer located between the heat dissipation layer and the heterojunction structure, and the portions of the metal layer located between adjacent heat dissipation columns and each heat dissipation column are in direct contact with the bonding layer respectively.

[0010] In one embodiment, the material of the metal layer is Ag, Cu, Al, or an alloy, and the alloy includes at least two of Ag, Cu, and Al.

[0011] In one embodiment, the semiconductor device further includes a substrate located between the heat dissipation layer and the heterojunction structure and a bonding layer located between the substrate and the heterojunction structure, and the bonding layer is in direct contact with the substrate.

[0012] In one embodiment, the height range of the heat dissipation columns is 100 μm to 2000 μm.

[0013] In one embodiment, the distance between two adjacent heat dissipation columns ranges from 10 μm to 2000 μm.

[0014] In one embodiment, the width of the heat dissipation column ranges from 10 μm to 2000 μm.

[0015] In one embodiment, the material of the heat dissipation layer is diamond; and / or,

[0016] The semiconductor device further includes a bonding layer located between the heat dissipation layer and the heterojunction structure. The material of the bonding layer is solder, or the bonding layer is a silicon nano-adhesion layer.

[0017] In one embodiment, the semiconductor device further includes a spacer layer located between the channel layer and the barrier layer and a charge supply layer located between the spacer layer and the barrier layer. The bandgap width of the spacer layer is greater than the bandgap widths of the channel layer and the charge supply layer respectively.

[0018] The semiconductor device provided by the embodiment of the present application has a heat dissipation layer provided on the side of the channel layer away from the barrier layer. The material of the heat dissipation layer is a single crystal material or a polycrystalline material, so the heat dissipation performance of the heat dissipation layer is relatively good, and the heat dissipation performance of the semiconductor device can be effectively improved; since the heat dissipation layer includes a plurality of heat dissipation columns arranged at intervals, the heat dissipation layer can be bent, and the bending performance of the semiconductor device can be improved while ensuring the heat dissipation performance of the semiconductor device, so that the semiconductor device can be applied to flexible devices. Description of the Drawings

[0019] Figure 1 is a cross-sectional view of a semiconductor device provided by an exemplary embodiment of the present application;

[0020] Figure 2 is a cross-sectional view of a semiconductor device provided by another exemplary embodiment of the present application;

[0021] Figure 3 is a cross-sectional view of a first intermediate structure provided by an exemplary embodiment of the present application;

[0022] Figure 4 is a cross-sectional view of a second intermediate structure provided by an exemplary embodiment of the present application;

[0023] Figure 5 is a cross-sectional view of a third intermediate structure provided by an exemplary embodiment of the present application;

[0024] Figure 6 is a cross-sectional view of a fourth intermediate structure provided by an exemplary embodiment of the present application;

[0025] Figure 7It is a cross-sectional view of the fifth intermediate structure provided by an exemplary embodiment of the present application;

[0026] Figure 8 It is a cross-sectional view of the sixth intermediate structure provided by an exemplary embodiment of the present application;

[0027] Figure 9 It is a cross-sectional view of the seventh intermediate structure provided by an exemplary embodiment of the present application;

[0028] Figure 10 It is a cross-sectional view of the eighth intermediate structure provided by an exemplary embodiment of the present application;

[0029] Figure 11 It is a cross-sectional view of the ninth intermediate structure provided by an exemplary embodiment of the present application;

[0030] Figure 12 It is a cross-sectional view of the tenth intermediate structure provided by an exemplary embodiment of the present application;

[0031] Figure 13 It is a cross-sectional view of the eleventh intermediate structure provided by an exemplary embodiment of the present application;

[0032] Figure 14 It is a cross-sectional view of the twelfth intermediate structure provided by an exemplary embodiment of the present application;

[0033] Figure 15 It is a cross-sectional view of the thirteenth intermediate structure provided by an exemplary embodiment of the present application;

[0034] Figure 16 It is a cross-sectional view of the fourteenth intermediate structure provided by an exemplary embodiment of the present application;

[0035] Figure 17 It is a cross-sectional view of the fourteenth intermediate structure provided by another exemplary embodiment of the present application. Detailed implementation manners

[0036] Here, the technical solutions in the embodiments (or "implementation manners") of the present application will be clearly and completely described in conjunction with the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other. When the following description relates to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0037] The embodiments of the present application provide a semiconductor device. As Figure 1 and Figure 2As shown, the semiconductor device includes a heterojunction structure 10, a gate 20, a source 30, a drain 40, and a heat dissipation layer 50. The heterojunction structure 10 includes a channel layer 11 and a barrier layer 12 located on one side of the channel layer 11. The gate 20, the source 30, and the drain 40 are all located on the side of the barrier layer 12 away from the channel layer 11. The heat dissipation layer 50 is located on the side of the channel layer 11 away from the barrier layer 12. The heat dissipation layer 50 includes a plurality of heat dissipation columns 51 arranged at intervals. The material of the heat dissipation layer 50 is a single crystal material or a polycrystalline material.

[0038] In the semiconductor device provided by the embodiment of the present application, by providing the heat dissipation layer 50 on the side of the channel layer 11 away from the barrier layer 12, and the material of the heat dissipation layer 50 is a single crystal material or a polycrystalline material, the heat dissipation performance of the heat dissipation layer 50 is relatively good, which can effectively improve the heat dissipation performance of the semiconductor device; since the heat dissipation layer 50 includes a plurality of heat dissipation columns 51 arranged at intervals, the heat dissipation layer 50 can be bent, which can improve the bending performance of the semiconductor device while ensuring the heat dissipation performance of the semiconductor device, so that the semiconductor device can be applied to flexible devices.

[0039] In one embodiment, the material of the heat dissipation layer 50 is diamond. Diamond has very good heat dissipation performance and can significantly improve the heat dissipation performance of the semiconductor device. In other embodiments, the material of the heat dissipation layer 50 can be single crystal silicon, silicon nitride, silicon carbide, gallium nitride, etc.

[0040] In one embodiment, the height range of the heat dissipation columns 51 is 100 μm to 2000 μm. With such a setting, it can be avoided that the height of the heat dissipation columns 51 is too small to effectively improve the heat dissipation performance of the semiconductor device, and it can also be avoided that the height of the heat dissipation columns 51 is too large to limit the bending angle of the semiconductor device. In some embodiments, the height of the heat dissipation columns 51 can be 100 μm, 300 μm, 500 μm, 700 μm, 1000 μm, 1300 μm, 1500 μm, 1700 μm, 2000 μm, etc.

[0041] In one embodiment, the distance between two adjacent heat dissipation columns 51 ranges from 10 μm to 2000 μm. With such a setting, it can be avoided that the density of the heat dissipation columns 51 is too small to effectively improve the heat dissipation performance of the semiconductor device, and it can also be avoided that the density of the heat dissipation columns 51 is too large to limit the bending angle of the semiconductor device. In some embodiments, the distance between two adjacent heat dissipation columns 51 can be 10 μm, 50 μm, 100 μm, 300 μm, 500 μm, 700 μm, 1000 μm, 1300 μm, 1500 μm, 1700 μm, 2000 μm, etc.

[0042] In one embodiment, the width of the heat dissipation column 51 ranges from 10 μm to 2000 μm. When the heat dissipation column 51 is cylindrical, the width of the heat dissipation column 51 refers to the diameter of the cross-section of the heat dissipation column 51; when the heat dissipation column 51 is cubic, the width of the heat dissipation column 51 refers to the largest side length of the heat dissipation column 51. With such a setting, it is possible to avoid the width of the heat dissipation column 51 being too small to effectively improve the heat dissipation performance of the semiconductor device, and it is also possible to avoid the width of the heat dissipation column 51 being too large to limit the bending angle of the semiconductor device. In some embodiments, the width of the heat dissipation column 51 can be 10 μm, 50 μm, 100 μm, 300 μm, 500 μm, 700 μm, 1000 μm, 1300 μm, 1500 μm, 1700 μm, 2000 μm, etc.

[0043] In one embodiment, as Figure 1 and Figure 2 shown, the semiconductor device further includes a metal layer 60 located on the side of the heat dissipation layer 50 away from the channel layer 11, and the orthographic projection of the metal layer 60 on the channel layer 11 covers the channel layer 11. With such a setting, the metal layer 60 covers each heat dissipation column 51, and the part of the metal layer 60 located between adjacent heat dissipation columns 51 is in direct contact with the film layer of the semiconductor device on the side of the heat dissipation layer 50 away from the metal layer 60. Then, the metal layer 60 can reinforce the heat dissipation columns 51 and prevent the heat dissipation columns 51 from falling off when the semiconductor device is bent.

[0044] In one embodiment, the material of the metal layer 60 is Ag, Cu, Al or an alloy, and the alloy includes at least two of Ag, Cu, Al. With such a setting, the metal layer 60 has good ductility and is not easily broken during the bending process, and the heat dissipation performance of the metal layer 60 is relatively excellent, which can ensure the heat dissipation effect of the semiconductor device.

[0045] In one embodiment, the thickness of the metal layer 60 ranges from 100 μm to 1000 μm. With such a setting, it is possible to avoid the thickness of the metal layer 60 being too small, resulting in the metal layer 60 breaking on the side of the heat dissipation column 51 during the formation of the metal layer 60 and being unable to cover the heat dissipation column 51 well, and it is also possible to avoid the thickness of the metal layer 60 being too large, resulting in an increase in the thickness of the semiconductor device and being unfavorable for the bending of the semiconductor device. In some embodiments, the thickness of the metal layer 60 is 100 μm, 300 μm, 500 μm, 700 μm, 900 μm, 1000 μm, etc.

[0046] In one embodiment, as Figure 1 and Figure 2, the semiconductor device further includes a bonding layer 80 located between the heat dissipation layer 50 and the heterojunction structure 10. The bonding layer 80 is used to bond the film layer structure including the heterojunction structure 10 and the film layer structure including the heat dissipation layer 50 together during the process of manufacturing the semiconductor device.

[0047] In some embodiments, the material of the bonding layer 80 is solder, or the bonding layer 80 is a silicon nano-adhesion layer. The solder can be silver paste or tin paste. With such a setting, the bonding layer 80 has good thermal conductivity, and can conduct the heat at the heterojunction structure 10 to the heat dissipation layer 50, avoiding the temperature of the heterojunction structure 10 being too high and affecting the life and stability of the semiconductor device.

[0048] In one embodiment, as Figure 1 shown, when the semiconductor device includes a metal layer 60, the part of the metal layer 60 located between adjacent heat dissipation columns 51 and each heat dissipation column 51 are in direct contact with the bonding layer 80 respectively. With such a setting, during the process of manufacturing the semiconductor device, after the heat dissipation columns 51 and the metal layer 60 are formed on the substrate, due to the presence of the metal layer 60, the multiple heat dissipation columns 51 of the heat dissipation layer 50 will not scatter, so the substrate can be removed, and a bonding material can be formed on the surface of the metal layer 60 and the heat dissipation columns 51 on the same side. With such a setting, it helps to reduce the thickness of the semiconductor device.

[0049] In another embodiment, as Figure 2 shown, the semiconductor device further includes a substrate 91 located between the heat dissipation layer 50 and the bonding layer 80, and the bonding layer 80 is in direct contact with the substrate 91. With such a setting, during the process of manufacturing the semiconductor device, after the heat dissipation columns 51 and the metal layer 60 are formed on the substrate 91, the bonding layer 80 can be formed on the substrate 91. Due to the presence of the substrate 91, it can further prevent the heat dissipation columns 51 from scattering or their positions from moving.

[0050] Furthermore, the thickness range of the substrate 91 is 20μm - 200μm; the material of the substrate 91 can be silicon carbide or silicon.

[0051] In one embodiment, the material of the channel layer 11 is unintentionally doped GaN, and the material of the barrier layer 12 is AlGaN. Due to the spontaneous polarization effect and piezoelectric polarization effect, the heterojunction structure 10 induces a built-in polarization electric field, thereby generating a high-density and high-mobility 2DEG (two-dimensional electron gas) at the interface between the channel layer 11 and the barrier layer 12.

[0052] In one embodiment, the thickness range of the channel layer 11 is 50nm - 500nm. The thickness of the channel layer 11 is, for example, 50nm, 100nm, 200nm, 300nm, 400nm, 500nm, etc.

[0053] In one embodiment, the thickness of the barrier layer 12 ranges from 10 nm to 500 nm. The thickness of the barrier layer 12 is, for example, 10 nm, 50 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, etc.

[0054] In one embodiment, as Figure 1 and Figure 2 shown, the semiconductor device further includes a nucleation layer 73 located on the side of the heterojunction structure 10 facing the heat dissipation layer 50. When fabricating the semiconductor device, the nucleation layer 73 is first formed on the substrate, and the heterojunction structure 10 is formed on the side of the nucleation layer 73 away from the substrate. The nucleation layer 73 can improve the lattice mismatch between the substrate and the film layer on the side of the nucleation layer 73 away from the substrate, the current collapse problem caused by interface defects or trap effects, and at the same time reduce the static current leakage and radio frequency conduction and improve the radio frequency performance. The nucleation layer 73 can be an AlN thin film or an AlGaN thin film, or the nucleation layer 73 can include two AlN thin films and an AlGaN thin film located between the two AlN thin films. The thickness range of the nucleation layer 73 can be from 10 nm to 500 nm.

[0055] In one embodiment, as Figure 1 and Figure 2 shown, the conductor device further includes a high-resistance buffer layer 74 located between the nucleation layer 73 and the heterojunction structure 10. The high-resistance buffer layer 74 can reduce the background carrier concentration to reduce the current collapse caused by the trap effect. The material of the high-resistance buffer layer 74 can be AlN or ZnO, or GaN doped with Mg, Fe, or C. The thickness range of the high-resistance buffer layer 74 can be from 50 nm to 500 nm.

[0056] In one embodiment, as Figure 1 and Figure 2 shown, the semiconductor device further includes a charge supply layer 72 located between the channel layer 11 and the barrier layer 12. The charge supply layer 72 can increase the electron concentration of 2DEG and improve the DC characteristics. The material of the charge supply layer 72 can be AlGaN or AIGaN doped with Si. The thickness range of the charge supply layer 72 can be from 1 nm to 10 nm.

[0057] In one embodiment, as Figure 1 and Figure 2As shown, the semiconductor device further includes a spacer layer 71 located between the charge supply layer 72 and the channel layer 11. The bandgap of the spacer layer 71 is greater than the bandgap of the channel layer 11 and the bandgap of the charge supply layer 72, respectively. The spacer layer 71 can reduce the influence of ion scattering in the charge supply layer 72 on the mobility of the 2DEG in the channel layer 11. The material of the spacer layer 71 can be AlN. The thickness range of the spacer layer 71 can be 1 nm to 10 nm.

[0058] In one embodiment, as Figure 1 and Figure 2 shown, the semiconductor device further includes a cap layer 75 located on the side of the barrier layer 12 away from the channel layer 11. The material of the cap layer 75 is GaN. The source electrode 30 and the drain electrode 40 are partially located in the slots penetrating through the cap layer 75 and the barrier layer 12, and the source electrode 30 and the drain electrode 40 are in contact with the charge supply layer 72, respectively. The side surfaces of the source electrode 30 and the drain electrode 40 are in contact with the cap layer 75, and good ohmic contacts are formed between the source electrode 30 and the drain electrode 40 and the cap layer 75, which helps to maintain the 2DEG generated by the heterojunction structure 10. The gate electrode 20 is located on the side of the cap layer 75 away from the heterojunction structure 10 and is in direct contact with the cap layer 75. A good Schottky contact is directly formed between the gate electrode 20 and the cap layer 75.

[0059] In one embodiment, as Figure 1 and Figure 2 shown, the semiconductor device further includes a passivation layer 76 located on the side of the cap layer 75 away from the heterojunction structure 10. The gate electrode 20 is partially located in the opening of the passivation layer 76. The slots where the above-mentioned source electrode 30 and drain electrode 40 are located penetrate through the passivation layer 76, the cap layer 75 and the barrier layer 12. The passivation layer 76 can reduce the gate leakage current, increase the breakdown voltage of the semiconductor device, and reduce the gate current collapse. The material of the passivation layer 76 can be silicon oxide or silicon carbide.

[0060] In one embodiment, the material of the gate electrode 20 can include at least two metal film layers. The material of the metal film layer is a material with a high work function. For example, the gate electrode 20 can include a stacked Ni film layer and Au film layer, or include a stacked Pt film layer and Au film layer, etc. This helps to suppress the gate leakage current. The thickness range of each metal film layer of the gate electrode 20 can be 5 nm to 200 nm.

[0061] In one embodiment, the materials of the source electrode 30 and the drain electrode 40 may include at least two metal film layers, and the materials of the metal film layers may be selected from Ti, Al, Ni, Au, Pt, etc. For example, the source electrode 30 and the drain electrode 40 may include a stacked Ti film layer and Al film layer, or include a stacked Ti film layer, Al film layer, Ni film layer and Au film layer, or include a stacked Ti film layer, Al film layer, Pt film layer and Au film layer, etc. The thickness range of each metal film layer in the source electrode 30 and the drain electrode 40 may be 5 nm to 200 nm.

[0062] In one embodiment, the semiconductor device is a HEMT.

[0063] The embodiment of the present application also provides a method for manufacturing a semiconductor device. The manufacturing method includes the following processes:

[0064] First, a nucleation layer is formed on a substrate.

[0065] Through this step, the first intermediate structure as shown in Figure 3 can be obtained. As shown in Figure 3 , the nucleation layer 73 covers the substrate 92. The MBE (Molecular Beam Epitaxy) technology can be used to form the nucleation layer 73. The material of the substrate 92 may be silicon or silicon carbide.

[0066] Subsequently, a high-resistance buffer layer is formed on the side of the nucleation layer away from the substrate.

[0067] Through this step, the second intermediate structure as shown in Figure 4 can be obtained. The MBE technology can be used to form the high-resistance buffer layer 74.

[0068] Subsequently, a channel layer is formed on the side of the high-resistance buffer layer away from the substrate.

[0069] Through this step, the third intermediate structure as shown in Figure 5 can be obtained. The MBE technology can be used to form the channel layer 11.

[0070] Subsequently, a spacer layer 71 is formed on the side of the channel layer 11 away from the substrate.

[0071] Through this step, the fourth intermediate structure as shown in Figure 6 can be obtained. The MBE technology can be used to form the channel layer spacer layer 71.

[0072] Subsequently, a charge supply layer 72 is formed on the side of the charge supply layer away from the substrate.

[0073] Through this step, the fifth intermediate structure as shown in Figure 7 can be obtained. The MBE technology can be used to form the charge supply layer 72.

[0074] Subsequently, a barrier layer 12 is formed on the side of the charge supply layer away from the substrate.

[0075] Through this step, the sixth intermediate structure as shown in Figure 8 can be obtained. The barrier layer 12 can be formed by MBE technology.

[0076] Subsequently, a cap layer 75 is formed on the side of the barrier layer 12 away from the substrate.

[0077] Through this step, the seventh intermediate structure as shown in Figure 9 can be obtained. The cap layer 75 can be formed by MBE technology.

[0078] Subsequently, a passivation layer 76 is formed on the side of the cap layer 75 away from the substrate.

[0079] Through this step, the eighth intermediate structure as shown in Figure 10 can be obtained. The passivation layer 76 can be formed by MBE technology.

[0080] Subsequently, two slots are formed through the passivation layer 76, the cap layer 75, and the barrier layer 12, and a source electrode 30 and a drain electrode 40 are formed. The source electrode 30 and the drain electrode 40 are located in different grooves.

[0081] Through this step, the ninth intermediate structure as shown in Figure 11 can be obtained. A photoresist with a hollowed-out area can be formed on the passivation layer 76 by photolithography and development techniques, and the passivation layer, the cap layer, and the barrier layer are etched through the hollowed-out area to form grooves. Dry etching techniques such as plasma etching, RIE (Reactive Ion Etching), and ICP (Inductively Coupled Plasma Etching) can be used to etch the passivation layer, the cap layer, and the barrier layer. The slots can be cylindrical with a diameter of 0.1 μm to 0.5 μm. After the grooves are formed, the photoresist is removed, and a photoresist with a hollowed-out area is formed again on the passivation layer by photolithography and development techniques, and the hollowed-out area exposes the grooves. The source electrode and the drain electrode are formed in the grooves by thin film deposition techniques such as electron beam evaporation or magnetron sputtering. Finally, the photoresist is removed.

[0082] Subsequently, an opening is formed through the passivation layer 76, and a gate electrode 20 is formed partially within the opening.

[0083] Through this step, the structure as shown in Figure 12The tenth intermediate structure shown. Lithography technology can be used to form a photoresist with a hollow on the passivation layer. The photoresist covers the source and drain electrodes, and the passivation layer 76 is etched through the hollow to form an opening. Dry etching technologies such as plasma etching, RIE, and ICP can be used to etch the passivation layer. The opening can be cylindrical with a diameter of 0.1 μm to 0.5 μm. After forming the opening, the photoresist is removed, and the lithography technology is used again to form a photoresist with a hollow on the passivation layer. The photoresist exposes the opening, and a gate 20 partially located in the opening is formed by thin film deposition technologies such as electron beam evaporation or magnetron sputtering.

[0084] Subsequently, the substrate of the tenth intermediate structure is thinned, or the substrate of the tenth intermediate structure is removed.

[0085] Through this step, the eleventh intermediate structure as shown in Figure 13 can be obtained. As shown in Figure 13 , the substrate is removed. Dry etching technologies such as plasma etching, RIE, and ICP can be used to etch the substrate to thin the substrate 92 or remove the substrate 92.

[0086] Subsequently, a heat dissipation thin film is formed on the substrate, and the heat dissipation thin film is patterned to obtain a plurality of spaced-apart heat dissipation columns 51; a metal layer 60 covering the heat dissipation columns is formed.

[0087] Through this step, the twelfth intermediate structure as shown in Figure 14 can be obtained. As shown in Figure 14 , the metal layer 60 covers each heat dissipation column 51 of the heat dissipation layer 50, and the part of the metal layer 60 located between adjacent heat dissipation columns 51 is in direct contact with the substrate 91.

[0088] Subsequently, the substrate of the twelfth intermediate structure is thinned, or the substrate of the twelfth intermediate structure is removed.

[0089] Dry etching technologies such as plasma etching, RIE, and ICP can be used to etch the substrate to thin the substrate or remove the substrate.

[0090] Subsequently, a first bonding film layer is formed on the surface of the eleventh intermediate structure away from the gate, and a second bonding film layer is formed on the surface of the twelfth intermediate structure after thinning or removing the substrate. The second bonding film layer faces the surface of the metal layer facing the heat dissipation columns.

[0091] Through this step, the thirteenth intermediate structure as shown in Figure 15 and the fourteenth intermediate structure as shown in Figure 16 or Figure 17 can be obtained. As shown in Figure 15 , the first bonding film layer 81 is in direct contact with the nucleation layer 73. As shown in Figure 16As shown, the second bonding film layer 82 is in direct contact with the substrate 91. In another embodiment, as Figure 17 shown, the substrate 91 is removed, and the second bonding film layer 82 is in direct contact with the metal layer 60 and the heat dissipation posts 51.

[0092] Subsequently, the thirteenth intermediate structure and the fourteenth intermediate structure are aligned, and the first bonding film layer contacts the second bonding film layer, and the thirteenth intermediate structure and the fourteenth intermediate structure are bonded.

[0093] Through this step, a semiconductor device as shown in Figure 1 or Figure 2 can be obtained. After the first bonding film layer 81 and the second bonding film layer 82 are bonded, a bonding layer 80 is formed. A transfer stamp can be used to pick up the thirteenth intermediate structure and the fourteenth intermediate structure and align them in contact. After the thirteenth intermediate structure and the fourteenth intermediate structure are in contact, temperature and pressure can be applied to bond them. The temperature range can be 25°C to 300°C, the pressure range can be 1 Mpa to 50 Mpa, and the duration of applying temperature and pressure can be 10 min to 60 min. This can ensure the reliability of the bonding process, and within this temperature and pressure range, it helps to reduce the thermal resistance at the bonding interface and further improve the heat dissipation performance of the semiconductor device.

[0094] Based on the above preparation method, an embodiment of the present application provides a specific example of a method for preparing a semiconductor device. The specific steps include:

[0095] First, use MBE technology to grow a 10-nm-thick AlN film layer as a nucleation layer on a substrate. In this step, the temperature of the substrate is 800°C. The Al metal atoms provided by the Al source react with the N atoms provided by nitrogen to form the AlN film layer. By adjusting the temperature of the Al source and the flow rate of nitrogen, the growth rate of the nucleation layer is controlled. The temperature of the Al source is 1200°C, and the growth rate of the nucleation layer is 5 nm / min. The Al source can be high-purity metal Al, and its purity can be greater than or equal to 99.9999%. The Al source can be solid metal Al particles or blocks, and the Al particles and Al blocks can form atomic beams under high-temperature heating.

[0096] Subsequently, use MBE technology to grow a 300-nm-thick Fe-doped GaN film layer as a high-resistance buffer layer on the nucleation layer. In this step, the temperature of the substrate is 800°C. The Ga metal atoms provided by the Ga source react with the N atoms provided by nitrogen to form the GaN film layer. The temperature of the Ga source is 1020°C, the temperature of the Fe source is 1100°C, and the growth rate of the high-resistance buffer layer is 3 nm / min. The Ga source can be high-purity metal Ga, and its purity can be greater than or equal to 99.9999%. The Ga source can be solid metal Al particles or blocks, and the Ga particles and Ga blocks can form atomic beams under high-temperature heating.

[0097] Subsequently, a 150-nm-thick intrinsic GaN film is grown on the high-resistance buffer layer as the channel layer by using MBE technology. The temperature of the substrate in this step is 700 °C. The Ga metal atoms provided by the Ga source react with the N atoms provided by nitrogen to form the channel layer. The temperature of the Ga source is 1020 °C, and the growth rate of the channel layer is 3 nm / min.

[0098] Subsequently, a 1-nm-thick AlN film is grown on the channel layer as the spacer layer by using MBE technology. The temperature of the substrate in this step is 800 °C. The Al metal atoms provided by the Al source react with the N atoms provided by nitrogen to form the spacer layer. By adjusting the temperature of the Al source and the flow rate of nitrogen, the growth rate of the spacer layer is controlled. The temperature of the Al source is 1150 °C, and the growth rate of the spacer layer is 4 nm / min.

[0099] Subsequently, a 1-nm-thick Si-doped AlGaN film is grown on the spacer layer as the charge supply layer by using MBE technology. The temperature of the substrate in this step is 800 °C. The Ga metal atoms provided by the Ga source react with the Al metal atoms provided by the Al source, the Si atoms provided by the SiCl4 (tetrachlorosilane) gas source, and the N atoms provided by nitrogen to form the charge supply layer. By adjusting the temperature of the Ga source, the temperature of the Al source, the flow rate of SiCl4, and the flow rate of nitrogen, the growth rate of the charge supply layer can be controlled. The temperature of the Ga source is 1200 °C, the temperature of the Al source is 1150 °C, the doping concentration of Si in AlGaN is 1% - 10%, and the growth rate of AlGaN is 5 nm / min.

[0100] Subsequently, a 50-nm-thick AlGaN film is grown on the charge supply layer as the barrier layer by using MBE technology. The temperature of the substrate in this step is 800 °C. The Ga metal atoms provided by the Ga source react with the Al metal atoms provided by the Al source and the N atoms provided by nitrogen to form the barrier layer. The temperature of the Ga source is 1200 °C, the temperature of the Al source is 1150 °C, and the growth rate of AlGaN is 5 nm / min.

[0101] Subsequently, a 10-nm-thick GaN film is grown on the barrier layer as the cap layer by using MBE technology. The temperature of the substrate in this step is 800 °C. The Ga metal atoms provided by the Ga source react with the N atoms provided by nitrogen to form the cap layer. The temperature of the Ga source is 1200 °C, and the growth rate of GaN is 5 nm / min.

[0102] Subsequently, an SiC film layer with a thickness of 50 nm is grown on the cap layer by MBE technology as a passivation layer. The temperature of the substrate in this step is 800 °C. The Si atoms of the SiCl4 gas source react with the C atoms provided by carbon tetrachloride (CCl4). The epitaxial temperature is 1600 °C, the C / Si ratio is 1.2, and the growth rate of the passivation layer is 1 nm / min.

[0103] Subsequently, a photoresist with a hollow is formed on the passivation layer by photolithography and development techniques, and grooves are formed by etching the passivation layer, the cap layer, and the barrier layer through the hollow area. Dry etching techniques such as plasma etching, RIE, and ICP can be used to etch the passivation layer, the cap layer, and the barrier layer. When etching the passivation layer, the cap layer, and the barrier layer, the gases introduced include BCl4, Cl2, and Ar, and the flow rates of the three are 40 sccm, 25 sccm, and 5 sccm respectively. The temperature of the gases is 100 °C, the etching power is 500 W, and the diameter of the formed groove is 3 μm. After forming the grooves, the photoresist is removed, and a photoresist with a hollow is formed again on the passivation layer by photolithography and development techniques. The hollow exposes the grooves, and source and drain electrodes are formed in the grooves by thin film deposition techniques such as electron beam evaporation or magnetron sputtering. The source and drain electrodes respectively include a stacked Ti film layer, an Al film layer, an Ni film layer, and an Au film layer. The thickness of the Ti film layer is 5 nm, the thickness of the Al film layer is 50 nm, the thickness of the Ni film layer is 30 nm, and the thickness of the Au film layer is 50 nm. Finally, the photoresist is removed.

[0104] Subsequently, a photoresist with a hollow is formed on the passivation layer by photolithography and development techniques. The photoresist covers the source and drain electrodes, and an opening is formed by etching the passivation layer through the hollow. Dry etching techniques such as plasma etching, RIE, and ICP can be used to etch the passivation layer, the cap layer, and the barrier layer. When etching the passivation layer, the cap layer, and the barrier layer, the gases introduced include BCl4, Cl2, and Ar, and the flow rates of the three are 40 sccm, 25 sccm, and 5 sccm respectively. The temperature of the gases is 100 °C, the etching power is 500 W, and the diameter of the formed opening is 3 μm. After forming the opening, the photoresist is removed, and a photoresist with a hollow is formed again on the passivation layer by photolithography and development techniques. The photoresist exposes the opening, and a gate electrode partially located in the opening is formed by thin film deposition techniques such as electron beam evaporation or magnetron sputtering. The gate electrode includes a stacked Ni film layer and an Au film layer. The thickness of the Ni film layer is 40 nm, and the thickness of the Au film layer is 60 nm. Finally, the photoresist is removed.

[0105] Subsequently, diamond films were grown on a clean SiC substrate using CVD technology, and the thickness of the diamond films was 500 μm; and a patterned photoresist was formed on the surface of the diamond films using photolithography and development techniques, and the diamond films were etched using a laser ablation technique to obtain a plurality of spaced-apart heat dissipation columns. The height of the heat dissipation columns was 500 μm, the diameter was 200 μm, and the spacing between adjacent heat dissipation columns was 500 μm.

[0106] Subsequently, a Cu metal layer was deposited on the heat dissipation columns using electron beam evaporation technology, and the thickness of the Cu metal layer was 200 μm.

[0107] Subsequently, the substrate and the substrate substrate were removed or thinned. The substrate and the substrate substrate were thinned using plasma etching technology. Finally, the substrate substrate was completely removed, and the thickness of the thinned substrate ranged from 20 μm to 200 μm. BCl4 and Ar were introduced during etching, and their flow rates were 40 sccm and 20 sccm respectively, the temperature was 25 °C, and the etching power was 400 W.

[0108] Subsequently, solder layers were grown on the surfaces of the substrate and the nucleation layer respectively. Silver solder paste was grown on the surfaces of the substrate and the substrate substrate using a doctor blade method, and the thickness of the silver solder paste was 30 μm.

[0109] Subsequently, a polydimethylsiloxane (PDMS) elastomeric stamp was used to transfer and pick up the two structures obtained in the previous step and assemble them. The temperature applied to the two structures was 120 °C, the pressure applied was 10 Mpa, and the time for applying the temperature and pressure was 30 min, thus obtaining a semiconductor device.

[0110] The embodiments of the method for preparing the semiconductor device provided in the embodiments of the present application and the embodiments of the semiconductor device belong to the same inventive concept. The descriptions of relevant details and beneficial effects can be referred to each other, and will not be elaborated here.

[0111] It should be noted that the drawings in the present application are all cross-sectional views obtained by cutting the three-dimensional structure along the stacking direction of the film layers.

[0112] Moreover, it can be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there can be an intermediate layer. Additionally, it can be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element, or there can be more than one intermediate layer or element. Additionally, it can also be understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there can also be more than one intermediate layer or element.

[0113] It should be noted that the technical solutions or technical features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the drawings; all modifications, equivalent replacements, improvements, etc. made within the spirit and principle of this application shall be included within the scope of protection of this application.

Claims

1. A semiconductor device, characterized in that: include: A heterojunction structure, the heterojunction structure comprising a channel layer and a barrier layer located on one side of the channel layer; The gate, source and drain are located on a side of the barrier layer away from the channel layer; The heat dissipation layer is located on a side of the channel layer away from the barrier layer. The heat dissipation layer comprises a plurality of heat dissipation columns arranged at intervals. The material of the heat dissipation layer is a single crystal material or a polycrystalline material.

2. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises a metal layer located on a side of the heat dissipation layer away from the channel layer, and an orthographic projection of the metal layer on the channel layer covers the channel layer.

3. The semiconductor device according to claim 2, characterized in that The semiconductor device further comprises a bonding layer located between the heat dissipation layer and the heterojunction structure, and a portion of the metal layer located between adjacent heat dissipation columns and each of the heat dissipation columns are in direct contact with the bonding layer.

4. The semiconductor device according to claim 2, characterized in that The material of the metal layer is Ag, Cu or Al.

5. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a substrate located between the heat dissipation layer and the heterojunction structure and a bonding layer located between the substrate and the heterojunction structure, wherein the bonding layer is in direct contact with the substrate.

6. The semiconductor device according to claim 1, wherein: The height of the heat dissipation column ranges from 100 μm to 2000 μm.

7. The semiconductor device according to claim 1, wherein: The distance between two adjacent heat dissipation columns ranges from 10 μm to 2000 μm.

8. The semiconductor device according to claim 1, wherein: The width of the heat dissipation column ranges from 10 μm to 2000 μm.

9. The semiconductor device according to claim 1, wherein: The material of the heat dissipation layer is diamond; and / or, The semiconductor device further comprises a bonding layer located between the heat dissipation layer and the heterojunction structure, the material of the bonding layer is solder, or the bonding layer is a silicon nano-adhesion layer.

10. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a spacer layer between the channel layer and the barrier layer and a charge supply layer between the spacer layer and the barrier layer, wherein the bandgap width of the spacer layer is greater than the bandgap width of the channel layer and the bandgap width of the charge supply layer.

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