Laser radar, vcsel laser drive circuit and switch chip

Abstract

The utility model discloses a laser radar, a vcsel laser drive circuit and a switch chip, and is applied to the technical field of power supplies, and the laser radar comprises a band-gap reference source which is used for providing an input voltage for an LDO (Low Dropout Regulator); the LDO is used for providing a first voltage for the first to Nth switching circuits; the register is used for storing the control signal; the first to Nth switching circuits are used for controlling the output of each switching circuit according to the output of the register, and the output of each switching circuit is a second voltage or 0v; at the same time, the output of one or more of the first to Nth switching circuits is a second voltage. According to the scheme of the invention, the high voltage is applied to the anode of the laser by controlling one or more of the N switching circuits to be switched on, and then the GaN switch is controlled to be switched on, so that the connected vcsel laser is switched on to emit light, and the purposes of providing a high-power power supply for the laser and simultaneously lightening the laser through multiple channels are achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of power supply, in particular to a driving circuit and a switch chip of a laser radar and a vcsel laser. Background Art

[0002] At present, LiDAR has great development and application in occasions such as autonomous driving and high-level assisted driving. LiDAR can achieve high-precision ranging, reconstruction of object shape, and road recognition. Vehicle-mounted LiDAR has some special requirements for laser light sources, especially the requirement to see far, so the power requirement is very high. For example, current vehicle-mounted LiDAR usually requires the peak optical power of VCSEL (Vertical-Cavity Surface-Emitting Laser) to reach 150W-300W, which brings great challenges to the power supply of VCSEL. In addition, since pure solid-state LiDAR has no mechanical rotating parts, to realize all-solid-state scanning LiDAR, it is necessary to use addressable multi-partition VCSEL, that is, to light up VCSELs in different partitions in time. In addition, in some current LiDARs, the luminous power is often unstable, resulting in a decrease in the performance of LiDAR.

[0003] In summary, how to provide high-power power to the laser and light up the laser in multiple channels simultaneously is a technical problem that technicians in this field urgently need to solve. Utility Model Content

[0004] The purpose of the utility model is to provide a driving circuit and a switch chip for a laser radar and a vcsel laser, so as to provide a high-power power supply for the laser and light up the laser in multiple channels at the same time.

[0005] In order to solve the above technical problems, the utility model provides the following technical solutions:

[0006] In a first aspect, the utility model provides a high-voltage switch chip, including: a bandgap reference source, an LDO, a register, and a first switch circuit to an Nth switch circuit;

[0007] The bandgap reference source is used to provide an input voltage to the LDO;

[0008] The LDO is used to provide a first voltage to the first to Nth switch circuits;

[0009] The register is used to store the control signal from the first switch circuit to the input end of the Nth switch circuit;

[0010] The first switch circuit to the Nth switch circuit are used to control the output of each switch circuit according to the output of the register. When the control signal is at a high level, the output of the switch circuit is the second voltage. When the control signal is at a low level, the output of the switch circuit is 0V. The second voltage is an externally input voltage, the second voltage is greater than the first voltage, the second voltage is greater than 50V, and the first voltage is greater than 3.3V.

[0011] Wherein, N is a positive integer greater than 10. At the same time, the output of one or more of the first switch circuit to the Nth switch circuit is the second voltage.

[0012] In an embodiment, the structures of the first switch circuit to the Nth switch circuit are the same, and any one of the first switch circuit to the Nth switch circuit includes:

[0013] A control circuit, a first NMOS switch, a second NMOS switch, a first capacitor, and an anti-backflow circuit;

[0014] The gate of the first NMOS switch and the gate of the second NMOS switch are respectively connected to the first output terminal of the control circuit and the second output terminal of the control circuit. The conduction states of the first NMOS switch and the second NMOS switch are opposite, and when the second NMOS switch is conducting, the output of this switch circuit is the second voltage.

[0015] The source of the first NMOS switch is grounded. The drain of the first NMOS switch is respectively connected to the source of the second NMOS switch and the second end of the first capacitor, and the connection end is used as the output terminal of the switch circuit. The drain of the second NMOS switch is connected to the second voltage.

[0016] The first end of the first capacitor is connected to the output terminal of the anti-backflow circuit, and the input terminal of the anti-backflow circuit is connected to the first voltage.

[0017] In an embodiment, the anti-backflow circuit is a diode;

[0018] The cathode of the diode is used as the output terminal of the anti-backflow circuit, and the anode of the diode is used as the input terminal of the anti-backflow circuit.

[0019] In an embodiment, the control circuit includes a single / double conversion circuit, a first buffer circuit, and a second buffer circuit;

[0020] The single / double conversion circuit is configured to receive the control signal output by the register. The first output terminal of the single / double conversion circuit is connected to the input terminal of the first buffer circuit, and the second output terminal of the single / double conversion circuit is connected to the input terminal of the second buffer circuit;

[0021] The output terminal of the first buffer circuit is connected to the first NMOS switch transistor;

[0022] The output terminal of the second buffer circuit is connected to the second NMOS switch transistor;

[0023] When the control signal is at a low level, the output of the first buffer circuit is at a high level, the output of the second buffer circuit is at a low level, the first NMOS transistor is turned on, and the second NMOS transistor is turned off;

[0024] When the control signal is at a high level, the output of the first buffer circuit is at a low level, the output of the second buffer circuit is at a high level, the first NMOS transistor is turned off, and the second NMOS transistor is turned on.

[0025] In one embodiment, the LDO includes: an error amplifier, a second capacitor, a first resistor, a second resistor, and a PMOS switch transistor;

[0026] For the error amplifier, its inverting input terminal is configured to be connected to the output terminal of the bandgap reference source, its non-inverting input terminal is respectively connected to the second terminal of the first resistor and the first terminal of the second resistor, and its output terminal is connected to the gate of the PMOS switch transistor;

[0027] The first terminal of the first resistor is connected to the drain of the PMOS switch transistor and the connection terminal serves as the output of the LDO. The source of the PMOS switch transistor is connected to the second voltage, and the second terminal of the second resistor is grounded; the first terminal of the second capacitor is connected to the output of the LDO, and the second terminal of the second capacitor is grounded.

[0028] In one embodiment, any one of the first switch circuit to the Nth switch circuit includes: a short-circuit protection circuit configured to output an alarm signal when detecting a short circuit in its own switch circuit.

[0029] In a second aspect, the present invention provides a driving circuit for a vcsel laser, including: the switch chip, the MCU controller, the GaN switch, and the switch driver as described above;

[0030] The switching chip includes N output ports, and the first output port to the Nth output port are respectively connected to the first ends of the first vcsel laser to the Nth vcsel laser; the second ends of the first vcsel laser to the Nth vcsel laser are all connected to the first end of the GaN switch, and the second end of the GaN switch is grounded;

[0031] The MCU controller is connected to the input end of the register of the switching chip;

[0032] The input end of the switch driver is connected to the MCU controller, and the output end of the switch driver is connected to the control end of the GaN switch;

[0033] The GaN switch is used to continuously switch the on-off state under the control of M trigger pulses issued by the MCU controller, so that the first to the Nth vcsel lasers emit light.

[0034] In one embodiment, it further includes: the first voltage stabilizing capacitor to the Nth voltage stabilizing capacitor;

[0035] The first ends of the first voltage stabilizing capacitor to the Nth voltage stabilizing capacitor are respectively connected to the first ends of the first vcsel laser to the Nth vcsel laser, and the second ends of the first voltage stabilizing capacitor to the Nth voltage stabilizing capacitor are all grounded.

[0036] In a third aspect, the present invention provides a lidar, including the driving circuit of the vcsel laser as described above.

[0037] In the solution of this application, a switching chip including a first switching circuit to an Nth switching circuit is provided, which can achieve stable power supply. Specifically, the input ends of the first switching circuit to the Nth switching circuit are all connected to the MCU controller, so that the MCU controller controls the first switching circuit to the Nth switching circuit to enter the working state one by one. Among them, N is a positive integer. In a single working cycle, only a single switching circuit among the first switching circuit to the Nth switching circuit can be in the working state. It can be seen that the solution of this application can support the occasions of pure solid-state lidar that requires addressing without mechanical rotating parts. The first ends of the first vcsel laser to the Nth vcsel laser are respectively connected to the output ends of the first switching circuit to the Nth switching circuit; the second ends of the first vcsel laser to the Nth vcsel laser are all connected to the first end of the GaN switch, and the second end of the GaN switch is grounded. It can be seen that during the period when the mth switching circuit outputs a high voltage (second voltage), that is, in a single working cycle, the GaN switch needs to be turned on, and the connected mth vcsel laser is turned on and emits light. In the solution of this application, the input end of the switch driver is connected to the controller, and the output end of the switch driver is connected to the control end of the GaN switch, so that under the control of the MCU controller, in a single working cycle, by sending M trigger pulses, the GaN switch is continuously switched between the on and off states. The switching chip and the driving circuit of the vcsel laser provided by this application control one or more of the N switching circuits to conduct, so as to apply a high voltage (such as 60v) to the anode of the laser. That is, in a single working cycle, then control the GaN switch to conduct, so that the connected vcsel laser is turned on and emits light, so as to achieve the utility model purpose of providing a high-power power supply for the laser and being able to light up the lasers in multiple channels at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0039] Figure 1 FIG. is a schematic structural diagram of a high-voltage switching chip provided by a specific embodiment of the present invention;

[0040] Figure 2 FIG. is a schematic structural diagram of a switching circuit provided by a specific embodiment of the present invention;

[0041] Figure 3Schematic diagram of the control circuit provided by a specific embodiment of the present utility model;

[0042] Figure 4 Schematic diagram of the LDO provided by a specific embodiment of the present utility model;

[0043] Figure 5 Schematic diagram of the driving circuit of the vcsel laser provided by a specific embodiment of the present utility model;

[0044] Figure 6 Schematic diagram of the waveform of relevant signals in a specific embodiment of the present utility model;

[0045] Figure 7 Schematic diagram of the voltage waveform at the output end of the switch circuit in a specific embodiment. Specific embodiment

[0046] The core of the present utility model is to provide a lidar, a driving circuit of a vcsel laser, and a switching chip, which can effectively ensure the power supply stability of the lidar when powering the lidar.

[0047] In order to enable those skilled in the art to better understand the solution of the present utility model, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts shall fall within the protection scope of the present utility model.

[0048] Please refer to Figure 1 , Figure 1 Schematic diagram of the high-voltage switching chip provided by a specific embodiment of the present utility model. The high-voltage switching chip may include: a bandgap reference source 10, an LDO 20, a register 30, a first switching circuit to an Nth switching circuit.

[0049] The bandgap reference source 10 is used to provide an input voltage for the LDO 20;

[0050] The LDO 20 is used to provide a first voltage for the first switching circuit to the Nth switching circuit;

[0051] The register 30 is used to store the control signals at the input ends of the first switching circuit to the Nth switching circuit;

[0052] The first switch circuit to the Nth switch circuit are used to control the output of each switch circuit according to the output of register 30. When the control signal is at a high level, the output of the switch circuit is the second voltage. When the control signal is at a low level, the output of the switch circuit is 0V; the second voltage is an externally input voltage, the second voltage is greater than the first voltage, the second voltage is greater than 50V, and the first voltage is greater than 3.3V;

[0053] In the solution of this application, there is 1 switch chip including the first switch circuit to the Nth switch circuit, which can achieve stable power supply. The value of N can be set according to needs and is usually a positive integer greater than 10. At the same time, the output of 1 or more switch circuits among the first switch circuit to the Nth switch circuit is the second voltage.

[0054] The bandgap reference source 10 is a circuit used to provide a reference voltage or reference current, and has the advantage of being almost independent of process, temperature changes, etc. In the solution of this application, the bandgap reference source 10 is used to provide an input voltage to the LDO 20 (Low Dropout Regulator). Figure 1 In this, the enable terminal of the bandgap reference source 10 is denoted as CHIP_EN, its power supply terminal and ground terminal are respectively denoted as VDD33 and VSS33, and the input voltage provided by the bandgap reference source 10 to the LDO 20 is denoted as VREF. The specific voltage level can be set and adjusted according to actual needs.

[0055] The LDO 20 can output a stable voltage. In the solution of this application, the LDO 20 is used to provide the first voltage to the first switch circuit to the Nth switch circuit to ensure the stability of the first voltage received by the first switch circuit to the Nth switch circuit. In addition, in actual applications, the input voltage provided by the bandgap reference source 10 to the LDO 20 is usually 3.3V, and the LDO 20 usually boosts the voltage to a certain extent. Therefore, in actual applications, the first voltage is usually greater than 3.3V, for example, specifically 5V.

[0056] The states of the first switch circuit to the Nth switch circuit can each be determined by the value in register 30, that is, the value in register 30 determines the control signal at the input end of the first switch circuit to the Nth switch circuit, and the value in register 30 can be read and written by the MCU controller. For example, in actual applications, Figure 1 The shown communication circuit can specifically be a communication circuit based on SPI (Serial Peripheral Interface) or I2C (Inter-Integrated Circuit). The MCU controller can configure the value in register 30 through the communication circuit to control the states of each switch circuit.

[0057] The first switch circuit to the Nth switch circuit can all control their own outputs according to the control signal of the register 30. The specific structures of the first switch circuit to the Nth switch circuit can be set and adjusted according to actual needs. However, it can be understood that the functional requirements of the first switch circuit to the Nth switch circuit in the solution of this application need to be met. That is, for any one of these N switch circuits, if the control signal of this switch circuit is at a high level, the output of this switch circuit is the second voltage. The second voltage is an externally input voltage and is a high voltage. Moreover, since the solution of this application is usually applied in lidar and has relatively high requirements for power, the second voltage is usually greater than 50V. In Figure 1 In the example of, the second voltage provided to the first switch circuit to the Nth switch circuit is denoted as HV60, indicating that the second voltage is a high voltage of 60V. 60V is only an example, and higher or lower voltages can be set according to measurement needs. For example, if a farther distance needs to be measured, a higher voltage is required. Conversely, when measuring a short distance, a lower voltage is required.

[0058] Correspondingly, if the control signal of this switch circuit is at a low level, the output of this switch circuit needs to be 0V. And in Figure 1 In the example of, "x32" represents that there are a total of 32 switch circuits, that is, N = 32. OUT<31:0> represents the outputs of the first switch circuit to the Nth switch circuit respectively. 32 is only an example. Each channel can be connected to the anodes of one or more lasers. For the sake of simplicity of description, the output of the switch circuit of each channel in this application is connected to the anode of one laser.

[0059] In a specific embodiment of the present utility model, the structures of the first switch circuit to the Nth switch circuit are the same, which is convenient for reducing production and maintenance costs. And any one of the first switch circuit to the Nth switch circuit includes: a control circuit 50, a first NMOS switch tube MN1, a second NMOS switch tube MN2, a first capacitor C01, and an anti-backflow circuit 40; the gates of the first NMOS switch tube MN1 and the second NMOS switch tube MN2 are respectively connected to the first output terminal and the second output terminal of the control circuit 50. The conduction states of the first NMOS switch tube MN1 and the second NMOS switch tube MN2 are opposite, and when the second NMOS switch tube MN2 is conducting, the output of this switch circuit is the second voltage; the source of the first NMOS switch tube MN1 is grounded, the drain of the first NMOS switch tube MN1 is respectively connected to the source of the second NMOS switch tube MN2 and the second end of the first capacitor C01, and the connection end is used as the output terminal of the switch circuit; the drain of the second NMOS switch tube MN2 is connected to the second voltage;

[0060] A first end of the first capacitor C01 is connected to an output end of the backflow prevention circuit 40 , and an input end of the backflow prevention circuit 40 is connected to a first voltage.

[0061] In some cases, the switching circuit required by the present application is realized based on the series connection of PMOS switch tubes and NMOS switch tubes. However, the PMOS switch tube on the high-voltage side needs to occupy a large surface area, which is not conducive to the miniaturization of the chip.

[0062] In this implementation mode, please refer to Figure 2 , is based on the series connection of two NMOS switch tubes to realize the switch circuit required by this application. Specifically, the first NMOS switch tube MN1 is set on the low voltage side, and its gate is connected to the first output terminal of the control circuit 50, denoted as LSG, and the second NMOS switch tube MN2 is set on the high voltage side, and its gate is connected to the second output terminal of the control circuit 50, denoted as HSG, and the drain of the second NMOS switch tube MN2 needs to be connected to the second voltage, which is a high voltage. When the first NMOS switch tube MN1 is turned on, the second NMOS switch tube MN2 is turned off. At this time, the output of the switch circuit is 0v, that is, Figure 2 VOUT in is 0v. At this time, the first voltage charges the first capacitor C01 through the anti-backflow circuit 40. For example, in the above example, the first voltage provided by LDO20 is specifically 5v, so the upper plate voltage of the first capacitor C01 is 5v. When the second NMOS switch tube MN2 is turned on, the first NMOS switch tube MN1 is turned off. At this time, the output of the switch circuit is 60v, that is, Figure 2 VOUT in is now 60v. And since the capacitor voltage cannot change suddenly, the upper plate voltage of the first capacitor C01 is 60+5=65v. In addition, it can be understood that since the anti-backflow circuit 40 is set, the upper plate voltage of the first capacitor C01 will not flow back to the LDO 20 of the previous stage.

[0063] The specific structure of the anti-backflow circuit 40 can be set according to actual needs. For example, in one embodiment, the anti-backflow circuit 40 can be a diode. The cathode of the diode serves as the output end of the anti-backflow circuit 40, and the anode of the diode serves as the input end of the anti-backflow circuit 40. When a diode is used to implement the anti-backflow circuit 40, the structure is simple and easy to implement. In another embodiment, the anti-backflow circuit 40 can be a PMOS switch tube, the source of which is connected to the first voltage, the drain is connected to the first end of the first capacitor C01, and the gate is connected to the third output end of the control circuit 50, and the on and off states of the PMOS switch tube and the second NMOS switch tube MN2 are opposite, that is, the function of the anti-backflow circuit 40 of the present application can be achieved. Compared with the use of a diode, the solution using a PMOS switch tube has almost no conduction voltage drop, so that no additional power consumption is generated.

[0064] The specific circuit structure of the control circuit 50 can be various, as long as it can control the on-off states of the first NMOS switch tube MN1 and the second NMOS switch tube MN2 based on the value in the register 30. For example, in a specific embodiment of the present invention, reference can be made to Figure 3 , the control circuit 50 may include a single / double conversion circuit 51, a first buffer circuit 53, and a second buffer circuit 52; the single / double conversion circuit 51 is configured to receive the control signal output by the register 30. The first output terminal of the single / double conversion circuit 51 is connected to the input terminal of the first buffer circuit 53, and the second output terminal of the single / double conversion circuit 51 is connected to the input terminal of the second buffer circuit 52; the output terminal of the first buffer circuit 53 is connected to the first NMOS switch tube MN1; the output terminal of the second buffer circuit 52 is connected to the second NMOS switch tube MN2; when the control signal is at a low level, the output of the first buffer circuit 53 is at a high level, the output of the second buffer circuit 52 is at a low level, the first NMOS tube is turned on, and the second NMOS tube is turned off; when the control signal is at a high level, the output of the first buffer circuit 53 is at a low level, the output of the second buffer circuit 52 is at a high level, the first NMOS tube is turned off, and the second NMOS tube is turned on.

[0065] In this embodiment, reference can be made to Figure 3 , the single / double conversion circuit 51 can output two signals with opposite levels based on the control signal IN output by the register 30, that is, Figure 3 the INP and INN shown in. For example, in a specific situation, for the single / double conversion circuit 51 in any one switch circuit, when the control signal IN output by the register 30 is 0v, the signal INN output by the first output terminal of the single / double conversion circuit 51 is 5v, and the signal INP output by the second output terminal of the single / double conversion circuit 51 is 0v. On the contrary, when the control signal IN output by the register 30 is 5v, the signal INN output by the first output terminal of the single / double conversion circuit 51 is 0v, and the signal INP output by the second output terminal of the single / double conversion circuit 51 is 5v.

[0066] This embodiment takes into account that directly driving and controlling the first NMOS switch tube MN1 and the second NMOS switch tube MN2 based on the single / double conversion circuit 51 may not have sufficient current driving ability. For this reason, for the second NMOS switch tube MN2, specifically, it is driven by the first buffer circuit 53. The signal INN output by the first output terminal of the single / double conversion circuit 51 is connected to the first buffer circuit 53, so as to drive the first NMOS switch tube MN1 through the first buffer circuit 53. For example, in a specific embodiment, when INN is 0v, the signal LSG output by the output terminal of the first buffer circuit 53 is 0v, and when INN is 5v, the signal LSG output by the output terminal of the first buffer circuit 53 is 5v. Figure 3VDD in it represents the first voltage of 5V.

[0067] Similarly, in this embodiment, the second NMOS switch tube MN2 is driven based on the second buffer circuit 52. In addition, it should be noted that the specific structures of the first buffer circuit 53 and the second buffer circuit 52 can be set and adjusted according to actual needs. For example, in a specific embodiment, through the structural design of the first buffer circuit 53, when the input INP of the first buffer circuit 53 is at a high level (e.g., 5V), the output HSG of the first buffer circuit 53 can be equal to VB (65V), and when the input INP of the first buffer circuit 53 is at a low level (0V), the output HSG of the first buffer circuit 53 can be equal to VS (0V), that is, equal to VOUT. In Figure 3 the example of, VB and VS are marked, which are two external ports of the first buffer circuit 53, one of which is connected to the upper plate of the first capacitor C01, and the other is connected to the lower plate of the first capacitor C01.

[0068] In a specific embodiment of the present utility model, reference can be made to Figure 4 , the LDO 20 includes: an error amplifier 21, a second capacitor C02, a first resistor R1, a second resistor R2, and a PMOS switch tube Q0; for the error amplifier 21, its inverting input terminal is used to connect to the output terminal of the bandgap reference source 10, its non-inverting input terminal is respectively connected to the second end of the first resistor R1 and the first end of the second resistor R2, and its output terminal is connected to the gate of the PMOS switch tube. The first end of the first resistor R1 is connected to the drain of the PMOS switch tube Q0 and the connection end is used as the output of the LDO 20, the source of the PMOS switch tube Q0 is connected to the second voltage, and the second end of the second resistor R2 is grounded; the first end of the second capacitor C02 is connected to the output of the LDO 20, and the second end of the second capacitor C02 is grounded.

[0069] The input of the LDO 20 in this embodiment is the voltage VREF output by the bandgap reference source 10, VREF is connected to the inverting input terminal of the error amplifier 21, and the non-inverting input terminal of the error amplifier 21 is connected to the proportional feedback of the output voltage. Therefore, the first voltage output by the error amplifier 21 = (1 + R1 / R2) × VREF. It can be seen that by selecting an appropriate resistance ratio and VREF, the voltage value of the required first voltage can be obtained. For example, the first voltage in the above example is 5V. And in the LDO 20 of this embodiment, the second capacitor C02 can be charged, so it is beneficial to ensure the stability of the first voltage.

[0070] In a specific embodiment of the present utility model, any one of the first switch circuit to the Nth switch circuit includes: a short-circuit protection circuit for outputting an alarm signal when detecting a short circuit in the switch circuit where it is located.

[0071] For reference, Figure 1 , Figure 1 the SCP in Figure 1 can be a short - circuit protection circuit in a certain switching circuit. When detecting any type of short - circuit in the switching circuit where it is located, it outputs an alarm signal ERROR. In addition, in practical applications, after the MCU controller receives the alarm signal, it can execute preset countermeasures, such as automatically shutting down all switching circuits to ensure circuit safety.

[0072] For reference, Figure 5 , this application also discloses a driving circuit for a vcsel laser, which may include a switching chip 61, an MCU controller 62, a GaN switch M0, and a switch driver 63 as described in any of the above embodiments.

[0073] The switching chip 61 includes N output ports. The first output port to the Nth output port are respectively connected to the first ends of the first vcsel laser to the Nth vcsel laser; the second ends of the first vcsel laser to the Nth vcsel laser are all connected to the first end of the GaN switch M0, and the second end of the GaN switch M0 is grounded; the MCU controller 62 is connected to the input end of the register 30 of the switching chip; the input end of the switch driver 63 is connected to the MCU controller 62, and the output end of the switch driver 63 is connected to the control end of the GaN switch M0; the GaN switch M0 is used to continuously switch the on - off state under the control of M trigger pulses issued by the MCU controller 62, so that the first to the Nth vcsel lasers emit light.

[0074] In Figure 4 the embodiment, OUT0 to OUT32 respectively represent the outputs of the first switching circuit to the 32nd switching circuit in the switching chip 61, and D0 to D31 respectively represent the first vcsel laser to the 32nd vcsel laser, that is Figure 4 it is still described by taking N = 32 as an example in Figure 4 .

[0075] Combined with the above description, the outputs of one or more switching circuits among the first switching circuit to the Nth switching circuit are the second voltage, and from Figure 4 it can be known that the vcsel laser connected to the corresponding switching circuit can conduct and emit light only when the GaN switch M0 is conducting.

[0076] The switching chip and the driving circuit of the VCSEL laser provided by this application control one or more of the N switching circuits to conduct, so as to apply a high voltage (such as 60V) to the anode of the laser. That is, within a single working cycle, the GaN switch is then controlled to conduct, so that the connected VCSEL laser conducts and emits light, so as to achieve the utility model purpose of providing a high-power power supply for the laser and being able to light up the laser simultaneously in multiple channels.

[0077] In Figure 6 the example, first, the output terminal of the first switching circuit outputs a second voltage, so OUT0 is at a high level. For example, according to the above example, OUT0 is specifically a high voltage of 60V. During this period, the control terminal signal TRIG of the GaN switch M0 is specifically a continuous pulse signal, so that the GaN switch M0 continuously switches between on and off states. Therefore, the first VCSEL laser D0 emits light intermittently, so that the capacitor arranged at the output terminal position of the first switching circuit can be charged, ensuring that the laser power emitted by the first VCSEL laser remains stable at a high power during the period when OUT0 is at a high level.

[0078] Similarly, then the output terminal of the second switching circuit outputs a second voltage, so OUT1 is at a high level. Since the principle is the same as above, it will not be repeated here.

[0079] In a specific embodiment of the present utility model, it may further include: the first voltage stabilizing capacitor to the Nth voltage stabilizing capacitor; the first ends of the first voltage stabilizing capacitor to the Nth voltage stabilizing capacitor are respectively connected to the first ends of the first VCSEL laser to the Nth VCSEL laser, and the second ends of the first voltage stabilizing capacitor to the Nth voltage stabilizing capacitor are all grounded.

[0080] As described above, in the solution of this application, the GaN switch M0 does not conduct continuously but switches continuously, so that the laser emits light intermittently. During the period when it does not emit light, the output terminal voltage of the switching circuit can rise due to capacitor charging to ensure the power of the next laser emission. In this regard, in this embodiment, by setting the first voltage stabilizing capacitor to the Nth voltage stabilizing capacitor, the stability of the output terminal voltage of the switching circuit is further ensured. Refer to Figure 4 and denote the capacitors arranged at the output terminal positions of the first switching circuit to the Nth switching circuit as C0 to C31 in sequence.

[0081] Refer to Figure 7, in a specific embodiment, during the operation of the driving circuit of the VCSEL laser, within any working cycle, the schematic diagram of the voltage waveform at the output end of the switching circuit can be seen. It can be seen that when the VCSEL laser emits light, the voltage at the output end of the switching circuit will slightly drop from 60V. However, when the VCSEL laser does not emit light, the voltage at the output end of the switching circuit rises.

[0082] That is to say, within a single working cycle, the VCSEL laser is not continuously powered. This is because in this application, it is considered that most current lidars use the dTOF scheme for ranging, that is, the VCSEL laser is a laser emitter. Even if the laser emission time is very short, the output voltage will still drop. Therefore, in this application, the switching circuit is continuously switched between on and off states, which makes the laser emit light intermittently. During the period when the laser does not emit light, the voltage at the output end of the switching circuit can rise due to capacitor charging. This can effectively ensure the power of the next laser emission. In this way, in a single working cycle, the laser power emitted by the laser emitter can maintain a stable high power. Therefore, when the switching chip applying the solution of this application powers the lidar, it can effectively ensure the power supply stability of the lidar.

[0083] Corresponding to the above embodiments of the driving circuit of the VCSEL laser, the embodiment of the present utility model further provides a lidar, which may include the driving circuit of the VCSEL laser in any of the above embodiments.

[0084] It should also be noted that in this application, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0085] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in the present application can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present utility model.

[0086] Specific examples are applied in the present application to elaborate on the principles and implementation manners of the present utility model. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present utility model. It should be pointed out that for those of ordinary skill in the art of this technology, without departing from the principle of the present utility model, several improvements and modifications can be made to the present utility model, and these improvements and modifications also fall within the protection scope of the present utility model.

Claims

1. A high voltage switch chip, characterized in that: include: A bandgap reference source, an LDO, a register, and a first switching circuit to an Nth switching circuit; The bandgap reference source is used to provide an input voltage to the LDO; The LDO is used to provide a first voltage to the first to Nth switch circuits; The register is used to store the control signal from the first switch circuit to the input end of the Nth switch circuit; The first switch circuit to the Nth switch circuit are used to control the output of each switch circuit according to the output of the register, when the control signal is at a high level, the output of the switch circuit is a second voltage, when the control signal is at a low level, the output of the switch circuit is 0v; the second voltage is an external input voltage, the second voltage is greater than the first voltage, the second voltage is greater than 50v, and the first voltage is greater than 3.3v; Wherein, N is a positive integer greater than 10, and at the same time, the output of one or more switch circuits from the first switch circuit to the Nth switch circuit is the second voltage.

2. The switch chip according to claim 1, characterized in that: The structures of the first switch circuit to the Nth switch circuit are the same, and any one of the first switch circuit to the Nth switch circuit includes: A control circuit, a first NMOS switch tube, a second NMOS switch tube, a first capacitor and an anti-backflow circuit; The gate of the first NMOS switch tube and the gate of the second NMOS switch tube are connected to the first output terminal of the control circuit and the second output terminal of the control circuit respectively, the conduction states of the first NMOS switch tube and the second NMOS switch tube are opposite, and when the second NMOS switch tube is turned on, the output of the switch circuit is the second voltage; The source of the first NMOS switch tube is grounded, the drain of the first NMOS switch tube is connected to the source of the second NMOS switch tube and the second end of the first capacitor respectively, and the connecting end serves as the output end of the switch circuit; the drain of the second NMOS switch tube is connected to the second voltage; The first end of the first capacitor is connected to the output end of the anti-backflow circuit, and the input end of the anti-backflow circuit is connected to the first voltage.

3. The switch chip according to claim 2, characterized in that: The anti-backflow circuit is a diode; The cathode of the diode serves as the output end of the anti-backflow circuit, and the anode of the diode serves as the input end of the anti-backflow circuit.

4. The switch chip according to claim 2, characterized in that: The control circuit includes a single-to-double conversion circuit, a first buffer circuit and a second buffer circuit; The single-to-double conversion circuit is used to receive the control signal output by the register, the first output end of the single-to-double conversion circuit is connected to the input end of the first buffer circuit, and the second output end of the single-to-double conversion circuit is connected to the input end of the second buffer circuit; The output end of the first buffer circuit is connected to the first NMOS switch tube; The output end of the second buffer circuit is connected to the second NMOS switch tube; When the control signal is at a low level, the output of the first buffer circuit is at a high level, the output of the second buffer circuit is at a low level, the first NMOS transistor is turned on, and the second NMOS transistor is turned off; When the control signal is at a high level, the output of the first buffer circuit is at a low level, the output of the second buffer circuit is at a high level, the first NMOS transistor is disconnected, and the second NMOS transistor is turned on.

5. The switch chip according to claim 1, characterized in that: The LDO includes: an error amplifier, a second capacitor, a first resistor, a second resistor and a PMOS switch tube; The error amplifier, whose inverting input end is used to connect to the output end of the bandgap reference source, whose non-inverting input end is respectively connected to the second end of the first resistor and the first end of the second resistor, and whose output end is connected to the gate of the PMOS switch tube; The first end of the first resistor is connected to the drain of the PMOS switch tube and the connection end serves as the output of the LDO, the source of the PMOS switch tube is connected to the second voltage, and the second end of the second resistor is grounded; the first end of the second capacitor is connected to the output of the LDO, and the second end of the second capacitor is grounded.

6. The switch chip according to claim 1, characterized in that: Any one of the first to Nth switch circuits includes a short-circuit protection circuit for outputting an alarm signal when a short circuit is detected in the switch circuit in which the circuit is located.

7. A driving circuit for a vcsel laser, characterized in that: include: The switch chip, MCU controller, GaN switch and switch driver according to any one of claims 1 to 6; The switch chip includes N output ports, the first output port to the Nth output port are respectively connected to the first end of the first vcsel laser to the first end of the Nth vcsel laser; the second end of the first vcsel laser to the second end of the Nth vcsel laser are all connected to the first end of the GaN switch, and the second end of the GaN switch is grounded; The MCU controller is connected to the input end of the register of the switch chip; The input end of the switch driver is connected to the MCU controller, and the output end of the switch driver is connected to the control end of the GaN switch; The GaN switch is used to continuously switch the on and off states under the control of M trigger pulses issued by the MCU controller, so that the first to the Nth vcsel lasers emit light.

8. The driving circuit of the vcsel laser according to claim 7, characterized in that: Also included: a 1st voltage stabilizing capacitor to an Nth voltage stabilizing capacitor; The first end of the first voltage-stabilizing capacitor to the first end of the Nth voltage-stabilizing capacitor are respectively connected to the first end of the first vcsel laser to the first end of the Nth vcsel laser, and the second end of the first voltage-stabilizing capacitor to the second end of the Nth voltage-stabilizing capacitor are both grounded.

9. A laser radar, characterized in that: A driving circuit comprising the vcsel laser as claimed in claim 7 or 8.

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