Analog voltage signal isolation acquisition circuit

Abstract

The utility model discloses an analog voltage signal isolation acquisition circuit. The circuit comprises an APC unit, a digital isolation unit, a shaping filtering unit, an operational amplifier output unit and an MCU acquisition unit. The APC unit comprises a filter circuit, a voltage signal to PWM converter U1 and a decoupling capacitor C2. The digital isolation unit comprises a third capacitor C3, a fourth capacitor C4 and a digital isolator U2; the shaping filtering unit comprises a second resistor R2, a fifth capacitor C5, a third resistor R3 and a sixth capacitor C6; the operational amplifier output unit comprises an operational amplifier U3, and the MCU acquisition unit comprises a chip U4. According to the utility model, the acquired analog voltage signals are more complete and stable, are not easy to be influenced by interference signals, have a fast response rate and a simple circuit structure, and have a great practical value.

Description

Technical Field

[0001] The utility model relates to the technical field of automatic control, and specifically, to an analog voltage signal isolation acquisition circuit. Background Art

[0002] In the field of signal processing, some signals need to be isolated to prevent some external interference signals from entering the system, such as the interference of conducted emissions (CE), which may cause the system to malfunction.

[0003] In practical applications, the power supply end of the control system is often high-voltage 220V AC, while the sampling end requires low voltage, and the ground wire needs to be isolated from the high voltage, which poses difficulties for the complete sampling of analog voltage signals. A relatively common method is to first convert the analog voltage signal into a single-channel PWM (pulse width modulation) signal, then isolate and output the signal through an optocoupler, and finally convert it back into a voltage signal. This method has high requirements for the response rate of the optocoupler, the PWM signal is easily interfered, and the output voltage signal is not stable enough and needs to be calibrated by software. Summary of the Utility Model

[0004] The purpose of the utility model is to provide an analog voltage signal isolation acquisition circuit to solve the problem that the output voltage signal in the prior art is not stable enough and needs to be calibrated by software.

[0005] To achieve the above purpose, the utility model adopts the following technical solutions:

[0006] An analog voltage signal isolation acquisition circuit, the circuit includes an APC unit, a digital isolation unit, a shaping and filtering unit, an operational amplifier output unit, and an MCU acquisition unit;

[0007] The APC unit includes a filtering circuit, a voltage signal to PWM converter U1, and a decoupling capacitor C2; the digital isolation unit includes a third capacitor C3, a fourth capacitor C4, and a digital isolator U2; the shaping and filtering unit includes a second resistor R2, a fifth capacitor C5, a third resistor R3, and a sixth capacitor C6;

[0008] The operational amplifier output unit includes an operational amplifier U3, and the MCU acquisition unit includes a chip U4.

[0009] Further, the filtering circuit in the APC unit includes a first resistor R1 and a first capacitor C1. One end of the first resistor R1 is connected to the input end of the analog voltage signal VIN, the other end of the first resistor R1 is connected to the first capacitor C1 and the pin 3 of the voltage signal to PWM converter U1, and the other end of the first capacitor C1 is connected to the ground wire GNDA.

[0010] Further, pin 5 of the voltage signal to PWM converter U1 is connected to ground GNDA, pin 6 of the voltage signal to PWM converter U1 is connected to pin 3 of the digital isolator U2, pin 7 of the voltage signal to PWM converter U1 is connected to pin 2 of the digital isolator U2, and pin 8 of the voltage signal to PWM converter U1 is connected to power supply VDDA;

[0011] Pin 8 of the voltage signal to PWM converter U1 is also connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to ground GNDA.

[0012] Further, the second capacitor C2 is a decoupling capacitor for the power supply VDDA of the voltage signal to PWM converter U1.

[0013] Further, pin 1 of the digital isolator U2 is connected to power supply VDDA, pin 1 of the digital isolator U2 is also connected to one end of the third capacitor C3, and the other end of the third capacitor C3 is connected to ground GNDA;

[0014] Pin 4 of the digital isolator U2 is connected to ground GNDA, pin 5 of the digital isolator U2 is connected to ground GNDB, pin 8 of the digital isolator U2 is connected to power supply VDDB, pin 8 of the digital isolator U2 is also connected to one end of the fourth capacitor C4, and the other end of the fourth capacitor C4 is connected to ground GNDB;

[0015] Pin 6 of the digital isolator U2 is connected to one end of the third resistor R3, the other end of the third resistor R3 is connected to one ends of the sixth capacitor C6 and the fifth capacitor C5, the other end of the sixth capacitor C6 is connected to ground GNDB, pin 7 of the digital isolator U2 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the fifth capacitor C5, and the sixth capacitor C6 and the fifth capacitor C5 are connected to each other.

[0016] Further, the third capacitor C3 is a decoupling capacitor for the power supply VDDA of the digital isolator U2, and the fourth capacitor C4 is a decoupling capacitor for the power supply VDDB of the digital isolator U2.

[0017] Further, the third resistor R3, the sixth capacitor C6 and the fifth capacitor C5 are jointly connected to pin 3 of the operational amplifier U3, pin 4 of the operational amplifier U3 is connected to ground GNDB, pin 8 of the operational amplifier U3 is connected to power supply VDDB, and pins 1 and 2 of the operational amplifier U3 are connected to each other.

[0018] Further, pin 1 and pin 2 of the operational amplifier U3 are connected to the input pin AD of the chip U4 of the MCU main control unit. The pin VCC of the chip U4 is connected to the power supply VDDB, and the pin GND of the chip U4 is connected to the ground wire GNDB.

[0019] The beneficial effects of the present utility model are as follows: In the same application scenario, the analog voltage signal collected by the present utility model is more complete and stable, not easily affected by interference signals, has a relatively fast response rate, and has a simple circuit structure, with great practical value. Description of the Drawings

[0020] Figure 1 is the principle block diagram of the present utility model;

[0021] Figure 2 is the circuit schematic diagram of the power supply module of the present utility model. Detailed Embodiments

[0022] Refer to Figure 1 , the principle block diagram of an analog voltage signal isolation acquisition circuit disclosed by the present utility model. The circuit includes an APC unit, a digital isolation unit, a shaping and filtering unit, an operational amplifier output unit, and an MCU acquisition unit.

[0023] After the analog voltage signal is input, it first passes through the APC unit to convert the analog voltage signal into two complementary PWM signals and outputs them through the digital isolation unit. After the two isolated PWM signals pass through the shaping and filtering unit, the output voltage signal passes through the operational amplifier output unit to output a stable voltage signal, which is the same as the input signal of the analog voltage. Finally, it is input to the MCU unit to realize signal acquisition.

[0024] Figure 1 and Figure 2 In Figure 2 , the isolation side 1 and the isolation side 2 are respectively connected to two independent isolation power supplies. As shown in

[0025] For the circuit schematic diagram of the power supply module of the complete analog voltage signal isolation acquisition circuit of the present utility model, specifically as shown in Figure 2 , the APC unit includes a filter circuit, a voltage signal to PWM converter U1, and a decoupling capacitor C2. The function of the APC unit is to generate two complementary PWM signals with a fixed frequency and a duty cycle that linearly changes with the input analog voltage signal.

[0026] The analog signal VIN is connected to one end of the first resistor R1. The other end of the first resistor R1 is connected to one end of the first capacitor C1 and pin 3 of the voltage signal to PWM converter U1. The first resistor R1 and the first capacitor C1 form a filtering circuit, which can make the voltage signal of the analog signal VIN smoother. The other end of the first capacitor C1 is connected to the ground wire GNDA.

[0027] Pin 5 of the voltage signal to PWM converter U1 is connected to the ground wire GNDA. Pin 6 of the voltage signal to PWM converter U1 is connected to pin 3 of the digital isolator U2. The PWMA1 signal formed by the voltage signal to PWM converter U1 is output from pin 6. Pin 7 of the voltage signal to PWM converter U1 is connected to pin 2 of the digital isolator U2. The complementary signal PWMB1 signal formed by the voltage signal to PWM converter U1 is output from pin 7. The PWMA1 signal and the PWMB1 signal are two PWM digital signals with fixed frequencies.

[0028] Pin 8 of the voltage signal to PWM converter U1 is connected to the power supply VDDA. Pin 8 of the voltage signal to PWM converter U1 is also connected to one end of the second capacitor C2. The other end of the second capacitor C2 is connected to the ground wire GNDA.

[0029] The second capacitor C2 is a decoupling capacitor for the power supply VDDA of the voltage signal to PWM converter U1.

[0030] The digital isolation unit includes a third capacitor C3, a fourth capacitor C4 and a digital isolator U2. The digital isolation unit isolates the input digital signal and outputs it, playing an isolation role.

[0031] Pin 2 of the digital isolator U2 is connected to pin 7 of the voltage signal to PWM converter U1 to complete the input of the complementary signal PWMB1. Pin 3 of the digital isolator U2 is connected to pin 6 of the voltage signal to PWM converter U1 to complete the input of the PWMA1 signal. The isolated signal PWMA2 is output from pin 6 of the digital isolator U2, and the isolated complementary signal PWMB2 is output from pin 7 of the digital isolator U2.

[0032] Pin 1 of the digital isolator U2 is connected to the power supply VDDA. Pin 1 of the digital isolator U2 is also connected to one end of the third capacitor C3. The other end of the third capacitor C3 is connected to the ground wire GNDA. Pin 4 of the digital isolator U2 is connected to the ground wire GNDA. Pin 5 of the digital isolator U2 is connected to the ground wire GNDB. Pin 8 of the digital isolator U2 is connected to the power supply VDDB. Pin 8 of the digital isolator U2 is also connected to one end of the fourth capacitor C4. The other end of the fourth capacitor C4 is connected to the ground wire GNDB.

[0033] Pin 6 of the digital isolator U2 is connected to one end of the third resistor R3. The other end of the third resistor R3 is connected to one end of the sixth capacitor C6 and the fifth capacitor C5. The other end of the sixth capacitor C6 is connected to the ground wire GNDB. Pin 7 of the digital isolator U2 is connected to one end of the second resistor R2. The other end of the second resistor R2 is connected to the fifth capacitor C5, and the sixth capacitor C6 and the fifth capacitor C5 are connected to each other.

[0034] The third capacitor C3 is a decoupling capacitor for the power supply VDDA on the isolated side 1 of the digital isolator U2, and the fourth capacitor C4 is a decoupling capacitor for the power supply VDDB on the isolated side 2 of the digital isolator U2.

[0035] The shaping and filtering unit includes the second resistor R2, the fifth capacitor C5, the third resistor R3, and the sixth capacitor C6. The shaping and filtering unit shapes and filters the two complementary PWM signals after isolation to form a stable voltage signal.

[0036] Pin 6 of the digital isolator U2 is connected to one end of the third resistor R3. The other end of the third resistor R3 is connected to one end of the sixth capacitor C6 and the fifth capacitor C5. The other end of the sixth capacitor C6 is connected to the ground wire GNDB. Pin 7 of the digital isolator U2 is connected to one end of the second resistor R2. The other end of the second resistor R2 is connected to the fifth capacitor C5, and the sixth capacitor C6 and the fifth capacitor C5 are connected to each other.

[0037] The first shaping and filtering circuit composed of the third resistor R3 and the sixth capacitor C6 is used to convert the PWMA2 signal into a voltage signal. The second shaping and filtering circuit composed of the second resistor R2 and the fifth capacitor C5 is used to superimpose the complementary signal PWMB2 onto the voltage signal converted from PWMA2 to eliminate its AC signal, thereby forming a stable voltage signal VOUT1.

[0038] The operational amplifier output unit includes an operational amplifier U3, and the operational amplifier output unit plays the role of signal strengthening and anti-interference ability improvement; the MCU acquisition unit includes a chip U4, and the role of the MCU acquisition unit is to complete the acquisition of the voltage signal.

[0039] The third resistor R3, the sixth capacitor C6, and the fifth capacitor C5 are jointly connected to pin 3 of the operational amplifier U3. Pin 4 of the operational amplifier U3 is connected to the ground wire GNDB. Pin 8 of the operational amplifier U3 is connected to the power supply VDDB. Pins 1 and 2 of the operational amplifier U3 are connected to each other.

[0040] Further, pin 1 and pin 2 of the operational amplifier U3 are connected to the input pin AD of the chip U4 of the MCU main control unit. The pin VCC of the chip U4 is connected to the power supply VDDB, and the pin GND of the chip U4 is connected to the ground wire GNDB.

[0041] The voltage signal VOUT1 is input into pin 3 of the operational amplifier U3 using the operational amplifier U3. The voltage signal VOUT2 is output from pin 1 of the operational amplifier U3. Pins 1 and 2 of the operational amplifier U3 are connected to form a voltage follower. The voltage signal VOUT2 is input into the input pin AD of the chip U4 of the MCU main control unit to complete data acquisition.

[0042] The working principle of the analog voltage signal isolation acquisition circuit of the present utility model is described as follows:

[0043] The first resistor R1 and the first capacitor C1 form a filtering circuit to make the input analog voltage signal of VIN smoother. After the analog voltage signal is input into the voltage signal to PWM converter U1 (model: GP9101) in the APC unit, it is converted into two fixed-frequency PWM digital signals (PWMA1 and PWMB1). The two PWM signals enter the input end of the digital isolator U2 (model: CA-IS3720). Using a dedicated isolation chip can maintain the accurate timing of the signal and improve the anti-interference ability. After the signal passes through the digital isolator U2, it becomes two isolated PWM signals (PWMA2 and PWMB2). PWMA2 is converted into a voltage signal after passing through the first shaping and filtering circuit composed of the third resistor R3 and the sixth capacitor C6. The complementary signal PWMB2 is superimposed on the voltage signal filtered by PWMA2 after passing through the second shaping and filtering circuit composed of the second resistor R2 and the fifth capacitor C5, making it into a more stable voltage signal VOUT1. The operational amplifier U3 (model: OPA2333) outputs the voltage signal VOUT2, and finally this voltage signal is input into the input pin AD sampling port of the MCU to complete the isolation acquisition of the signal.

[0044] It should be noted that the above embodiments are only for illustrating the technical concept and features of the present utility model. The so-called one end, the other end, etc. described therein are all corresponding to the drawings of the present utility model and are not used to limit specific content. The purpose is to enable those skilled in the art to understand the content of the present utility model and implement it accordingly, and it cannot be used to limit the protection scope of the present utility model. All equivalent changes or modifications made according to the spirit of the present utility model should be covered within the protection scope of the present utility model.

Claims

1. An analog voltage signal isolation and acquisition circuit, characterized in that: The circuit includes an APC unit, a digital isolation unit, a shaping filter unit, an operational amplifier output unit and an MCU acquisition unit; The APC unit includes a filter circuit, a voltage signal to PWM converter U1 and a decoupling capacitor C2; the digital isolation unit includes a third capacitor C3, a fourth capacitor C4 and a digital isolator U2; the shaping filter unit includes a second resistor R2, a fifth capacitor C5 and a third resistor R3, a sixth capacitor C6; The operational amplifier output unit includes an operational amplifier U3, and the MCU acquisition unit includes a chip U4.

2. The analog voltage signal isolation and acquisition circuit according to claim 1, characterized in that: The filtering circuit in the APC unit includes a first resistor R1 and a first capacitor C1, one end of the first resistor R1 is connected to the input end of the analog voltage signal VIN, the other end of the first resistor R1 is connected to the first capacitor C1 and the pin 3 of the voltage signal to PWM converter U1, and the other end of the first capacitor C1 is connected to the ground line GNDA.

3. The analog voltage signal isolation and acquisition circuit according to claim 2, characterized in that: Pin 5 of the voltage signal to PWM converter U1 is connected to the ground line GNDA, pin 6 of the voltage signal to PWM converter U1 is connected to pin 3 of the digital isolator U2, pin 7 of the voltage signal to PWM converter U1 is connected to pin 2 of the digital isolator U2, and pin 8 of the voltage signal to PWM converter U1 is connected to the power supply VDDA; The pin 8 of the voltage signal to PWM converter U1 is also connected to one end of a second capacitor C2, and the other end of the second capacitor C2 is connected to a ground line GNDA.

4. The analog voltage signal isolation and acquisition circuit according to claim 3, characterized in that: The second capacitor C2 is a decoupling capacitor of the power supply VDDA of the voltage signal to PWM converter U1.

5. The analog voltage signal isolation and acquisition circuit according to claim 3, characterized in that: Pin 1 of the digital isolator U2 is connected to a power supply VDDA, and pin 1 of the digital isolator U2 is also connected to one end of a third capacitor C3, and the other end of the third capacitor C3 is connected to a ground line GNDA; Pin 4 of the digital isolator U2 is connected to the ground line GNDA, pin 5 of the digital isolator U2 is connected to the ground line GNDB, pin 8 of the digital isolator U2 is connected to the power supply VDDB, pin 8 of the digital isolator U2 is also connected to one end of the fourth capacitor C4, and the other end of the fourth capacitor C4 is connected to the ground line GNDB; Pin 6 of the digital isolator U2 is connected to one end of the third resistor R3, the other end of the third resistor R3 is connected to one end of the sixth capacitor C6 and the fifth capacitor C5, the other end of the sixth capacitor C6 is connected to the ground wire GNDB, pin 7 of the digital isolator U2 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the fifth capacitor C5, and the sixth capacitor C6 and the fifth capacitor C5 are connected to each other.

6. The analog voltage signal isolation and acquisition circuit according to claim 5, characterized in that: The third capacitor C3 is a decoupling capacitor of the power supply VDDA of the digital isolator U2 , and the fourth capacitor C4 is a decoupling capacitor of the power supply VDDB of the digital isolator U2 .

7. The analog voltage signal isolation and acquisition circuit according to claim 5, characterized in that: The third resistor R3, the sixth capacitor C6 and the fifth capacitor C5 are commonly connected to the pin 3 of the operational amplifier U3, the pin 4 of the operational amplifier U3 is connected to the ground wire GNDB, the pin 8 of the operational amplifier U3 is connected to the power supply VDDB, and the pins 1 and 2 of the operational amplifier U3 are connected to each other.

8. The analog voltage signal isolation and acquisition circuit according to claim 7, characterized in that: Pins 1 and 2 of the operational amplifier U3 are connected to input pin AD of a chip U4 of the MCU main control unit, a pin VCC of the chip U4 is connected to a power source VDDB, and a pin GND of the chip U4 is connected to a ground wire GNDB.

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