Band-gap reference current source and power-on reset circuit

Abstract

The utility model discloses a band-gap reference current source and a power-on reset circuit, and relates to the technical field of power-on reset circuits. The reset circuit comprises a low-noise current reference circuit and a reference current and power-on reset signal output circuit, and the signal output end of the low-noise current reference circuit is connected with the signal input end of the reference current and power-on reset signal output circuit. The low-noise current reference circuit is used for generating a current signal required by the reference current and power-on reset signal output circuit, and the reference current and power-on reset signal output circuit is used for processing the input current signal and respectively outputting a band-gap reference current signal and a power-on reset signal. According to the low-noise band-gap reference current circuit, the NPN low-noise transistor and the PMOS transistor are adopted to design the low-noise band-gap reference current circuit, substrate noise, 1 / f flicker noise and far-end phase noise introduced by the NMOS transistor are reduced, and the precision is high.

Description

Technical Field

[0001] The utility model relates to the technical field of power-on reset circuits, in particular to a low-noise bandgap reference current and power-on reset circuit with self-starting function. Background Art

[0002] The power-on reset circuit is used to generate a reset signal inside the chip, which is crucial for the normal operation of the chip. For any electronic chip, in order to ensure the stability and accuracy of the chip operation, before the chip starts to work, it generally needs to be reset to make the chip have a definite initial working state. An accurate reset circuit has a great impact on the various working performances of the chip. The power-on reset circuits in the prior art generally have a relatively high noise, resulting in a decrease in accuracy. Summary of the Utility Model

[0003] The technical problem to be solved by the utility model is how to provide a bandgap reference current and power-on reset circuit with low noise and high accuracy.

[0004] To solve the above technical problem, the technical solution adopted by the utility model is: a bandgap reference current source and power-on reset circuit, including a low-noise current reference circuit and a reference current and power-on reset signal output circuit. The signal output end of the low-noise current reference circuit is connected to the signal input end of the reference current and power-on reset signal output circuit. The low-noise current reference circuit is used to generate the current signal required by the reference current and power-on reset signal output circuit. The reference current and power-on reset signal output circuit is used to process the input current signal and output a bandgap reference current signal and a power-on reset signal respectively.

[0005] Further technical solution lies in: the low-noise current reference circuit includes PMOS transistor P1 and PMOS transistor P2. The drain of P1 and the drain of P2 are connected to the power supply. The gates of P1 and P2 are connected and then connected to the signal output end of the low-noise operational amplifier A3. The source of P1 is divided into two paths. The first path is connected to the collector of transistor BP1, and the second path is connected to the inverting input end of A3. The source of P2 is divided into two paths. The first path is connected to the collector of transistor BP2 through resistor R2, and the second path is connected to the non-inverting input end of A3. The emitters of transistor BP1 and transistor BP2 are connected and then grounded through resistor R1. The output end of the low-noise operational amplifier A3 is divided into two paths. The first path is grounded through capacitor C1, and the second path is the signal output end of the low-noise current reference circuit.

[0006] A further technical solution lies in that: the low-noise operational amplifier A3 includes a PMOS transistor P7. The drain of the PMOS transistor P7 is connected to the power supply. The gate and the source of the PMOS transistor P7 are connected and then connected to the collector of an NPN transistor N2 via a resistor R4. The collector of the NPN transistor N2 is connected to the base of the NPN transistor N2. The emitter of the NPN transistor N2 is grounded via a resistor R5. The drains of a PMOS transistor P5 and a PMOS transistor P6 are connected to the power supply. The gates of the PMOS transistor P5 and the PMOS transistor P5 are connected and then connected to the source of the PMOS transistor P5. The source of the PMOS transistor P5 is connected to the collector of an NPN transistor B1. The source of the PMOS transistor P6 is connected to the collector of an NPN transistor B2. The emitters of the NPN transistor B1 and the NPN transistor B2 are connected and then connected to the collector of an NPN transistor N3. The emitter of the NPN transistor N3 is grounded via a resistor R6. The base of the NPN transistor B1 is the non-inverting input terminal of the low-noise operational amplifier A3. The base of the NPN transistor B2 is the inverting input terminal of the low-noise operational amplifier A3. The node between the NPN transistor B2 and the PMOS transistor P6 is the signal output terminal of the low-noise operational amplifier A3.

[0007] A further technical solution lies in that: the reference current and power-on reset signal output circuit includes a PMOS transistor P3 and a PMOS transistor P4. The drains of the PMOS transistor P3 and the PMOS transistor P4 are connected to the power supply. The gate of the PMOS transistor P3 is connected to the drain of an NMOS transistor N1 and the gate of an NMOS transistor N2 and then serves as the signal input terminal of the reference current and power-on reset signal output circuit. The source of the NMOS transistor N2 is the reference current signal output terminal. The source of the NMOS transistor N1 is grounded. The gate of the NMOS transistor N1 is connected to the output terminal of a buffer A2. The source of the PMOS transistor P3 is divided into three paths. The first path is grounded via a resistor R3. The second path is grounded via a capacitor C2. The third path is connected to the input terminal of a Schmitt trigger A1. The output terminal of the Schmitt trigger A1 is connected to the input terminal of the buffer A2. The output terminal of the buffer A2 is connected to the input terminal of a buffer A4. The output terminal of the buffer A4 is the power-on reset signal output terminal.

[0008] The beneficial effects produced by adopting the above technical solutions are as follows: This application uses NPN low-noise transistors and PMOS transistors to design a low-noise bandgap reference current circuit, reducing the substrate noise, 1 / f flicker noise, and remote phase noise introduced by NMOS transistors, and having high precision. This circuit adopts an integrated design and innovatively integrates the power-on reset circuit and the bandgap reference circuit. In order to adapt to this power-on reset circuit, an NMOS transistor is introduced on the basis of the traditional classic Schmitt trigger circuit, and the traditional single-feedback PMOS transistor and single-feedback NMOS transistor are changed to an array structure to increase the design flexibility. Description of the Drawings

[0009] The present utility model will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0010] Figure 1 is the principle block diagram of the circuit according to the embodiment of the present utility model;

[0011] Figure 2 is the schematic diagram of the circuit according to the embodiment of the present utility model;

[0012] Figure 3 is the schematic diagram of the low-noise current reference circuit in the circuit according to the embodiment of the present utility model;

[0013] Figure 4 is the schematic diagram of the low-noise operational amplifier A3 in the circuit according to the embodiment of the present utility model;

[0014] Figure 5 is the schematic diagram of the Schmitt trigger A1 in the circuit according to the embodiment of the present utility model. Specific embodiments

[0015] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the protection scope of the present utility model.

[0016] Many specific details are set forth in the following description in order to provide a thorough understanding of the present utility model, but the present utility model may be practiced in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of the present utility model. Therefore, the present utility model is not limited by the specific embodiments disclosed below.

[0017] As Figure 1 shown, the embodiment of the present utility model discloses a bandgap reference current source and a power-on reset circuit, including a low-noise current reference circuit and a reference current and power-on reset signal output circuit. The signal output end of the low-noise current reference circuit is connected to the signal input end of the reference current and power-on reset signal output circuit. The low-noise current reference circuit is used to generate the current signal required by the reference current and power-on reset signal output circuit. The reference current and power-on reset signal output circuit is used to process the input current signal and output a bandgap reference current signal and a power-on reset signal respectively.

[0018] Further, as Figure 2 and Figure 3As shown, the low-noise current reference circuit includes PMOS transistor P1 and PMOS transistor P2. The drains of P1 and P2 are connected to the power supply. The gates of P1 and P2 are connected and then connected to the signal output terminal of the low-noise operational amplifier A3. The source of P1 is divided into two paths. The first path is connected to the collector of NPN transistor BP1, and the second path is connected to the inverting input terminal of A3. The source of P2 is divided into two paths. The first path is connected to the collector of transistor BP2 through resistor R2, and the second path is connected to the non-inverting input terminal of A3. The emitters of transistor BP1 and transistor BP2 are connected and then grounded through resistor R1. The output terminal of the low-noise operational amplifier A3 is divided into two paths. The first path is grounded through capacitor C1, and the second path is the signal output terminal of the low-noise current reference circuit. The node between the inverting input terminal of the low-noise operational amplifier A3 and PMOS transistor P1 is node E, and the node between the non-inverting input terminal of the low-noise operational amplifier A3 and PMOS transistor P2 is node F.

[0019] Working principle of the low-noise current reference circuit: When two bipolar transistors operate at unequal current densities, the difference in their base-emitter voltages is proportional to the absolute temperature. In this application, a low-noise NPN transistor is used as the bandgap reference, which has lower background noise characteristics and near-end 1 / f flicker noise characteristics. Through deep negative feedback of the gates of PMOS transistor P1 and PMOS transistor P2 by the low-noise operational amplifier A3, it is ensured that the currents flowing through the NPN transistor BP1 branch and the NPN transistor BP2 branch are consistent. In addition, in order to reduce the noise introduced by the operational amplifier, the differential circuit of the low-noise operational amplifier A3 uses NPN transistors, and capacitor C1 plays a role in filtering the feedback node C and stabilizing the low-noise operational amplifier A3.

[0020] As Figure 4As shown, the low-noise operational amplifier A3 includes a PMOS transistor P7. The drain of the PMOS transistor P7 is connected to the power supply. After the gate and the source of the PMOS transistor P7 are connected, they are connected to the collector of an NPN transistor N2 through a resistor R4. The collector of the NPN transistor N2 is connected to the base of the NPN transistor N2. The emitter of the NPN transistor N2 is grounded through a resistor R5. The drains of a PMOS transistor P5 and a PMOS transistor P6 are connected to the power supply. After the gates of the PMOS transistor P5 and the PMOS transistor P5 are connected, they are connected to the source of the PMOS transistor P5. The source of the PMOS transistor P5 is connected to the collector of an NPN transistor B1. The source of the PMOS transistor P6 is connected to the collector of an NPN transistor B2. After the emitters of the NPN transistor B1 and the NPN transistor B2 are connected, they are connected to the collector of an NPN transistor N3. The emitter of the NPN transistor N3 is grounded through a resistor R6. The base of the NPN transistor B1 is the non-inverting input terminal of the low-noise operational amplifier A3. The base of the NPN transistor B2 is the inverting input terminal of the low-noise operational amplifier A3. The node between the NPN transistor B2 and the PMOS transistor P6 is the signal output terminal of the low-noise operational amplifier A3.

[0021] Working principle of the low-noise operational amplifier A3: This operational amplifier is composed of a PMOS transistor P7, an NPN transistor N2, and resistors R4, R5, and R6. Resistors R5 and R6 form the source degeneration circuit of the NPN transistor. The current of this circuit is mainly determined by resistor R4. The NPN transistor N2, resistor R5 and the NPN transistor N3, resistor R6 form a simple current mirror. The copied current ratio is inversely proportional to resistors R5 and R6. The NPN transistor N3, the NPN transistor B1, the NPN transistor B2, and the PMOS transistors P5 and P6 form a classic five-transistor operational amplifier. Compared with the traditional five-transistor operational amplifier of NMOS and PMOS, this circuit has the advantages of simple structure, low 1 / f noise at the input and output near ends, and low background noise at the far ends.

[0022] As Figure 1As shown, the reference current and power-on reset signal output circuit includes PMOS transistor P3 and PMOS transistor P4. The drains of PMOS transistor P3 and PMOS transistor P4 are connected to the power supply. The gate of PMOS transistor P3 is connected to the drain of NMOS transistor N1 and the gate of NMOS transistor N2, and then serves as the signal input terminal of the reference current and power-on reset signal output circuit. The source of NMOS transistor N2 is the reference current signal output terminal; the source of NMOS transistor N1 is grounded, the gate of NMOS transistor N1 is connected to the output terminal of buffer A2. The source of PMOS transistor P3 is divided into three paths. The first path is grounded through resistor R3, the second path is grounded through capacitor C2, and the third path is connected to the input terminal of Schmitt trigger A1. The output terminal of Schmitt trigger A1 is connected to the input terminal of buffer A2. The output terminal of buffer A2 is connected to the input terminal of buffer A4, and the output terminal of buffer A4 is the power-on reset signal output terminal. The node between PMOS transistor P3 and PMOS transistor P4 is node C, the node between PMOS transistor P3 and Schmitt trigger A1 is node A, and the node between buffer A2 and buffer A4 is node B.

[0023] As Figure 5 shown, the Schmitt trigger A1 includes PMOS transistors P8 - P 10 and NMOS transistors N4 - N7. The gates of PMOS transistor P8, PMOS transistor P9, NMOS transistor N4, and NMOS transistor N5 are connected and then serve as the signal input terminal of the Schmitt trigger A1. The source of PMOS transistor P8 is divided into two paths. The first path is connected to the drain of PMOS transistor P9, and the second path is connected to the drain of PMOS transistor P<1>. The source of PMOS transistor P<1> is connected to the drain of PMOS transistor P<2>, and so on, PMOS transistor P <n-1>The source of <n>The drain connection of PMOS transistor P <n>The source of [device] is connected to the drain of NMOS transistor N5. The gate of NMOS transistor N7 is connected to the power supply, and the source of NMOS transistor N7 is grounded;

[0024] The source of PMOS transistor P9 is divided into two paths. The first path is connected to the output terminal of the Schmitt trigger A1, and the second path is connected to the drain of NMOS transistor N6. The source of NMOS transistor N6 is connected to the drain of NMOS transistor N5. The source of NMOS transistor N5 is divided into two paths. The first path is connected to the drain of NMOS transistor N4, and the second path is connected to the drain of NMOS transistor N<1>. The source of NMOS transistor N<1> is connected to the drain of NMOS transistor N<2>, and so on, NMOS transistor N <n-1>The source of <n>The drain connection of PMOS transistor N <n>The source of is connected to the drain of PMOS transistor P 10 The drain of is connected, and the gate of PMOS transistor P 10 The gate of is grounded; the PMOS transistors P<1>-PMOS transistors P <n>The gate of which is connected to NMOS transistors N<1> - NMOS transistor N <n>After the gates are connected, it serves as the signal output terminal of the Schmitt trigger A1.

[0025] Compared with the traditional classic Schmitt trigger circuit, this circuit adds an NMOS transistor N4, and the operating current value of the main path of this Schmitt trigger can be adjusted by adjusting the W / L size of N4; the output feedback single PMOS transistor of the traditional classic Schmitt trigger is changed to a PMOS array transistor P<1>, P<2>, P<3>... P <n>, The NMOS in the output feedback form is changed to the NMOS array transistors N<1>, N<2>, N<3>... N <n>, after improvement, feedback adjustment and design flexibility are added, and the power-on reset time is adjusted.

[0026] The bandgap reference current source and power-on reset circuit work process: when powered on, the resistor R3 pulls down the level of node A to a low level. As the voltage increases, the Schmitt trigger A1 and the buffer A2 work normally, and the voltage of node B gradually increases. At this time, the NMOS tube N1 is turned on, and the level of node C is pulled down. The PMOS tubes P1 and P2 are turned on, and the current flowing through the PMOS tubes P1 and P2 gradually increases to the design value. The current flowing through the transistors BP1 and BP2 also gradually increases. In this process, the voltage of the G node continues to increase, and the voltages of the nodes E and F also continue to increase. When the voltages at the E point and the F point reach the normal working range of the low-noise operational amplifier A3, the error voltage is fed back to the PMOS tubes P1 and P2. At this point, the low-noise bandgap current reference circuit works normally, and the capacitor C1 on the C node is used to stabilize the operational amplifier.

[0027] The PMOS tube P4 proportionally replicates the current of the PMOS tube P1 to provide a bandgap reference current source that hardly changes with temperature for the external circuit of the chip and is output through the port IREF.

[0028] The PMOS tube P3 proportionally copies the current of the PMOS tube P1, and continuously charges the resistor R3 and the capacitor C2, so that the voltage of the node A continues to increase. When the voltage of the node A reaches the logic flip level designed by the Schmitt trigger A1, the voltage of the node B begins to decrease, and the NMOS tube N1 is turned off, thus completing the self-starting.

[0029] During the power-on process of the circuit, the voltage at point B starts from a low level and gradually rises to a high level. After that, the voltage changes to a low level after the PMOS tube P3 completes charging the resistor R3 and the capacitor C2, realizing the standard power-on reset function through the port POR output.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A bandgap reference current source and a power-on reset circuit, characterized in that: It comprises a low-noise current reference circuit and a reference current and power-on reset signal output circuit, wherein the signal output end of the low-noise current reference circuit is connected to the signal input end of the reference current and power-on reset signal output circuit, the low-noise current reference circuit is used to generate the current signal required by the reference current and power-on reset signal output circuit, and the reference current and power-on reset signal output circuit is used to process the input current signal and output a bandgap reference current signal and a power-on reset signal respectively.

2. The bandgap reference current source and power-on reset circuit according to claim 1, wherein: The low-noise current reference circuit includes a PMOS tube P1 and a PMOS tube P2, the drain of the P1 and the drain of the P2 are connected to a power supply, the gate of the P1 is connected to the gate of the P2 and then connected to the signal output end of the low-noise operational amplifier A3, the source of the P1 is divided into two paths, the first path is connected to the collector of the transistor BP1, and the second path is connected to the inverting input end of the A3; the source of the P2 is divided into two paths, the first path is connected to the collector of the transistor BP2 via a resistor R2, and the second path is connected to the non-inverting input end of the A3; the emitter of the transistor BP1 is connected to the emitter of the transistor BP2 and then connected to the ground via a resistor R1; the output end of the low-noise operational amplifier A3 is divided into two paths, the first path is connected to the ground via a capacitor C1, and the second path is the signal output end of the low-noise current reference circuit.

3. The bandgap reference current source and power-on reset circuit as claimed in claim 2, characterized in that: The node between the inverting input terminal of the low noise operational amplifier A3 and the PMOS transistor P1 is a node E, and the node between the non-inverting input terminal of the low noise operational amplifier A3 and the PMOS transistor P2 is a node F.

4. The bandgap reference current source and power-on reset circuit as claimed in claim 2, characterized in that: The transistor BP1 and the transistor BP2 use NPN transistors.

5. The bandgap reference current source and power-on reset circuit as claimed in claim 2, characterized in that: The low noise operational amplifier A3 includes a PMOS tube P7, the drain of the PMOS tube P7 is connected to the power supply, the gate of the PMOS tube P7 is connected to the source and then connected to the collector of the NPN tube N2 via the resistor R4, the collector of the NPN tube N2 is connected to the base of the NPN tube N2, and the emitter of the NPN tube N2 is grounded via the resistor R5; the drain of the PMOS tube P5 and the drain of the PMOS tube P6 are connected to the power supply, the gate of the PMOS tube P5 is connected to the gate of the PMOS tube P5 and then connected to the source of the PMOS tube P5, the source of the PMOS tube P5 is connected to the NPN transistor B1 The collector of the NPN transistor B1 is connected, the source of the PMOS transistor P6 is connected to the collector of the NPN transistor B2, the emitter of the NPN transistor B1 is connected to the emitter of the NPN transistor B2 and then connected to the collector of the NPN transistor N3, the emitter of the NPN transistor N3 is grounded via a resistor R6, the base of the NPN transistor B1 is the non-inverting input terminal of the low-noise operational amplifier A3, the base of the NPN transistor B2 is the inverting input terminal of the low-noise operational amplifier A3, and the node between the NPN transistor B2 and the PMOS transistor P6 is the signal output terminal of the low-noise operational amplifier A3.

6. The bandgap reference current source and power-on reset circuit as claimed in claim 1, characterized in that: The reference current and power-on reset signal output circuit comprises a PMOS tube P3 and a PMOS tube P4, the drain of the PMOS tube P3 and the drain of the PMOS tube P4 are connected to a power supply, the gate of the PMOS tube P3 is connected to the drain of the NMOS tube N1 and the gate of the NMOS tube N2 and serves as the signal input end of the reference current and power-on reset signal output circuit, and the source of the NMOS tube N2 is the reference current signal output end; the source of the NMOS tube N1 is grounded, the gate of the NMOS tube N1 is connected to the output end of the buffer A2, the source of the PMOS tube P3 is divided into three paths, the first path is grounded via a resistor R3, the second path is grounded via a capacitor C2, and the third path is connected to the input end of a Schmitt trigger A1, the output end of the Schmitt trigger A1 is connected to the input end of the buffer A2, the output end of the buffer A2 is connected to the input end of the buffer A4, and the output end of the buffer A4 is the power-on reset signal output end.

7. The bandgap reference current source and power-on reset circuit as claimed in claim 6, characterized in that: The node between the PMOS transistor P3 and the PMOS transistor P4 is a node C, the node between the PMOS transistor P3 and the Schmitt trigger A1 is a node A, and the node between the buffer A2 and the buffer A4 is a node B.

8. The bandgap reference current source and power-on reset circuit as claimed in claim 6, characterized in that: The Schmitt trigger A1 includes PMOS tubes P8-P 10 The gates of the PMOS tube P8, PMOS tube P9, NMOS tube N4 and NMOS tube N5 are connected as the signal input end of the Schmitt trigger A1, and the source of the PMOS tube P8 is divided into two paths, the first path is connected to the drain of the PMOS tube P9, and the second path is connected to the drain of the PMOS tube P <1> The drain connection of the PMOS tube P <1> The source of the PMOS tube P <2> The drain connection of the PMOS tube P <n-1>The source of the PMOS tube P <n>The drain connection of the PMOS tube P <n> The source of is connected to the drain of NMOS tube N5, the gate of NMOS tube N7 is connected to the power supply, and the source of NMOS tube N7 is grounded;< / n> < / n> The source of the PMOS tube P9 is divided into two paths, the first path is connected to the output end of the Schmitt trigger A1, and the second path is connected to the drain of the NMOS tube N6. The source of the NMOS tube N6 is connected to the drain of the NMOS tube N5. The source of the NMOS tube N5 is divided into two paths, the first path is connected to the drain of the NMOS tube N4, and the second path is connected to the drain of the NMOS tube N <1> The drain connection of NMOS tube N <1> The source of NMOS tube N <2> The drain connection of NMOS tube N <n-1>The source of the PMOS tube N <n>The drain connection of PMOS tube N <n>The source of the PMOS tube P 10 The drain connection of the PMOS tube P 10 The gate of the PMOS tube P <1> -PMOS tube P <n>The gate of the NMOS tube N <1> - NMOS tube N <n> The gate of is connected as the signal output end of the Schmitt trigger A1.< / n> < / n> < / n> < / n>

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