A power-on reset circuit of a multi-power supply chip, a chip and an electronic device

Abstract

The application discloses a power-on reset circuit of a multi-power supply chip, a chip and electronic equipment, and relates to the technical field of chips. The power-on reset circuit comprises a plurality of power supply detection circuits, the input ends of each power supply detection circuit are respectively connected to a corresponding power supply, and each power supply detection circuit is configured to output a detection completion signal when detecting that the corresponding power supply voltage reaches a preset detection threshold; and a logic processing circuit, the input end of the logic processing circuit is electrically connected to the output ends of the plurality of power supply detection circuits, and the logic processing circuit is configured to output a power-on reset signal when simultaneously receiving all detection completion signals. The application is configured with independent voltage detection modules for each power supply of the multi-power supply chip, and cooperates with logic centralized processing of detection signals, can adapt to any power supply power-on sequence, realizes independent voltage detection of each power supply, ensures that a reset signal is released only when all power supplies reach a preset detection threshold, fundamentally avoids abnormal work of the chip at a low voltage, and can greatly reduce the design complexity of a multi-power supply POR circuit.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit design, and in particular relates to a power-on reset circuit, chip, and electronic device for a multi-power supply chip. Background Technology

[0002] With the increasing integration of chip functions, multiple power inputs have become the mainstream architecture in chip design, requiring independent power supplies for different functional modules such as digital logic, analog circuits, and I / O ports within the chip. To ensure stable and reliable startup of the chip after power-on and to avoid logic anomalies, data errors, or even device damage under undervoltage conditions, the chip system must be equipped with a power-on reset (POR) circuit. This circuit performs voltage threshold detection on each power supply and only releases the reset signal, allowing the chip to enter normal operating mode, when all power supply voltages have reached the preset requirements for normal chip operation.

[0003] Existing multi-power supply POR circuits still suffer from the core pain point of difficulty in balancing adaptability, reliability, and cost control: On the one hand, the circuit lacks compatibility with the power-on sequence, making it unsuitable for any power-on application scenario, and prone to false triggering or missed triggering of reset signals, resulting in insufficient chip startup reliability; on the other hand, the design complexity of the multi-power supply differentiated detection threshold is high, and the threshold stability is easily affected by external factors such as process and temperature. At the same time, the circuit structure is redundant, increasing the design and manufacturing cost of the chip. Summary of the Invention

[0004] The purpose of this application is to provide a power-on reset circuit for multi-power supply chips, which aims to solve the problems of related power-on reset circuits being unable to adapt to arbitrary power-on sequences of chips, having poor flexibility and stability, and high design costs.

[0005] The first aspect of this application provides a power-on reset circuit for a multi-power supply chip, comprising: Multiple power supply detection circuits, each of which has its input terminal connected to a corresponding power supply and is configured to output a detection completion signal when the voltage of the corresponding power supply reaches a preset detection threshold. A logic processing circuit, the input of which is electrically connected to the output of a plurality of power detection circuits, is configured to output a power-on reset signal when all detection completion signals are received simultaneously.

[0006] In one embodiment, the plurality of power detection circuits include: a first power detection circuit, a second power detection circuit, and a third power detection circuit; The input terminal of the first power supply detection circuit is connected to the first power supply and is configured to output a first detection completion signal when the first power supply voltage is detected to reach a first preset detection threshold. The input terminal of the second power supply detection circuit is connected to the second power supply and is configured to output a second detection completion signal when the first power supply detection circuit outputs a first detection completion signal and the second power supply voltage is detected to reach a second preset detection threshold. The input terminal of the third power supply detection circuit is connected to the third power supply and is configured to output the third detection completion signal when the first power supply detection circuit outputs the first detection completion signal and the third power supply voltage is detected to reach the third preset detection threshold.

[0007] In one embodiment, it further includes: An enabling unit is electrically connected to the first power detection circuit, the second power detection circuit, and the third power detection circuit, respectively, and is configured to enable the second power detection circuit and the third power detection circuit when the first power detection circuit outputs a first detection completion signal.

[0008] In one embodiment, the first power supply detection circuit includes: a first resistor, a first NMOS transistor, a hysteresis inverter, and a first two-stage inverter; The first end of the first resistor is electrically connected to the first power supply and the gate of the first NMOS transistor, respectively. The second end of the first resistor is electrically connected to the drain of the first NMOS transistor and the input of the hysteresis inverter, respectively. The source of the first NMOS transistor is grounded. The power supply terminal of the hysteresis inverter is electrically connected to the first power supply, and the output terminal of the hysteresis inverter is electrically connected to the first two-stage inverter.

[0009] In one embodiment, the hysteresis inverter includes: a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor; The gates of the first PMOS transistor, the second PMOS transistor, the second NMOS transistor, and the third NMOS transistor are all electrically connected to the source of the first NMOS transistor. The source of the first PMOS transistor is electrically connected to the drain of the second PMOS transistor and the source of the third PMOS transistor, respectively. The drain of the first PMOS transistor is electrically connected to the drain of the third NMOS transistor, the gate of the third PMOS transistor, and the gate of the fourth NMOS transistor, respectively. The source of the second PMOS transistor is electrically connected to the first power supply. The gate of the third PMOS transistor is electrically connected to the gate of the fourth NMOS transistor, and the drain of the third PMOS transistor is grounded. The source of the second NMOS transistor is grounded, and the drain of the second NMOS transistor is electrically connected to the source of the third NMOS transistor. The source of the fourth NMOS transistor is electrically connected to the first power supply, and the drain of the fourth NMOS transistor is electrically connected to the source of the third NMOS transistor and the drain of the second NMOS transistor.

[0010] In one embodiment, the second power supply detection circuit includes: a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a first current mirror, and a second two-stage inverter. The first current mirror includes a fourth PMOS transistor and a fifth PMOS transistor. The source of the fifth NMOS transistor is grounded, the drain of the fifth NMOS transistor is electrically connected to the source of the sixth NMOS transistor, the gates of the fifth NMOS transistor and the sixth NMOS transistor are both electrically connected to the second power supply, and the drain of the sixth NMOS transistor is electrically connected to the gate of the fourth PMOS transistor, the drain of the fourth PMOS transistor, and the gate of the fifth PMOS transistor, respectively. The source of the seventh NMOS transistor is grounded, the drain of the seventh NMOS transistor is electrically connected to the source of the eighth NMOS transistor, the gates of the seventh NMOS transistor and the eighth NMOS transistor are both electrically connected to the first power supply, and the drain of the eighth NMOS transistor is electrically connected to the drain of the fifth PMOS transistor, the gate of the ninth NMOS transistor, and the input terminal of the second two-stage inverter, respectively. The source of the ninth NMOS transistor is electrically connected to the drain of the seventh NMOS transistor and the source of the eighth NMOS transistor, respectively, and the drain of the ninth NMOS transistor is electrically connected to the second power supply. The source of the fourth PMOS transistor and the source of the fifth PMOS transistor are both electrically connected to the second power supply. The power supply terminals of the second two-stage inverter are electrically connected to the first power supply.

[0011] In one embodiment, the third power supply detection circuit includes: a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a second current mirror, and a third two-stage inverter, wherein the second current mirror includes a sixth PMOS transistor and a seventh PMOS transistor; The source of the tenth NMOS transistor is grounded, the drain of the tenth NMOS transistor is electrically connected to the source of the eleventh NMOS transistor, the gates of the tenth NMOS transistor and the eleventh NMOS transistor are both electrically connected to the third power supply, and the drain of the eleventh NMOS transistor is electrically connected to the gate of the sixth PMOS transistor, the drain of the sixth PMOS transistor, and the gate of the seventh PMOS transistor, respectively. The source of the twelfth NMOS transistor is grounded, the drain of the twelfth NMOS transistor is electrically connected to the source of the thirteenth NMOS transistor, the gates of the twelfth NMOS transistor and the thirteenth NMOS transistor are both electrically connected to the first power supply, and the drain of the thirteenth NMOS transistor is electrically connected to the drain of the seventh PMOS transistor, the gate of the fourteenth NMOS transistor, and the input terminal of the third two-stage inverter, respectively. The source of the fourteenth NMOS transistor is electrically connected to the drain of the twelfth NMOS transistor and the source of the thirteenth NMOS transistor, respectively, and the drain of the fourteenth NMOS transistor is electrically connected to the third power supply. The source of the sixth PMOS transistor and the source of the seventh PMOS transistor are both electrically connected to the third power supply. The power supply terminal of the third two-stage inverter is electrically connected to the first power supply.

[0012] In one embodiment, the mirror ratios of the first current mirror and the second current mirror are different, the second preset detection threshold is determined based on the first preset detection threshold and the mirror ratio of the first current mirror, and the third preset detection threshold is determined based on the first preset detection threshold and the mirror ratio of the second current mirror.

[0013] A second aspect of this application provides a chip, the chip including the power-on reset circuit described above.

[0014] A third aspect of this application provides an electronic device, which includes the power-on reset circuit described above.

[0015] The power-on reset circuit of the multi-power supply chip described in this embodiment includes multiple power supply detection circuits. The input terminal of each power supply detection circuit is connected to a corresponding power supply. When the voltage of the corresponding power supply reaches a preset detection threshold, a detection completion signal is output. A logic processing circuit is also included, with its input terminal electrically connected to the output terminals of the multiple power supply detection circuits. When all detection completion signals are received simultaneously, a power-on reset signal is output. This embodiment, by configuring independent voltage detection modules for each power supply of the multi-power supply chip and coordinating with centralized logic processing of the detection signals, can perfectly adapt to any power supply power-on sequence, accurately realize independent voltage detection for each power supply, and ensure that the reset signal is released only when all power supplies reach the preset detection threshold, fundamentally avoiding abnormal low-voltage operation of the chip. Simultaneously, the circuit adopts a modular architecture, making it easy to integrate and reuse, significantly reducing the design complexity of the multi-power supply POR circuit. Attached Figure Description

[0016] To more clearly illustrate the related technologies or the technical solutions in the embodiments of this application, the drawings used in the description of the related technologies or the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application, and not all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of a power-on reset circuit provided in the first aspect of the embodiments of this application; Figure 2 A detailed structural schematic diagram of the power-on reset circuit provided in the first aspect of the embodiments of this application; Figure 3 A schematic diagram of the reset signal in the power-on reset circuit provided in the first aspect of the embodiments of this application; Figure 4 This is a schematic diagram of the structure of the first power supply detection circuit in the power-on reset circuit provided in the first aspect of the embodiments of this application; Figure 5 A detailed circuit structure diagram of the first power supply detection circuit in the power-on reset circuit provided in the first aspect of the embodiments of this application; Figure 6 A detailed circuit structure diagram of the second power supply detection circuit in the power-on reset circuit provided in the first aspect of the embodiments of this application; Figure 7 A detailed circuit structure diagram of the third power supply detection circuit in the power-on reset circuit provided in the first aspect of the embodiments of this application; Figure 8 This is a schematic diagram of a chip provided for a second aspect of an embodiment of this application; Figure 9 This is a schematic diagram of an electronic device provided for a third aspect of the embodiments of this application. Detailed Implementation

[0018] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0019] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0020] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means one or more, unless otherwise explicitly specified.

[0022] In the field of integrated circuit technology, as chip functions become increasingly complex, a single power supply can no longer meet the operational needs of different modules within the chip. Multiple power inputs have become the mainstream architecture in chip design. For example, digital logic modules within a chip require a core power supply, analog circuit modules require an analog power supply, and I / O ports require a dedicated I / O power supply. To ensure that the chip can start up and operate stably and correctly after power-on, and to avoid problems such as logic confusion, data errors, or even device damage caused by the chip operating under low or undervoltage conditions, a power-on reset circuit must be configured in the chip system. This circuit performs threshold detection on the voltage of each power supply. Only when the voltage of all power supplies reaches the preset threshold for normal chip operation is the reset signal released, allowing the chip to enter normal operating mode.

[0023] However, current power-on reset circuits for multi-power supply chips use a shared detection link to detect the voltage of multiple power supplies. This is prone to interference between power supply detection signals and cannot adapt to the different voltage detection threshold requirements of each power supply, resulting in low detection accuracy. Furthermore, they lack adaptability to the power-on sequence. Some existing circuits rely on a fixed power-on sequence for their power detection logic. When the power-on sequence changes arbitrarily in practical applications, false positives or false negatives may occur, leading to premature or delayed release of the reset signal, preventing the chip from starting normally. Finally, the stability of the detection threshold is poor; the power supply voltage detection threshold of existing circuits is easily affected by chip manufacturing processes. External factors such as process technology and operating environment temperature can cause significant fluctuations. When the detection threshold deviates, it may lead to premature release of the reset signal when the power supply voltage does not meet the chip's operating requirements, or the chip may remain in the reset state even after the power supply voltage meets the requirements, affecting the chip's operational stability. The circuit design is also highly complex. To achieve differentiated detection thresholds for different power supplies, some existing circuits require a separate complete threshold detection and signal processing link for each power supply. The links cannot reuse their structures, resulting in a large number of components and a large layout area in the entire power-on reset circuit. This increases the chip's design and manufacturing costs and reduces the circuit's integration.

[0024] Therefore, a multi-power-source chip power-on reset circuit that can adapt to any power-on sequence, achieve independent and accurate voltage threshold detection for each power source, and has strong threshold stability, simple circuit structure, and reusability has become the key to solving the existing technical problems and is also a technical goal that those skilled in the art urgently need to achieve.

[0025] Figure 1 A schematic diagram of a power-on reset circuit provided in the first aspect of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below: The power-on reset circuit of the multi-power supply chip in this embodiment includes multiple power supply detection circuits 101~10n, the input of each power supply detection circuit is connected to a corresponding power supply 201~20n, and is configured to output a detection completion signal when the voltage of the corresponding power supply reaches a preset detection threshold; and a logic processing circuit 301, the input of which is electrically connected to the output of the multiple power supply detection circuits, and is configured to output a power-on reset signal when all detection completion signals are received simultaneously.

[0026] Specifically, the power-on reset circuit includes multiple power detection circuits and logic processing circuits. Each power detection circuit is an independent detection module, and its input is connected one-to-one to a corresponding power supply of the multi-power chip. Each power detection circuit is configured to independently detect the voltage of the connected power supply and monitor in real time whether the voltage value of the corresponding power supply reaches the preset detection threshold for that power supply. When the voltage of the corresponding power supply reaches the preset detection threshold, a detection completion signal indicating that the power supply detection is complete is output.

[0027] The logic processing circuit is the core of the signal processing for the entire power-on reset circuit. Its input is electrically connected to the output of all power detection circuits to receive the detection completion signals output by each power detection circuit. The logic processing circuit is configured to perform logical judgment on all received detection completion signals. Only when all power detection circuit output detection completion signals are received simultaneously, that is, when it is determined that all power supply voltages of the multi-power chip have reached their respective preset detection thresholds, will a power-on reset signal be output. This power-on reset signal is used to release the reset state of the multi-power chip and allow the chip to enter the normal working mode.

[0028] This circuit uses independent power detection circuits to detect each power source separately. Combined with the centralized signal judgment of the logic processing circuit, it can adapt to any power-on sequence of multi-power source chips. Moreover, each power detection circuit works independently without interfering with each other. It can accurately identify the voltage compliance status of each power source and ensure that the reset signal is released only when all power sources meet the operating voltage requirements, effectively improving the stability and reliability of multi-power source chips during power-on.

[0029] exist Figure 1 Based on the provided structural schematic diagram of the power-on reset circuit, this application also provides a detailed structural schematic diagram of the power-on reset circuit, please refer to the following for details. Figure 2 .

[0030] In one embodiment, the plurality of power supply detection circuits include: a first power supply detection circuit 101, a second power supply detection circuit 102, and a third power supply detection circuit 103; the input terminal of the first power supply detection circuit 101 is connected to a first power supply 201 and is configured to output a first detection completion signal when the voltage of the first power supply 201 is detected to reach a first preset detection threshold; the input terminal of the second power supply detection circuit 102 is connected to the second power supply 202 and is configured to output a second detection completion signal when the first power supply 201 detection circuit outputs the first detection completion signal and the voltage of the second power supply 202 is detected to reach a second preset detection threshold; the input terminal of the third power supply detection circuit 103 is connected to the third power supply 203 and is configured to output a third detection completion signal when the first power supply 201 detection circuit outputs the first detection completion signal and the voltage of the third power supply 203 is detected to reach a third preset detection threshold.

[0031] Specifically, the first power supply detection circuit 101 is the basic detection module of the entire POR circuit. Its input terminal is connected to the first power supply 201, which is used to perform voltage threshold detection on the first power supply 201 that supplies power to the core functional module of the chip. The first power supply detection circuit 101 is configured to monitor the voltage value of the first power supply 201 in real time. When the voltage of the first power supply 201 reaches a preset first detection threshold, it outputs a first detection completion signal. The first detection completion signal is used to characterize the voltage compliance status of the first power supply 201, and also serves as the enable control signal for the second power supply detection circuit 102 and the third power supply detection circuit 103, realizing hierarchical linkage control of multiple power supply detection.

[0032] The input terminal of the second power supply detection circuit 102 is connected to the second power supply 202 and is used to perform voltage threshold detection on the second power supply 202 corresponding to the second functional module of the chip. The second power supply detection circuit 102 is configured to start voltage detection on the second power supply 202 only when it receives the first detection completion signal output by the first power supply detection circuit 101, and output the second detection completion signal when the voltage of the second power supply 202 reaches the second preset detection threshold.

[0033] The input terminal of the third power supply detection circuit 103 is connected to the third power supply 203 and is used to perform voltage threshold detection on the third power supply 203 corresponding to the third functional module of the chip. The third power supply detection circuit 103 is configured to start voltage detection on the third power supply 203 only when it receives the first detection completion signal output by the first power supply detection circuit 101, and output the third detection completion signal when the voltage of the third power supply 203 reaches the third preset detection threshold.

[0034] Understandably, the first, second, and third preset detection thresholds can be set independently according to the power supply requirements of different functional modules of the chip. The three can be the same or different to adapt to the differentiated power supply requirements of multi-power chips. The first, second, and third detection completion signals are all output to the logic processing circuit, which performs synchronous logic judgment of multiple signals. Only when all three detection completion signals are valid will the final power-on reset signal be output to release the chip from the reset state.

[0035] In one embodiment, the system further includes an enabling unit, which is electrically connected to the first power detection circuit, the second power detection circuit, and the third power detection circuit, and is configured to enable the second power detection circuit and the third power detection circuit when the first power detection circuit outputs a first detection completion signal.

[0036] Specifically, the enabling unit uses the first detection completion signal output by the first power supply detection circuit as the enabling trigger condition. When the first power supply detection circuit does not output the first detection completion signal, that is, when the first power supply voltage does not reach the first preset detection threshold, the enabling unit remains in the off state, and the second and third power supply detection circuits are always in a non-working shielded state and will not start the voltage detection operation of the second and third power supplies. Only when the first power supply voltage reaches the standard and the first power supply detection circuit outputs a valid first detection completion signal, the enabling unit responds to the signal and completes conduction, thereby providing the second and third power supply detection circuits with the control signal to start working, so that they can officially start the voltage threshold detection of the corresponding power supply.

[0037] In detail, the circuit operation in this embodiment can be divided into two stages: the VCCINT power detection stage and the other power detection stage. During the VCCINT power detection stage, the power supply VCCINT is not powered on and the detection threshold is reached. While POR_VCCINT remains low, other power detection circuit output signals are disabled, and POR remains low. During other power detection phases, the power supply VCCINT reaches the detection threshold upon power-up. When POR_VCCINT goes high, the VCCAUX and VCCO power supply detection circuits are enabled. The circuits will continue to operate until both VCCAUX and VCCO reach their detection thresholds. and Then, POR_VCCAUX and POR_VCCO are pulled high, at which point POR is pulled high, and the POR circuit completes the power detection function.

[0038] Furthermore, in some embodiments, the first power source is the core power source (V). CCINT The second power supply is an analog power supply (V). CCAUX ) and the third power supply is the port power supply (V CCO The corresponding detection circuits are V CCINT Power detection circuit, V CCAUX Power detection circuit and V CCO The power supply detection circuit outputs its respective detection completion signals POR_VCCINT, POR_VCCAUX, and POR_VCCO when the detected power supplies reach their respective detection thresholds. The three detection completion signals are ANDed to ensure that all three signals are pulled high before the POR signal is output, indicating that all three power supplies have reached their design thresholds and can meet the requirements for normal chip operation. At this time, the chip reset signal POR is released.

[0039] Detailed, such as Figure 3As shown, when each power supply voltage rises to its respective design threshold voltage VTH, the detection completion signals POR_VCCINT, POR_VCCAUX, and POR_VCCO are pulled high respectively. Since the three detection completion signals are ANDed, POR is pulled high only after all three signals have been pulled high. It is understandable that the power-on sequence and slope of each power supply in the diagram are not fixed and can be arbitrarily set.

[0040] A schematic diagram of the structure of the first power supply detection circuit in the power-on reset circuit provided in the first aspect of this application is shown in the attached diagram. For details, please refer to [link to specific documentation]. Figure 4 .

[0041] In one embodiment, the first power supply detection circuit 101 includes: a first resistor R1, a first NMOS transistor N1, a hysteresis inverter 1011, and a first two-stage inverter 1012; the first terminal of the first resistor R1 is connected to the first power supply V. CCINT The gate of the first NMOS transistor N1 is electrically connected, and the second end of the first resistor R1 is electrically connected to the drain of the first NMOS transistor N1 and the input of the hysteresis inverter 1011, respectively; the source of the first NMOS transistor N1 is grounded; the power supply terminal of the hysteresis inverter 1011 is connected to the first power supply V. CCINT Electrically connected, the output of the hysteresis inverter 1011 is electrically connected to the first two-stage inverter 1012.

[0042] It is understandable that the first resistor R1 and the first NMOS transistor N1 together constitute a voltage-to-current conversion and potential sampling unit, which can convert the voltage change of the first power supply VCCINT into a potential change at the input of the hysteresis inverter 1011. The hysteresis inverter 1011, as the core threshold switching judgment unit, effectively avoids false switching of the detection signal caused by small fluctuations during the VCCINT voltage rise process through its own hysteresis characteristics, thus improving the anti-interference capability of voltage detection. The first two-stage inverter 1012 includes two inverters connected in series, receiving the output signal of the hysteresis inverter 1011 to complete subsequent signal processing and transmission. Simultaneously, all functional modules of the first power supply detection circuit 101 are powered by the first power supply VCCINT, achieving power supply synchronization between the detection circuit and the detected power supply. This ensures that during the VCCINT power-on process, the detection circuit can synchronously enter the working state as the power supply voltage rises, eliminating the need for an additional power supply, simplifying the overall circuit architecture, and meeting the design requirements of simplified POR circuits for multi-power supply chips.

[0043] This application also provides a detailed circuit structure diagram of the first power supply detection circuit in the power-on reset circuit. Please refer to the following for details. Figure 5 .

[0044] In one embodiment, the hysteresis inverter 1011 includes: a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a first PMOS transistor P1, a second PMOS transistor P2, and a third PMOS transistor P3; the gates of the first PMOS transistor P1, the second PMOS transistor P2, the second NMOS transistor N2, and the third NMOS transistor N3 are all electrically connected to the source of the first NMOS transistor N1; the source of the first PMOS transistor P1 is electrically connected to the drain of the second PMOS transistor P2 and the source of the third PMOS transistor P3, respectively; the drain of the first PMOS transistor P1 is electrically connected to the drain of the third NMOS transistor N3, the gate of the third PMOS transistor P3, and the gate of the fourth NMOS transistor N4, respectively; the source of the second PMOS transistor P2 is connected to a first power supply V. CCINT Electrical connections: The gate of the third PMOS transistor P3 is electrically connected to the gate of the fourth NMOS transistor N4, and the drain of the third PMOS transistor P3 is grounded; the source of the second NMOS transistor N2 is grounded, and the drain of the second NMOS transistor N2 is electrically connected to the source of the third NMOS transistor N3; the source of the fourth NMOS transistor N4 is connected to the first power supply V. CCINT Electrically connected, the drain of the fourth NMOS transistor N4 is electrically connected to the source of the third NMOS transistor N3 and the drain of the second NMOS transistor N2.

[0045] Specifically, the gates of the first PMOS transistor P1, the second PMOS transistor P2, the second NMOS transistor N2, and the third NMOS transistor N3 are all electrically connected to the source of the first NMOS transistor N1; the source of the first PMOS transistor P1 is electrically connected to the drain of the second PMOS transistor P2 and the source of the third PMOS transistor P3, respectively; the drain of the first PMOS transistor P1 is electrically connected to the drain of the third NMOS transistor N3, the gate of the third PMOS transistor P3, and the gate of the fourth NMOS transistor N4, respectively; the source of the second PMOS transistor P2 is connected to the first power supply VCCI. The NT transistor is electrically connected and powered by the first power supply VCCINT. The gate of the third PMOS transistor P3 is electrically connected to the gate of the fourth NMOS transistor N4, and the drain of the third PMOS transistor P3 is grounded. The source of the second NMOS transistor N2 is grounded, and the drain of the second NMOS transistor N2 is electrically connected to the source of the third NMOS transistor N3. The source of the fourth NMOS transistor N4 is electrically connected to the first power supply VCCINT, and the drain of the fourth NMOS transistor N4 is electrically connected to the source of the third NMOS transistor N3 and the drain of the second NMOS transistor N2.

[0046] In detail, in this embodiment, the hysteresis inverter 1011 is used for threshold judgment in the first power supply detection circuit. Through a multi-transistor topology, it forms a hysteresis switching characteristic, providing a stable hysteresis window for the switching of the detection signal during the rise of the first power supply VCCINT voltage. This effectively avoids false switching of the detection signal when VCCINT voltage ripples or small fluctuations occur, significantly improving the anti-interference capability and threshold judgment accuracy of the first power supply voltage detection. Simultaneously, the hysteresis inverter 1011 is powered by the first power supply VCCINT and can enter the working state synchronously with the power-on process of the first power supply VCCINT, achieving synchronous detection with the first power supply voltage change. No additional auxiliary power supply circuit is required, meeting the design requirements of circuit simplification. Its output is directly connected to the first two-stage inverter, stably outputting the threshold-flipped electrical signal to the subsequent circuit for determining whether the first detection completion signal has been generated.

[0047] It is understandable that the current flowing through resistor R1 This is the drain current of N1: , , = - *R1 , in, The process parameter coefficients for the first NMOS transistor N1 are determined by the device's structure and manufacturing process. This refers to the real-time voltage of the first power supply core. The threshold voltage of the first NMOS transistor N1 For electron mobility, W is the capacitance per unit area of ​​the oxide layer of the MOSFET. N1 and L N1 These represent the channel width and length of the first NMOS transistor N1, respectively. This represents the potential at node C, where the drain of the first NMOS transistor N1 is connected to the first resistor R1. When the power supply VCCINT does not reach the high threshold, this represents the threshold voltage of MOS transistor N1. When the current flows through R1 and is close to 0, the C potential follows the power supply VCCINT. After passing through the hysteresis inverter and two stages of inversion, POR_VCCINT is low. When VCCINT rises to the N1 threshold, As the voltage increases rapidly, the voltage drop across R1 increases rapidly, and point C decreases. When the potential at C drops to the toggling threshold of the hysteresis inverter, POR_VCCINT is toggled high.

[0048] This application also provides a detailed circuit diagram of the second power supply detection circuit in the power-on reset circuit. Please refer to the following for details. Figure 6 .

[0049] like Figure 6 As shown, in one embodiment, the second power supply detection circuit 102 includes: a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a first current mirror 1021, and a second two-stage inverter 1022. The first current mirror 1021 includes a fourth PMOS transistor P4 and a fifth PMOS transistor P5. The source of the fifth NMOS transistor N5 is grounded, and the drain of the fifth NMOS transistor N5 is electrically connected to the source of the sixth NMOS transistor N6. The gates of both the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are connected to the second power supply V. CCAUX Electrically connected, the drain of the sixth NMOS transistor N6 is electrically connected to the gate of the fourth PMOS transistor P4, the drain of the fourth PMOS transistor P4, and the gate of the fifth PMOS transistor P5, respectively; the source of the seventh NMOS transistor N7 is grounded, and the drain of the seventh NMOS transistor N7 is electrically connected to the source of the eighth NMOS transistor N8; the gates of both the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are connected to the first power supply V. CCINT Electrically connected, the drain of the eighth NMOS transistor N8 is electrically connected to the drain of the fifth PMOS transistor P5, the gate of the ninth NMOS transistor N9, and the input of the second two-stage inverter 1022; the source of the ninth NMOS transistor N9 is electrically connected to the drain of the seventh NMOS transistor N7 and the source of the eighth NMOS transistor N8; the drain of the ninth NMOS transistor N9 is connected to the second power supply V. CCAUX Electrical connection; the source of the fourth PMOS transistor P4 and the source of the fifth PMOS transistor P5 are both connected to the second power supply V. CCAUX Electrical connection; the power supply terminal of the second two-stage inverter 1022 is connected to the first power supply V. CCINT Electrical connection.

[0050] Specifically, the source of the fifth NMOS transistor N5 is grounded, the drain of the fifth NMOS transistor N5 is electrically connected to the source of the sixth NMOS transistor N6, and the gates of both the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are electrically connected to the second power supply VCCAUX, forming a current sampling loop for the VCCAUX voltage; the drain of the sixth NMOS transistor N6 is electrically connected to the gate of the fourth PMOS transistor P4, the drain of the fourth PMOS transistor P4, and the gate of the fifth PMOS transistor P5, respectively, providing a working trigger signal for the first current mirror 1021. The source of the seventh NMOS transistor N7 is grounded, and the drain of the seventh NMOS transistor N7 is electrically connected to the source of the eighth NMOS transistor N8. The gates of both the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are electrically connected to the first power supply VCCINT, serving as the enable trigger branch of the second power supply detection circuit 102. The drain of the eighth NMOS transistor N8 is electrically connected to the drain of the fifth PMOS transistor P5, the gate of the ninth NMOS transistor N9, and the input of the second two-stage inverter 1022, respectively, to realize the comparison of the detection current and the transmission of the detection signal.

[0051] The source of the ninth NMOS transistor N9 is electrically connected to the drain of the seventh NMOS transistor N7 and the source of the eighth NMOS transistor N8, respectively. The drain of the ninth NMOS transistor N9 is electrically connected to the second power supply VCCAUX, providing hysteresis regulation support for the second power supply detection circuit 102. The sources of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are both electrically connected to the second power supply VCCAUX, which provides power to the first current mirror 1021. The power supply terminal of the second two-stage inverter 1022 is electrically connected to the first power supply VCCINT, completing the subsequent shaping and amplification of the detection signal, which is used to output the second detection completion signal POR_VCCAUX.

[0052] In this embodiment, the fifth NMOS transistor N5 and the sixth NMOS transistor N6 work together to form a current sampling unit for the VCCAUX voltage, which can convert the voltage change of VCCAUX into a corresponding current signal, providing a basis for the operation of the first current mirror 1021; the branch composed of the seventh NMOS transistor N7 and the eighth NMOS transistor N8 is controlled by the first power supply VCCINT, enabling the second power supply detection circuit 102 and the first power supply detection circuit 101. Only when the VCCINT voltage reaches the target can this branch trigger the second power supply detection circuit 102 to enter the working state, which is in line with the design logic of multi-power supply hierarchical detection. The first current mirror 1021 serves as the core current comparison and threshold adjustment unit of the second power supply detection circuit 102. Through the mirroring of the fourth PMOS transistor P4 and the fifth PMOS transistor P5, it can realize the proportional conversion of the detection current, providing a hardware foundation for the flexible adjustment of the VCCAUX detection threshold. The ninth NMOS transistor N9 provides hysteresis for the detection circuit, effectively avoiding false flipping of the detection signal due to small fluctuations during the VCCAUX voltage rise process, and improving the anti-interference capability of voltage detection. The second two-stage inverter 1022 completes the shaping of the detection signal and enhances the driving capability, ensuring that the second detection completion signal POR_VCCAUX can be stably transmitted to the subsequent logic processing circuit.

[0053] In detail, POR_VCCINT and POR_VCCAUX have a logical relationship; therefore, the VCCAUX detection circuit is not enabled when POR_VCCINT is not toggling. When the VCCINT power supply reaches the threshold, transistors N7 and N8 turn on, and the current flowing through N7 and N8... Satisfy the following formula:

[0054]

[0055] When VCCAUX reaches a high value, N5 and N6 conduct, and the current flowing through N6 and N8 at this time... for:

[0056]

[0057] P4 and P5 form a current mirror with a mirror ratio of M1:M2. Therefore, the current flowing through P5 is:

[0058] when When the A potential is pulled down to a low level, after two stages of inversion, the POR_VCCAUX output is low; when When the A potential is pulled up to a high level, after two stages of inversion, the POR_VCCAUX output is high; Therefore when The time is the reversal point, expressed as:

[0059] By designing N5, N6, N7, and N8 symmetrically, we can maximize the... , According to the above formula, the detection threshold voltage of VCCAUX can be expressed as being related to the detection threshold voltage of VCCINT:

[0060] Therefore, the detection threshold of the power supply can be adjusted by setting the size ratio of P4 and P4 transistor. N9 can provide a delay effect for detection.

[0061] This embodiment also provides a detailed circuit diagram of the third power supply detection circuit in the power-on reset circuit. Please refer to [link / reference needed] for details. Figure 7 .

[0062] like Figure 7 As shown, in one embodiment, the third power supply detection circuit 103 includes: a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a second current mirror 1031, and a third two-stage inverter 1032. The second current mirror 1031 includes a sixth PMOS transistor P6 and a seventh PMOS transistor P7. The source of the tenth NMOS transistor N10 is grounded, the drain of the tenth NMOS transistor N10 is electrically connected to the source of the eleventh NMOS transistor N11, and the gates of both the tenth NMOS transistor N10 and the eleventh NMOS transistor N11 are connected to the third power supply V. CCO Electrically connected, the drain of the eleventh NMOS transistor N11 is electrically connected to the gate of the sixth PMOS transistor P6, the drain of the sixth PMOS transistor P6, and the gate of the seventh PMOS transistor P7, respectively; the source of the twelfth NMOS transistor N12 is grounded, and the drain of the twelfth NMOS transistor N12 is electrically connected to the source of the thirteenth NMOS transistor N13; the gates of both the twelfth NMOS transistor N12 and the thirteenth NMOS transistor N13 are connected to the first power supply V. CCINT Electrically connected, the drain of the thirteenth NMOS transistor N13 is electrically connected to the drain of the seventh PMOS transistor P7, the gate of the fourteenth NMOS transistor N14, and the input of the third two-stage inverter 1032; the source of the fourteenth NMOS transistor N14 is electrically connected to the drain of the twelfth NMOS transistor N12 and the source of the thirteenth NMOS transistor N13; the drain of the fourteenth NMOS transistor N14 is connected to the third power supply V. CCOElectrical connection; the source of the sixth PMOS transistor P6 and the source of the seventh PMOS transistor P7 are both connected to the third power supply V. CCO Electrical connection; the power supply terminal of the third two-stage inverter 1032 is connected to the first power supply V. CCINT Electrical connection.

[0063] Specifically, the source of the tenth NMOS transistor N10 is grounded, the drain of the tenth NMOS transistor N10 is electrically connected to the source of the eleventh NMOS transistor N11, and the gates of both the tenth NMOS transistor N10 and the eleventh NMOS transistor N11 are electrically connected to the third power supply VCCO, forming a current sampling loop for the VCCO voltage; the drain of the eleventh NMOS transistor N11 is electrically connected to the gate of the sixth PMOS transistor P6, the drain of the sixth PMOS transistor P6, and the gate of the seventh PMOS transistor P7, respectively, providing a working trigger signal for the second current mirror 1031. The source of the twelfth NMOS transistor N12 is grounded, and the drain of the twelfth NMOS transistor N12 is electrically connected to the source of the thirteenth NMOS transistor N13. The gates of both the twelfth NMOS transistor N12 and the thirteenth NMOS transistor N13 are electrically connected to the first power supply VCCINT, serving as the enable trigger branch of the third power supply detection circuit 103. The drain of the thirteenth NMOS transistor N13 is electrically connected to the drain of the seventh PMOS transistor P7, the gate of the fourteenth NMOS transistor N14, and the input of the third two-stage inverter 1032, respectively, to realize the comparison of the detection current and the transmission of the detection signal.

[0064] The source of the fourteenth NMOS transistor N14 is electrically connected to the drain of the twelfth NMOS transistor N12 and the source of the thirteenth NMOS transistor N13, respectively. The drain of the fourteenth NMOS transistor N14 is electrically connected to the third power supply VCCO, providing hysteresis regulation support for the third power supply detection circuit 103. The sources of the sixth PMOS transistor P6 and the seventh PMOS transistor P7 are both electrically connected to the third power supply VCCO, which provides power to the second current mirror 1031. The power supply terminal of the third two-stage inverter 1032 is electrically connected to the first power supply VCCINT, completing the subsequent shaping and amplification of the detection signal, and providing support for outputting the third detection completion signal POR_VCCO.

[0065] In this embodiment, the tenth NMOS transistor N10 and the eleventh NMOS transistor N11 work together to form a current sampling unit for the VCCO voltage, which can convert the voltage change of VCCO into a corresponding current signal, providing a basis for the operation of the second current mirror 1031; the branch composed of the twelfth NMOS transistor N12 and the thirteenth NMOS transistor N13 is controlled by the first power supply VCCINT, realizing the linkage enable of the third power supply detection circuit 103 and the first power supply detection circuit 101. Only when the VCCINT voltage reaches the standard can this branch trigger the third power supply detection circuit 103 to enter the working state, which is consistent with the enable logic of the second power supply detection circuit, realizing hierarchical and orderly control of multiple power supply detection. The second current mirror 1031 serves as the core current comparison and threshold adjustment unit of the third power supply detection circuit 103. Through the mirroring of the sixth PMOS transistor P6 and the seventh PMOS transistor P7, it realizes the proportional conversion of the detection current, providing a hardware foundation for the flexible adjustment of the VCCO detection threshold. The fourteenth NMOS transistor N14 provides hysteresis for the detection circuit, effectively avoiding false flipping of the detection signal caused by small fluctuations during the VCCO voltage rise process, and improving the anti-interference capability and stability of the IO power supply voltage detection. The third two-stage inverter 1032 completes the shaping of the detection signal and enhances the driving capability, ensuring that the third detection completion signal POR_VCCO can be stably transmitted to the subsequent logic processing circuit and participate in the final power-on reset signal logic judgment.

[0066] It is understandable that the VCCO power detection circuit and the VCCAUX power detection circuit have the same structure, the difference being that the current mirror image ratio is different, and the VCCO can be set to have different switching thresholds.

[0067] In one embodiment, the mirror ratios of the first current mirror and the second current mirror are different, the second preset detection threshold is determined based on the first preset detection threshold and the mirror ratio of the first current mirror, and the third preset detection threshold is determined based on the first preset detection threshold and the mirror ratio of the second current mirror.

[0068] Specifically, the first current mirror 1021 is composed of the fourth PMOS transistor P4 and the fifth PMOS transistor P5, and its mirror ratio is the device size ratio of the fourth PMOS transistor P4 and the fifth PMOS transistor P5. The second current mirror 1031 is composed of the sixth PMOS transistor P6 and the seventh PMOS transistor P7, and its mirror ratio is the device size ratio of the sixth PMOS transistor P6 and the seventh PMOS transistor P7. By designing the size ratio of the two sets of PMOS transistors differently, the mirror ratio of the first and second current mirrors can be flexibly adjusted without changing the overall topology of the VCCAUX and VCCO power detection circuits. The detection threshold can be set differently only by adjusting the parameters of the core components.

[0069] Based on the aforementioned differentiated mirror ratio design, both the second and third preset detection thresholds are set proportionally to the first preset detection threshold, ensuring a precise proportional relationship between the voltage detection thresholds of VCCAUX and VCCO and the detection threshold of VCCINT. This design allows for precise simultaneous control of the detection thresholds of VCCAUX and VCCO while maintaining the stability of the first power supply's VCCINT detection threshold. Furthermore, the detection thresholds of all three power supplies, thanks to the symmetrical circuit design and the proportional characteristics of the current mirror, maintain resistance to interference from external factors such as process technology and temperature, ensuring the stability of the detection thresholds and meeting the differentiated and highly stable voltage detection requirements of multiple power supply chips for different power supply modules.

[0070] Understandably, this design allows the VCCAUX and VCCO power detection circuits to adopt the same topology as the core detection circuit. Threshold differentiation is achieved only by adjusting the current mirror ratio, eliminating the need to redesign a complete voltage detection link for different power supplies. This significantly simplifies the overall design process of multi-power supply POR circuits, reduces the types of components and the layout area, and meets the design requirements of simplified and integrated multi-power supply chip POR circuits. It also makes the later debugging and parameter optimization of the circuit more convenient.

[0071] In summary, the power-on reset circuit of the multi-power chip described in this application embodiment takes the three-power supply architecture of core power supply VCCINT, analog power supply VCCAUX, and IO power supply VCCO as the specific implementation scenario, and constructs an overall architecture of three independent power supply detection circuits + enable unit + logic processing circuit, forming a complete POR circuit solution that adapts to any power-on sequence of multiple power supplies and has a stable and adjustable detection threshold. The circuit first independently detects the voltage of VCCINT using a first power supply detection circuit. Relying on the voltage-to-current conversion of resistors and NMOS transistors, and the threshold flipping of a hysteresis inverter, it outputs a first detection completion signal POR_VCCINT. Then, the enable unit uses POR_VCCINT as a trigger signal to enable the second and third power supply detection circuits with identical structures, which respectively detect the voltage of VCCAUX and VCCO. Both VCCAUX and VCCO achieve current ratio conversion through NMOS transistor sampling and a current mirror composed of PMOS transistors, and are equipped with a hysteresis adjustment transistor to improve detection stability. The first and second current mirrors are designed with different mirror ratios, so that the second preset detection threshold of VCCAUX and the third preset detection threshold of VCCO are determined based on the first preset detection threshold of VCCINT, without the need to redesign the detection link. Finally, the logic processing circuit executes and processes the three detection completion signals POR_VCCINT, POR_VCCAUX, and POR_VCCO. Only when all three signals are valid, the final power-on reset signal is output to release the chip reset.

[0072] This invention, through its concise and modular circuit design, perfectly solves the technical pain points of existing multi-power supply POR circuits, such as poor adaptability, insufficient stability of detection thresholds, and complex design, achieving multiple technical benefits: First, by using an independent power supply detection module and logic signal processing, it ensures that the reset signal is only released after all power supply voltages have reached the preset detection threshold, fundamentally preventing abnormal operation of the chip under undervoltage conditions and ensuring the safety of chip power-on startup; Second, based on VCCINT detection, it achieves graded enabling of other power supply detection circuits, with no fixed requirements for the power-on sequence and voltage ramp-up rate of each power supply, adapting to any power-on scenario in the actual application of multi-power supply chips, improving the circuit's scenario compatibility and operational reliability; Third, relying on the differentiated design of the current mirror image ratio, it achieves flexible and differentiated settings for the detection thresholds of each power supply, and through the symmetrical design of MOS transistors, the detection thresholds are minimally affected by external factors such as process and temperature, ensuring the threshold... The circuit exhibits high stability; fourth, the VCCAUX and VCCO detection circuits use the same topology, achieving threshold differences only by adjusting the current mirror ratio, thus realizing high reuse of circuit modules, significantly simplifying the design process of multi-supply POR circuits, reducing layout area, and lowering chip design and manufacturing costs; fifth, hysteresis inverters or hysteresis regulators are set in each power supply detection circuit, effectively avoiding false switching of detection signals caused by small fluctuations during power supply voltage ramp-up, improving the anti-interference capability of voltage detection, and ensuring stable signal output after detection; sixth, the overall circuit is built using conventional MOSFETs, resistors, and inverters, without complex dedicated components, and each detection module is powered synchronously with the detected power supply, requiring no additional auxiliary power supply, further simplifying the circuit architecture, improving circuit integration and engineering practicality, and widely adaptable to various multi-supply input architecture chip systems, providing reliable circuit support for stable chip power-on and startup.

[0073] Figure 8 A schematic diagram of a chip provided in the second aspect of an embodiment of this application is shown. The chip A includes a power-on reset circuit 01 for a multi-power supply chip as described in any of the above claims.

[0074] Figure 9 A schematic diagram of an electronic device provided in the third aspect of the present application is shown. The electronic device B includes a power-on reset circuit 01 for a multi-power supply chip as described in any of the preceding claims.

[0075] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0076] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, phrases such as "in one embodiment," "in some embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0077] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A power-on reset circuit for a multi-power supply chip, characterized in that, include: Multiple power supply detection circuits, each of which has its input terminal connected to a corresponding power supply and is configured to output a detection completion signal when the voltage of the corresponding power supply reaches a preset detection threshold. A logic processing circuit, the input of which is electrically connected to the output of a plurality of power detection circuits, is configured to output a power-on reset signal when all detection completion signals are received simultaneously.

2. The power-on reset circuit according to claim 1, characterized in that, The plurality of power detection circuits include: a first power detection circuit, a second power detection circuit, and a third power detection circuit; The input terminal of the first power supply detection circuit is connected to the first power supply and is configured to output a first detection completion signal when the first power supply voltage is detected to reach a first preset detection threshold. The input terminal of the second power supply detection circuit is connected to the second power supply and is configured to output a second detection completion signal when the first power supply detection circuit outputs a first detection completion signal and the second power supply voltage is detected to reach a second preset detection threshold. The input terminal of the third power supply detection circuit is connected to the third power supply and is configured to output the third detection completion signal when the first power supply detection circuit outputs the first detection completion signal and the third power supply voltage is detected to reach the third preset detection threshold.

3. The power-on reset circuit according to claim 2, characterized in that, Also includes: An enabling unit is electrically connected to the first power detection circuit, the second power detection circuit, and the third power detection circuit, respectively, and is configured to enable the second power detection circuit and the third power detection circuit when the first power detection circuit outputs a first detection completion signal.

4. The power-on reset circuit according to claim 2, characterized in that, The first power supply detection circuit includes: a first resistor, a first NMOS transistor, a hysteresis inverter, and a first two-stage inverter; The first end of the first resistor is electrically connected to the first power supply and the gate of the first NMOS transistor, respectively. The second end of the first resistor is electrically connected to the drain of the first NMOS transistor and the input of the hysteresis inverter, respectively. The source of the first NMOS transistor is grounded. The power supply terminal of the hysteresis inverter is electrically connected to the first power supply, and the output terminal of the hysteresis inverter is electrically connected to the first two-stage inverter.

5. The power-on reset circuit according to claim 4, characterized in that, The hysteresis inverter includes: a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor; The gates of the first PMOS transistor, the second PMOS transistor, the second NMOS transistor, and the third NMOS transistor are all electrically connected to the source of the first NMOS transistor. The source of the first PMOS transistor is electrically connected to the drain of the second PMOS transistor and the source of the third PMOS transistor, respectively. The drain of the first PMOS transistor is electrically connected to the drain of the third NMOS transistor, the gate of the third PMOS transistor, and the gate of the fourth NMOS transistor, respectively. The source of the second PMOS transistor is electrically connected to the first power supply. The gate of the third PMOS transistor is electrically connected to the gate of the fourth NMOS transistor, and the drain of the third PMOS transistor is grounded. The source of the second NMOS transistor is grounded, and the drain of the second NMOS transistor is electrically connected to the source of the third NMOS transistor. The source of the fourth NMOS transistor is electrically connected to the first power supply, and the drain of the fourth NMOS transistor is electrically connected to the source of the third NMOS transistor and the drain of the second NMOS transistor.

6. The power-on reset circuit according to claim 2, characterized in that, The second power supply detection circuit includes: a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a first current mirror, and a second two-stage inverter. The first current mirror includes a fourth PMOS transistor and a fifth PMOS transistor. The source of the fifth NMOS transistor is grounded, the drain of the fifth NMOS transistor is electrically connected to the source of the sixth NMOS transistor, the gates of the fifth NMOS transistor and the sixth NMOS transistor are both electrically connected to the second power supply, and the drain of the sixth NMOS transistor is electrically connected to the gate of the fourth PMOS transistor, the drain of the fourth PMOS transistor, and the gate of the fifth PMOS transistor, respectively. The source of the seventh NMOS transistor is grounded, the drain of the seventh NMOS transistor is electrically connected to the source of the eighth NMOS transistor, the gates of the seventh NMOS transistor and the eighth NMOS transistor are both electrically connected to the first power supply, and the drain of the eighth NMOS transistor is electrically connected to the drain of the fifth PMOS transistor, the gate of the ninth NMOS transistor, and the input terminal of the second two-stage inverter, respectively. The source of the ninth NMOS transistor is electrically connected to the drain of the seventh NMOS transistor and the source of the eighth NMOS transistor, respectively, and the drain of the ninth NMOS transistor is electrically connected to the second power supply. The source of the fourth PMOS transistor and the source of the fifth PMOS transistor are both electrically connected to the second power supply. The power supply terminals of the second two-stage inverter are electrically connected to the first power supply.

7. The power-on reset circuit according to claim 6, characterized in that, The third power supply detection circuit includes: a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a second current mirror, and a third two-stage inverter. The second current mirror includes a sixth PMOS transistor and a seventh PMOS transistor. The source of the tenth NMOS transistor is grounded, the drain of the tenth NMOS transistor is electrically connected to the source of the eleventh NMOS transistor, the gates of the tenth NMOS transistor and the eleventh NMOS transistor are both electrically connected to the third power supply, and the drain of the eleventh NMOS transistor is electrically connected to the gate of the sixth PMOS transistor, the drain of the sixth PMOS transistor, and the gate of the seventh PMOS transistor, respectively. The source of the twelfth NMOS transistor is grounded, the drain of the twelfth NMOS transistor is electrically connected to the source of the thirteenth NMOS transistor, the gates of the twelfth NMOS transistor and the thirteenth NMOS transistor are both electrically connected to the first power supply, and the drain of the thirteenth NMOS transistor is electrically connected to the drain of the seventh PMOS transistor, the gate of the fourteenth NMOS transistor, and the input terminal of the third two-stage inverter, respectively. The source of the fourteenth NMOS transistor is electrically connected to the drain of the twelfth NMOS transistor and the source of the thirteenth NMOS transistor, respectively, and the drain of the fourteenth NMOS transistor is electrically connected to the third power supply. The source of the sixth PMOS transistor and the source of the seventh PMOS transistor are both electrically connected to the third power supply. The power supply terminal of the third two-stage inverter is electrically connected to the first power supply.

8. The power-on reset circuit according to claim 7, characterized in that, The first current mirror and the second current mirror have different mirror ratios. The second preset detection threshold is determined based on the first preset detection threshold and the mirror ratio of the first current mirror. The third preset detection threshold is determined based on the first preset detection threshold and the mirror ratio of the second current mirror.

9. A chip, characterized in that, The chip includes a power-on reset circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, The electronic device includes a power-on reset circuit as described in any one of claims 1 to 8.

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