Image audio signal display driving circuit

Abstract

The utility model relates to an image audio signal display drive circuit, which comprises a main control chip, an HDM I signal processing module, an LVDS output module, an audio power amplifier module and a power supply module, HDM I signals are accessed to the HDM I signal processing module, the output end of the HDM I signal processing module is connected with the main control chip, and the output end of the LVDS output module is connected with the audio power amplifier module. The main control chip outputs an image signal to the LVDS output module, the audio power amplifier module receives an audio signal output by the main control chip and an external PC audio signal, the audio power amplifier module outputs an audio signal, and the power supply module outputs a power supply signal to the main control chip. The problems of poor signal integrity, imperfect power management, poor reliability and the like are effectively solved, the user experience is greatly improved, and the image quality, the response speed, the color accuracy and the like are ensured to meet the requirements of users.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic circuits, and particularly relates to an image and audio signal display driving circuit. Background Art

[0002] A display driving board is an electronic component specifically used to control pixels of display devices such as liquid crystal displays (LCDs) or organic light-emitting diodes (OLEDs). Its main function is to receive image data from a PC, main board, etc., and convert this data into electrical signals for controlling each pixel. It usually integrates one or more driving chips, which are responsible for generating the required row and column control signals, as well as adjusting pixel brightness and color. These signals are then transmitted to the pixel units on the display panel through a series of delicate circuits and wires. According to different display technologies and application requirements, different interface standards can also be output, such as LVDS (Low Voltage Differential Signaling), MIPI (Mobile Industry Processor Interface), eDP (Enhanced DisplayPort), etc. These interface standards define the data transmission rate, format, and electrical characteristics to ensure reliable signal transmission and clear image display. During the design process of the entire driving board, signal integrity affects the image quality, power management affects the power consumption of the whole machine, and compatibility affects the adaptation of different main boards. Summary of the Invention

[0003] The utility model provides an image and audio signal display driving circuit, aiming to solve the problem that the existing driving board has poor compatibility with different interfaces.

[0004] The utility model provides an image and audio signal display driving circuit, including a main control chip, an HDMI signal processing module, an LVDS output module, an audio power amplifier module, and a power supply module. The HDMI signal processing module accesses an HDMI signal, the output end of the HDMI signal processing module is connected to the main control chip, the main control chip outputs an image signal to the LVDS output module, the audio power amplifier module receives the audio signal output by the main control chip and an external PC audio signal, the audio power amplifier module outputs an audio signal, and the power supply module outputs a power supply signal to the main control chip.

[0005] As a further improvement of the present utility model, the power supply module includes a DC power input interface JP1, a PH power input interface JP2, a power supply chip U1, a power supply chip U2, and a power supply chip U3. The DC power input interface JP1 and the PH power input interface JP2 are respectively connected to a DC 12V voltage. The DC power input interface JP1 is connected to a capacitor C7. The pin 1 of the DC power input interface JP1 and the pin 1 of the PH power input interface JP2 are both connected to one end of a fuse F1. The other end of the fuse F1 outputs a 12V voltage to the power supply chip U1, the power supply chip U2, and the power supply chip U3. The power supply chip U1 outputs a 5V voltage, the power supply chip U2 outputs a 3.3V voltage, and the power supply chip U3 outputs a 1V voltage.

[0006] As a further improvement of the present utility model, the power supply module further includes a backlight power control interface JP3. The pins 5 and 6 of the backlight power control interface JP3 are connected to a 12V voltage. The pin 3 of the backlight power control interface JP3 is connected to the collector of a triode Q1. The base of the triode Q1 is connected to the pin 34 of the main control chip. The pin 4 of the backlight power control interface JP3 is connected to the pin 35 of the main control chip.

[0007] As a further improvement of the present utility model, the HDMI signal processing module includes an HDMI signal input interface D1, an anti-interference chip UX1, and an anti-interference chip UX2. The HDMI signal input interface D1 is connected to an HDMI signal. The pin 1 of the HDMI signal input interface D1 is connected to the pin 9 of the anti-interference chip UX1. The pin 2 of the anti-interference chip UX1 is connected to the pin 17 of the main control chip. The pin 3 of the HDMI signal input interface D1 is connected to the pin 10 of the anti-interference chip UX1. The pin 1 of the anti-interference chip UX1 is connected to the pin 16 of the main control chip. The pin 4 of the HDMI signal input interface D1 is connected to the pin 6 of the anti-interference chip UX1. The pin 5 of the anti-interference chip UX1 is connected to the pin 15 of the main control chip. The pin 6 of the HDMI signal input interface D1 is connected to the pin 7 of the anti-interference chip UX1. The pin 4 of the anti-interference chip UX1 is connected to the pin 14 of the main control chip. The pin 7 of the HDMI signal input interface D1 is connected to the pin 9 of the anti-interference chip UX2. The pin 2 of the anti-interference chip UX2 is connected to the pin 12 of the main control chip. The pin 9 of the HDMI signal input interface D1 is connected to the pin 10 of the anti-interference chip UX2. The pin 1 of the anti-interference chip UX2 is connected to the pin 11 of the main control chip. The pin 10 of the HDMI signal input interface D1 is connected to the pin 6 of the anti-interference chip UX2. The pin 5 of the anti-interference chip UX2 is connected to the pin 18 of the main control chip. The pin 12 of the HDMI signal input interface D1 is connected to the pin 7 of the anti-interference chip UX2. The pin 4 of the anti-interference chip UX2 is connected to the pin 19 of the main control chip.

[0008] As a further improvement of the present utility model, the LVDS output module includes an LVDS signal output interface JP5. The 1st, 2nd, and 3rd pins of the LVDS signal output interface JP5 are connected to the drain of the field effect transistor Q3. The source of the field effect transistor Q3 is respectively connected to 12V, 5V, and 3.3V voltages. The gate of the field effect transistor Q3 is connected to the collector of the triode Q4. The base of the triode Q4 is connected to the 97th pin of the main control chip. The 88th pin of the main control chip is connected to the 7th pin of the LVDS signal output interface JP5. The 87th pin of the main control chip is connected to the 8th pin of the LVDS signal output interface JP5. The 86th pin of the main control chip is connected to the 9th pin of the LVDS signal output interface JP5. The 85th pin of the main control chip is connected to the 10th pin of the LVDS signal output interface JP5. The 84th pin of the main control chip is connected to the 11th pin of the LVDS signal output interface JP5. The 83rd pin of the main control chip is connected to the 12th pin of the LVDS signal output interface JP5. The 82nd pin of the main control chip is connected to the 15th pin of the LVDS signal output interface JP5. The 81st pin of the main control chip is connected to the 16th pin of the LVDS signal output interface JP5. The 80th pin of the main control chip is connected to the 17th pin of the LVDS signal output interface JP5. The 79th pin of the main control chip is connected to the 18th pin of the LVDS signal output interface JP5. The 74th pin of the main control chip is connected to the 19th pin of the LVDS signal output interface JP5. The 73rd pin of the main control chip is connected to the 20th pin of the LVDS signal output interface JP5. The 72nd pin of the main control chip is connected to the 21st pin of the LVDS signal output interface JP5. The 71st pin of the main control chip is connected to the 22nd pin of the LVDS signal output interface JP5. The 70th pin of the main control chip is connected to the 23rd pin of the LVDS signal output interface JP5. The 69th pin of the main control chip is connected to the 24th pin of the LVDS signal output interface JP5. The 68th pin of the main control chip is connected to the 29th pin of the LVDS signal output interface JP5. The 87th pin of the main control chip is connected to the 30th pin of the LVDS signal output interface JP5.

[0009] As a further improvement of the present utility model, the audio power amplifier module includes an audio power amplifier chip U7, a PCAudio input interface JP7, and an audio output interface CN1. The 6th pin of the audio power amplifier chip U7 is connected to the 58th pin of the main control chip, the 3rd pin of the audio power amplifier chip U7 is connected to the 59th pin of the main control chip, the 7th pin of the audio power amplifier chip U7 is connected to the 115th pin of the main control chip, the 2nd pin of the audio power amplifier chip U7 is connected to the 65th pin of the main control chip. The PCAudio input interface JP7 receives an external PC audio signal and transmits it to the audio power amplifier chip U7. The 11th pin of the audio power amplifier chip U7 is connected to the 1st pin of the audio output interface CN1, the 9th pin of the audio power amplifier chip U7 is connected to the 2nd pin of the audio output interface CN1, the 16th pin of the audio power amplifier chip U7 is connected to the 3rd pin of the audio output interface CN1, and the 14th pin of the audio power amplifier chip U7 is connected to the 4th pin of the audio output interface CN1.

[0010] As a further improvement of the present utility model, it further includes a Flash chip U5, and the 3rd pin of the Flash chip U5 is connected to the 96th pin of the main control chip.

[0011] As a further improvement of the present utility model, it further includes a key control interface JP4. The 1st pin of the key control interface JP4 is connected to the 102nd pin of the main control chip, the 2nd pin of the key control interface JP4 is connected to the 94th pin of the main control chip, the 3rd pin of the key control interface JP4 is connected to the 93rd pin of the main control chip, the 4th pin of the key control interface JP4 is connected to the 92nd pin of the main control chip, the 5th pin of the key control interface JP4 is connected to the 91st pin of the main control chip, the 7th pin of the key control interface JP4 is connected to the 43rd pin of the main control chip, the 8th pin of the key control interface JP4 is connected to the 42nd pin of the main control chip, and the 9th pin of the key control interface JP4 is connected to the 90th pin of the main control chip.

[0012] As a further improvement of the present utility model, it further includes a debugging interface JP8. The 2nd pin of the debugging interface JP8 is connected to the 101st pin of the main control chip, and the 3rd pin of the debugging interface JP8 is connected to the 100th pin of the main control chip.

[0013] As a further improvement of the present utility model, the model of the main control chip is 2525BR.

[0014] The beneficial effects of the present utility model are as follows: effectively solving problems such as poor signal integrity, imperfect power management, and poor reliability, greatly improving the user experience, and ensuring that aspects such as image quality, response speed, and color accuracy meet the needs of users. Description of the Drawings

[0015] Figure 1 It is a relationship diagram of each module in the circuit of the present utility model;

[0016] Figure 2 It is a specific circuit connection diagram of the main control chip of the present utility model;

[0017] Figure 3 It is a specific circuit connection diagram of the power supply module of the present utility model;

[0018] Figure 4 It is a specific circuit connection diagram of the HDMI signal processing module of the present utility model;

[0019] Figure 5 It is a specific circuit connection diagram of the LVDS output module of the present utility model;

[0020] Figure 6 It is a specific circuit connection diagram of the audio power amplifier module of the present utility model;

[0021] Figure 7 It is a specific circuit connection diagram of the Flash chip of the present utility model;

[0022] Figure 8 It is a specific circuit connection diagram of the key control interface of the present utility model;

[0023] Figure 9 It is a specific circuit connection diagram of the debugging interface of the present utility model. Detailed implementation manners

[0024] In order to make the objectives, technical solutions and advantages of the present utility model clearer and more understandable, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments.

[0025] As Figures 1-9 shown, the present utility model provides an image and audio signal display driving circuit, including a main control chip, an HDMI signal processing module, an LVDS output module, an audio power amplifier module and a power supply module. The HDMI signal processing module accesses an HDMI signal. The output end of the HDMI signal processing module is connected to the main control chip. The main control chip outputs an image signal to the LVDS output module. The audio power amplifier module receives the audio signal output by the main control chip and an external PC audio signal. The audio power amplifier module outputs an audio signal. The power supply module outputs a power signal to the main control chip.

[0026] As an embodiment of the present utility model, the power supply module includes a DC power input interface JP1, a PH power input interface JP2, a power supply chip U1, a power supply chip U2, and a power supply chip U3. The DC power input interface JP1 and the PH power input interface JP2 are respectively connected to a DC 12V voltage. The DC power input interface JP1 is connected to a capacitor C7. The 1-pin of the DC power input interface JP1 and the 1-pin of the PH power input interface JP2 are both connected to one end of a fuse F1. The other end of the fuse F1 outputs a 12V voltage to the power supply chip U1, the power supply chip U2, and the power supply chip U3. The power supply chip U1 outputs a 5V voltage, the power supply chip U2 outputs a 3.3V voltage, and the power supply chip U3 outputs a 1V voltage.

[0027] As another embodiment of the present utility model, the power supply module further includes a backlight power control interface JP3. The 5th and 6th pins of the backlight power control interface JP3 are connected to a 12V voltage. The 3rd pin of the backlight power control interface JP3 is connected to the collector of a triode Q1. The base of the triode Q1 is connected to the 34th pin of the main control chip. The 4th pin of the backlight power control interface JP3 is connected to the 35th pin of the main control chip.

[0028] As another embodiment of the present utility model, the HDMI signal processing module includes an HDMI signal input interface D1, an anti-interference chip UX1, and an anti-interference chip UX2. The HDMI signal input interface D1 is connected to an HDMI signal. The 1-pin of the HDMI signal input interface D1 is connected to the 9th pin of the anti-interference chip UX1. The 2nd pin of the anti-interference chip UX1 is connected to the 17th pin of the main control chip. The 3rd pin of the HDMI signal input interface D1 is connected to the 10th pin of the anti-interference chip UX1. The 1st pin of the anti-interference chip UX1 is connected to the 16th pin of the main control chip. The 4th pin of the HDMI signal input interface D1 is connected to the 6th pin of the anti-interference chip UX1. The 5th pin of the anti-interference chip UX1 is connected to the 15th pin of the main control chip. The 6th pin of the HDMI signal input interface D1 is connected to the 7th pin of the anti-interference chip UX1. The 4th pin of the anti-interference chip UX1 is connected to the 14th pin of the main control chip. The 7th pin of the HDMI signal input interface D1 is connected to the 9th pin of the anti-interference chip UX2. The 2nd pin of the anti-interference chip UX2 is connected to the 12th pin of the main control chip. The 9th pin of the HDMI signal input interface D1 is connected to the 10th pin of the anti-interference chip UX2. The 1st pin of the anti-interference chip UX2 is connected to the 11th pin of the main control chip. The 10th pin of the HDMI signal input interface D1 is connected to the 6th pin of the anti-interference chip UX2. The 5th pin of the anti-interference chip UX2 is connected to the 18th pin of the main control chip. The 12th pin of the HDMI signal input interface D1 is connected to the 7th pin of the anti-interference chip UX2. The 4th pin of the anti-interference chip UX2 is connected to the 19th pin of the main control chip.

[0029] As another embodiment of the present utility model, the LVDS output module includes an LVDS signal output interface JP5. The 1st, 2nd, and 3rd pins of the LVDS signal output interface JP5 are connected to the drain of the field effect transistor Q3. The source of the field effect transistor Q3 is respectively connected to 12V, 5V, and 3.3V voltages. The gate of the field effect transistor Q3 is connected to the collector of the triode Q4. The base of the triode Q4 is connected to the 97th pin of the main control chip. The 88th pin of the main control chip is connected to the 7th pin of the LVDS signal output interface JP5. The 87th pin of the main control chip is connected to the 8th pin of the LVDS signal output interface JP5. The 86th pin of the main control chip is connected to the 9th pin of the LVDS signal output interface JP5. The 85th pin of the main control chip is connected to the 10th pin of the LVDS signal output interface JP5. The 84th pin of the main control chip is connected to the 11th pin of the LVDS signal output interface JP5. The 83rd pin of the main control chip is connected to the 12th pin of the LVDS signal output interface JP5. The 82nd pin of the main control chip is connected to the 15th pin of the LVDS signal output interface JP5. The 81st pin of the main control chip is connected to the 16th pin of the LVDS signal output interface JP5. The 80th pin of the main control chip is connected to the 17th pin of the LVDS signal output interface JP5. The 79th pin of the main control chip is connected to the 18th pin of the LVDS signal output interface JP5. The 74th pin of the main control chip is connected to the 19th pin of the LVDS signal output interface JP5. The 73rd pin of the main control chip is connected to the 20th pin of the LVDS signal output interface JP5. The 72nd pin of the main control chip is connected to the 21st pin of the LVDS signal output interface JP5. The 71st pin of the main control chip is connected to the 22nd pin of the LVDS signal output interface JP5. The 70th pin of the main control chip is connected to the 23rd pin of the LVDS signal output interface JP5. The 69th pin of the main control chip is connected to the 24th pin of the LVDS signal output interface JP5. The 68th pin of the main control chip is connected to the 29th pin of the LVDS signal output interface JP5. The 87th pin of the main control chip is connected to the 30th pin of the LVDS signal output interface JP5.

[0030] As another embodiment of the present utility model, the audio power amplifier module includes an audio power amplifier chip U7, a PCAudio input interface JP7, and an audio output interface CN1. The 6th pin of the audio power amplifier chip U7 is connected to the 58th pin of the main control chip, the 3rd pin of the audio power amplifier chip U7 is connected to the 59th pin of the main control chip, the 7th pin of the audio power amplifier chip U7 is connected to the 115th pin of the main control chip, the 2nd pin of the audio power amplifier chip U7 is connected to the 65th pin of the main control chip. The PCAudio input interface JP7 receives an external PC audio signal and transmits it to the audio power amplifier chip U7. The 11th pin of the audio power amplifier chip U7 is connected to the 1st pin of the audio output interface CN1, the 9th pin of the audio power amplifier chip U7 is connected to the 2nd pin of the audio output interface CN1, the 16th pin of the audio power amplifier chip U7 is connected to the 3rd pin of the audio output interface CN1, and the 14th pin of the audio power amplifier chip U7 is connected to the 4th pin of the audio output interface CN1.

[0031] As another embodiment of the present utility model, it further includes a Flash chip U5, and the 3rd pin of the Flash chip U5 is connected to the 96th pin of the main control chip.

[0032] As another embodiment of the present utility model, it further includes a key control interface JP4. The 1st pin of the key control interface JP4 is connected to the 102nd pin of the main control chip, the 2nd pin of the key control interface JP4 is connected to the 94th pin of the main control chip, the 3rd pin of the key control interface JP4 is connected to the 93rd pin of the main control chip, the 4th pin of the key control interface JP4 is connected to the 92nd pin of the main control chip, the 5th pin of the key control interface JP4 is connected to the 91st pin of the main control chip, the 7th pin of the key control interface JP4 is connected to the 43rd pin of the main control chip, the 8th pin of the key control interface JP4 is connected to the 42nd pin of the main control chip, and the 9th pin of the key control interface JP4 is connected to the 90th pin of the main control chip.

[0033] As another embodiment of the present utility model, it further includes a debugging interface JP8. The 2nd pin of the debugging interface JP8 is connected to the 101st pin of the main control chip, and the 3rd pin of the debugging interface JP8 is connected to the 100th pin of the main control chip.

[0034] As another embodiment of the present utility model, the model of the main control chip is 2525BR.

[0035] The utility model provides an image and audio signal display driving circuit, which adopts the latest series of main control chips of RTD2525, and has the characteristics of stable data transmission, strong compatibility, stable working performance, multiple interface selection, energy saving and consumption reduction; and domestic high-performance power supply chips. It effectively solves the problems of poor signal integrity, imperfect power management, and poor reliability, greatly improves the user experience, and ensures that the image quality, response speed, color accuracy, etc. meet the needs of users.

[0036] The specific circuit connection diagram is as shown in the attached Figures 2-9 specification, where JP1 is the DC2.0 power input interface, JP2 is the PH-2.0 power input interface, JP3 is the backlight power control interface, JP4 is the button control interface, JP5 is the LVDS signal output interface, JP6 is the TTL output interface, JP7 is the PC Audio input interface, JP8 is the debugging interface, CN1 is the audio output interface, D1 is the HDMI signal input interface, U6 is the 2525BR main control chip, U7 is the audio power amplifier chip, and U5 is the Flash chip.

[0037] As Figure 3 shown, the external device inputs a DC12V power supply, which is input through the DC power input interface or the PH power input interface JP2, filtered by the capacitor C7, reaches the fuse F1, and after being filtered by the capacitors E1, C5, C3, C10, C15, it is transmitted to the power supply chips U1, U2, and U3. After step-down and filtering processing, DC5V, DC3.3V, and DC1V voltages are respectively output to provide a stable power supply for the entire system. The external device inputs a DC12V power supply, which is input through the DC power input interface or the PH power input interface JP2, filtered by the capacitor C7, reaches the fuse F1, and is transmitted to the backlight power control interface JP3 after being filtered by the inductors L4, C18, C19 to provide voltage for the external backlight module. The voltage output by the power supply is transmitted to the voltage selection resistors R40, R41, R43, and after being controlled by the triode Q3 and the field effect transistor Q4, and filtered by the capacitors EC1, C49, it is transmitted to the LVDS signal output interface JP5 to provide voltage for the external TCON board.

[0038] As Figure 4 shown, the external device outputs an HDMI signal, which is transmitted through a wire to the HDMI signal input interface D1. After being filtered by the anti-interference chips UX1 and UX2, it is input to the main control chip U6. After the operation and conversion of the main control chip, it is output to the LVDS signal output interface JP5 to provide an image signal for the external TCON board.

[0039] As Figure 6As shown, the external PC audio signal is transmitted to the PC Audio input interface JP7. After filtering, it is transmitted to the audio power amplifier chip U7. After processing, operation, and amplification, it is transmitted to the audio output interface CN1 to provide an audio signal for external audio devices. The external device outputs an HDMI audio signal, which is transmitted through a wire to the HDMI signal input interface D1. After filtering by the anti-interference chips UX1 and UX2, it is input to the main control chip U6. After the operation and conversion of the main control chip, it is transmitted to the audio power amplifier chip U7. After processing, operation, and amplification, it is transmitted to the audio output interface CN1 to provide an audio signal for external audio devices.

[0040] As Figure 8 shown, the action of the external button and the issued button control signal are transmitted to the button control interface JP4. After pull-up and matching processing by the RP2 and RP3 network resistors, it is transmitted to the main control chip U6. After the operation and conversion of the main control chip U6, corresponding commands are output.

[0041] The main control chip U6 issues an instruction. After being processed and controlled by the triode Q1 and the resistors R48, R49, and R14, it is transmitted to the backlight power control interface P3 to control the switch and brightness of the external backlight module.

[0042] As Figure 7 shown, some operation data of the main control chip is transmitted to the Flash chip U5 for storage. When needed, it is transmitted to the main control chip U6 for calling.

[0043] As Figure 9 shown, during the operation of the main control chip U6, some data signals occur. After pull-up processing by the resistors R62 and R63, they are transmitted to the debugging interface JP8, which facilitates designers to understand the operation of the main control chip U6 in real time.

[0044] The above content is a further detailed description of the present utility model in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present utility model is only limited to these descriptions. For those of ordinary skill in the technical field to which the present utility model belongs, without departing from the concept of the present utility model, several simple deductions or substitutions can still be made, which should all be regarded as belonging to the protection scope of the present utility model.

Claims

1. An image and audio signal display driving circuit, characterized in that: It includes a main control chip, an HDMI signal processing module, an LVDS output module, an audio power amplifier module and a power module. The HDMI signal processing module receives the HDMI signal, the output end of the HDMI signal processing module is connected to the main control chip, the main control chip outputs an image signal to the LVDS output module, the audio power amplifier module receives the audio signal output by the main control chip and the external PC audio signal, the audio power amplifier module outputs an audio signal, and the power module outputs a power signal to the main control chip.

2. The image and audio signal display driving circuit according to claim 1, characterized in that: The power module includes a DC power input interface JP1, a PH power input interface JP2, a power chip U1, a power chip U2 and a power chip U3. The DC power input interface JP1 and the PH power input interface JP2 are respectively connected to a DC 12V voltage. The DC power input interface JP1 is connected to a capacitor C7. Pin 1 of the DC power input interface JP1 and pin 1 of the PH power input interface JP2 are both connected to one end of a fuse F1. The other end of the fuse F1 outputs a 12V voltage to the power chip U1, the power chip U2 and the power chip U3. The power chip U1 outputs a 5V voltage, the power chip U2 outputs a 3.3V voltage, and the power chip U3 outputs a 1V voltage.

3. The image and audio signal display driving circuit according to claim 2, characterized in that: The power module also includes a backlight power control interface JP3, pins 5 and 6 of the backlight power control interface JP3 are connected to a 12V voltage, pin 3 of the backlight power control interface JP3 is connected to the collector of the transistor Q1, the base of the transistor Q1 is connected to pin 34 of the main control chip, and pin 4 of the backlight power control interface JP3 is connected to pin 35 of the main control chip.

4. The image and audio signal display driving circuit according to claim 1, characterized in that: The HDMI signal processing module includes an HDMI signal input interface D1, an anti-interference chip UX1 and an anti-interference chip UX2. The HDMI signal input interface D1 is connected to the HDMI signal. Pin 1 of the HDMI signal input interface D1 is connected to pin 9 of the anti-interference chip UX1, pin 2 of the anti-interference chip UX1 is connected to pin 17 of the main control chip, pin 3 of the HDMI signal input interface D1 is connected to pin 10 of the anti-interference chip UX1, pin 1 of the anti-interference chip UX1 is connected to pin 16 of the main control chip, pin 4 of the HDMI signal input interface D1 is connected to pin 6 of the anti-interference chip UX1, pin 5 of the anti-interference chip UX1 is connected to pin 15 of the main control chip, pin 6 of the HDMI signal input interface D1 is connected to pin 17 of the main control chip, 1, pin 4 of the anti-interference chip UX1 is connected to pin 14 of the main control chip, pin 7 of the HDMI signal input interface D1 is connected to pin 9 of the anti-interference chip UX2, pin 2 of the anti-interference chip UX2 is connected to pin 12 of the main control chip, pin 9 of the HDMI signal input interface D1 is connected to pin 10 of the anti-interference chip UX2, pin 1 of the anti-interference chip UX2 is connected to pin 11 of the main control chip, pin 10 of the HDMI signal input interface D1 is connected to pin 6 of the anti-interference chip UX2, pin 5 of the anti-interference chip UX2 is connected to pin 18 of the main control chip, pin 12 of the HDMI signal input interface D1 is connected to pin 7 of the anti-interference chip UX2, and pin 4 of the anti-interference chip UX2 is connected to pin 19 of the main control chip.

5. The image and audio signal display driving circuit according to claim 1, characterized in that: The LVDS output module includes an LVDS signal output interface JP5, wherein the 1, 2, and 3 pins of the LVDS signal output interface JP5 are connected to the drain of the field effect tube Q3, the source of the field effect tube Q3 is respectively connected to 12V, 5V, and 3.3V voltages, the gate of the field effect tube Q3 is connected to the collector of the transistor Q4, the base of the transistor Q4 is connected to the 97th pin of the main control chip, the 88th pin of the main control chip is connected to the 7th pin of the LVDS signal output interface JP5, and the 87th pin of the main control chip is connected to the LVDS signal The 8th pin of the main control chip is connected to the 8th pin of the LVDS signal output interface JP5, the 86th pin of the main control chip is connected to the 9th pin of the LVDS signal output interface JP5, the 85th pin of the main control chip is connected to the 10th pin of the LVDS signal output interface JP5, the 84th pin of the main control chip is connected to the 11th pin of the LVDS signal output interface JP5, the 83rd pin of the main control chip is connected to the 12th pin of the LVDS signal output interface JP5, the 82nd pin of the main control chip is connected to the 15th pin of the LVDS signal output interface JP5, the Pin 81 of the main control chip is connected to pin 16 of the LVDS signal output interface JP5, pin 80 of the main control chip is connected to pin 17 of the LVDS signal output interface JP5, pin 79 of the main control chip is connected to pin 18 of the LVDS signal output interface JP5, pin 74 of the main control chip is connected to pin 19 of the LVDS signal output interface JP5, pin 73 of the main control chip is connected to pin 20 of the LVDS signal output interface JP5, pin 72 of the main control chip is connected to pin 21 of the LVDS signal output interface JP5, pin 71 of the main control chip is connected to pin 22 of the LVDS signal output interface JP5, pin 70 of the main control chip is connected to pin 23 of the LVDS signal output interface JP5, pin 69 of the main control chip is connected to pin 24 of the LVDS signal output interface JP5, pin 68 of the main control chip is connected to pin 29 of the LVDS signal output interface JP5, and pin 87 of the main control chip is connected to pin 30 of the LVDS signal output interface JP5.

6. The image and audio signal display driving circuit according to claim 1, characterized in that: The audio power amplifier module includes an audio power amplifier chip U7, a PC Audio input interface JP7 and an audio output interface CN1. Pin 6 of the audio power amplifier chip U7 is connected to pin 58 of the main control chip, pin 3 of the audio power amplifier chip U7 is connected to pin 59 of the main control chip, pin 7 of the audio power amplifier chip U7 is connected to pin 115 of the main control chip, pin 2 of the audio power amplifier chip U7 is connected to pin 65 of the main control chip, the PC Audio input interface JP7 receives an external PC audio signal and transmits it to the audio power amplifier chip U7, pin 11 of the audio power amplifier chip U7 is connected to pin 1 of the audio output interface CN1, pin 9 of the audio power amplifier chip U7 is connected to pin 2 of the audio output interface CN1, pin 16 of the audio power amplifier chip U7 is connected to pin 3 of the audio output interface CN1, and pin 14 of the audio power amplifier chip U7 is connected to pin 4 of the audio output interface CN1.

7. The image and audio signal display driving circuit according to claim 1, characterized in that: It also includes a Flash chip U5, and the 3rd pin of the Flash chip U5 is connected to the 96th pin of the main control chip.

8. The image and audio signal display driving circuit according to claim 1, characterized in that: It also includes a key control interface JP4, wherein pin 1 of the key control interface JP4 is connected to pin 102 of the main control chip, pin 2 of the key control interface JP4 is connected to pin 94 of the main control chip, pin 3 of the key control interface JP4 is connected to pin 93 of the main control chip, pin 4 of the key control interface JP4 is connected to pin 92 of the main control chip, pin 5 of the key control interface JP4 is connected to pin 91 of the main control chip, pin 7 of the key control interface JP4 is connected to pin 43 of the main control chip, pin 8 of the key control interface JP4 is connected to pin 42 of the main control chip, and pin 9 of the key control interface JP4 is connected to pin 90 of the main control chip.

9. The image and audio signal display driving circuit according to claim 1, characterized in that: It also includes a debugging interface JP8, wherein pin 2 of the debugging interface JP8 is connected to pin 101 of the main control chip, and pin 3 of the debugging interface JP8 is connected to pin 100 of the main control chip.

10. The image and audio signal display driving circuit according to claim 1, characterized in that: The model of the main control chip is 2525BR.

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