Parallel operation detection control circuit

Abstract

The utility model provides a parallel operation detection control circuit. The parallel operation detection control circuit comprises a first sampling module, a second sampling module and a parallel operation control module, the first sampling module is used for collecting a first voltage and a second voltage, and outputting a first control signal when the phase of the first voltage and the phase of the second voltage are complementary. Wherein the first voltage is the voltage between the first live wire and the first null line, and the second voltage is the voltage between the second live wire and the second null line; the second sampling module is used for collecting a third voltage and outputting a second control signal when the third voltage is greater than a preset threshold value; wherein the third voltage is the voltage between the first live wire and the second live wire; the parallel operation control module is used for controlling the first null line to be connected with the second null line when receiving the first control signal and the second control signal. The parallel operation detection control circuit controls the zero lines of the two energy storage systems to be connected when voltage phases output by the two energy storage systems are complementary, and the situation of parallel operation abnormity can be avoided.

Description

Technical Field

[0001] This application belongs to the technical field of energy storage, and particularly relates to a parallel connection detection and control circuit. Background Art

[0002] The parallel connection technology is a technology that superimposes the output powers of two or more energy storage devices and then outputs them to an electrical device to supply power to the electrical device.

[0003] When two energy storage devices are connected in parallel, the controller will control the phases of the output voltages of the two energy storage devices to be complementary. If the phases of the output voltages of the two energy storage devices are not complementary, the electrical device connected to the two energy storage devices may not work properly at this time, and may even damage the electrical device. Utility Model Content

[0004] The embodiment of this application provides a parallel connection detection circuit, which can detect whether the phases of the output voltages of two energy storage machines are complementary, and control the connection of the neutral lines of the two energy storage machines when it is detected that the phases of the output voltages of the two energy storage machines are complementary, so as to prevent abnormal parallel connection.

[0005] The embodiment of this application provides a parallel connection detection and control circuit. The parallel connection detection and control circuit is connected to a double-phase-fire parallel connection circuit. The double-phase-fire parallel connection circuit includes a first energy storage system and a second energy storage system. The first energy storage system includes a first phase-fire line and a first neutral line, and the second energy storage system includes a second phase-fire line and a second neutral line. The parallel connection detection and control circuit includes a first sampling module, a second sampling module and a parallel connection control module. The first sampling module is respectively connected to the parallel connection control module, the first phase-fire line, the first neutral line, the second phase-fire line and the second neutral line. The second sampling module is respectively connected to the parallel connection control module, the first phase-fire line and the second phase-fire line. The parallel connection control module is also respectively connected to the first neutral line and the second neutral line. The first sampling module is used to collect a first voltage and a second voltage, and output a first control signal when the phase of the first voltage is complementary to the phase of the second voltage. Wherein, the first voltage is the voltage between the first phase-fire line and the first neutral line, and the second voltage is the voltage between the second phase-fire line and the second neutral line. The second sampling module is used to collect a third voltage and output a second control signal when the third voltage is greater than a preset threshold. Wherein, the third voltage is the voltage between the first phase-fire line and the second phase-fire line. The parallel connection control module is used to control the connection of the first neutral line and the second neutral line when receiving the first control signal and the second control signal.

[0006] In some embodiments, the parallel operation control module includes a switch unit and a control unit; a first input end of the switch unit is connected to the second sampling module, a second input end of the switch unit is connected to the first sampling module, an output end of the switch unit is connected to a control end of the control unit, and the control unit is further connected to the first neutral line and the second neutral line respectively; the switch unit is configured to output a first level signal when receiving the first control signal and the second control signal; the control unit is configured to control the connection between the first neutral line and the second neutral line when receiving the first level signal.

[0007] In some embodiments, the switch unit includes a first switch sub-unit, a second switch sub-unit and a third switch sub-unit; a control end of the first switch sub-unit is connected to an output end of the second sampling module, an output end of the first switch sub-unit is connected to a control end of the second switch sub-unit, an output end of the second switch sub-unit is connected to a control end of the third switch sub-unit, an input end of the third switch sub-unit is connected to an output end of the first sampling module, and an output end of the third switch sub-unit is connected to the control unit; the first switch sub-unit is configured to conduct when receiving the second control signal; the second switch sub-unit is configured to conduct when the first switch sub-unit conducts; the third switch sub-unit is configured to output the first level signal when receiving the first control signal and the second switch sub-unit conducts.

[0008] In some embodiments, the control unit includes a switching transistor Q4, a relay RLY1, a resistor R2 and a resistor R28; a first end of the resistor R2 is connected to an output end of the third switch sub-unit, a second end of the resistor R2 is connected to a control end of the switching transistor Q4 and a first end of the resistor R28, a first end of the switching transistor Q4 is connected to a first power supply through a coil of the relay RLY1, a third end of the switching transistor Q4 is connected to a second end of the resistor R28 and grounded, a common contact of the relay RLY1 is connected to the first neutral line, and a normally open contact of the relay RLY1 is connected to the second neutral line.

[0009] In some embodiments, the first sampling module includes a first sampling unit, a second sampling unit, and a first detection unit; a first input end of the first sampling unit is connected to the first live wire, a second input end of the first sampling unit is connected to the first neutral wire, a first input end of the second sampling unit is connected to the second live wire, a second input end of the second sampling unit is connected to the second neutral wire, output ends of the first sampling unit and the second sampling unit are both connected to an input end of the first detection unit, and an output end of the first detection unit is connected to the parallel operation control module; the first sampling unit is configured to collect the voltage of the first live wire and the voltage of the first neutral wire and generate the first voltage; the second sampling unit is configured to collect the voltage of the second live wire and the voltage of the second neutral wire and generate the second voltage; the first detection unit is configured to output the first control signal when the phase of the first voltage is complementary to the phase of the second voltage.

[0010] In some embodiments, the first detection unit includes a first charge and discharge sub-unit and a first detection sub-unit; an input end of the first charge and discharge sub-unit is connected to both the output end of the first sampling unit and the output end of the second sampling unit, an output end of the first charge and discharge sub-unit is connected to an input end of the first detection sub-unit, and an output end of the first detection sub-unit is connected to the parallel operation control module; the first charge and discharge sub-unit is configured to cut off when the phase of the first voltage is complementary to the phase of the second voltage; the first detection sub-unit is configured to output the first control signal when the first charge and discharge sub-unit cuts off.

[0011] In some embodiments, the first charge and discharge sub-unit includes a diode D3, a resistor R3, a resistor R6, and a capacitor C6; a positive electrode of the diode D3, a first end of the resistor R6, the output end of the first sampling unit, and the output end of the second sampling unit are all connected, a negative electrode of the diode D3 is connected to a first end of the resistor R3, a second end of the resistor R6, a second end of the resistor R3, a first end of the capacitor C6, and an input end of the first detection sub-unit are all connected, and a second end of the capacitor C6 is grounded.

[0012] In some embodiments, the second sampling module includes a third sampling unit and a second detection unit; a first input end of the third sampling unit is connected to the first live wire, a second input end of the third sampling unit is connected to the second live wire, an output end of the third sampling unit is connected to an input end of the second detection unit, and an output end of the second detection unit is connected to the parallel operation control module; the third sampling unit is configured to collect the voltage of the first live wire and the voltage of the second live wire and generate the third voltage; the second detection unit is configured to output the second control signal when the third voltage is greater than the preset threshold.

[0013] In some embodiments, the second detection unit includes a second charge and discharge sub-unit and a second detection sub-unit; an input end of the second charge and discharge sub-unit is connected to the output end of the third sampling unit, an output end of the second charge and discharge sub-unit is connected to an input end of the second detection sub-unit, and an output end of the second detection sub-unit is connected to the parallel operation control module; the second charge and discharge sub-unit is configured to output a first voltage signal when the third voltage is greater than the preset threshold; the second detection sub-unit is configured to output the second control signal when receiving the first voltage signal.

[0014] In some embodiments, the parallel operation detection and control circuit further includes an indication module; the indication module is connected to the parallel operation control module; the indication module is configured to indicate the working state of the parallel operation detection and control circuit.

[0015] The embodiment of the present application provides a parallel operation detection and control circuit. The parallel operation detection and control circuit samples the voltages at the output ends of two energy storage systems and determines whether the voltage phases output by the two energy storage systems are complementary. When the voltage phases output by the two energy storage systems are complementary, the neutral wires of the two energy storage systems are controlled to be connected, which can avoid the situation of abnormal parallel operation. By accurately detecting parameters such as voltage and phase, it is ensured that the two energy storage systems are connected in parallel under suitable conditions, reducing system fluctuations and failures caused by improper parallel operation, and improving the stability of the entire parallel operation system. The accurate detection and control mechanism reduces the risk of errors in the parallel operation, improves the reliability of the entire parallel operation system, and reduces the possibility of unexpected shutdowns and equipment damage. Description of the Drawings

[0016] One or more embodiments are exemplarily illustrated by corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings represent similar elements, unless otherwise stated, and the drawings in the figures do not constitute a proportional limitation.

[0017] Figure 1 is a structural block diagram of a parallel operation detection and control circuit provided by an embodiment of the present application;

[0018] Figure 2 It is a schematic diagram of the first live wire, the first neutral wire, the second live wire, and the second neutral wire provided by an embodiment of the present application;

[0019] Figure 3 It is a structural block diagram of the first sampling module provided by an embodiment of the present application;

[0020] Figure 4 It is a schematic diagram of the circuit structures of the first sampling unit and the second sampling unit provided by an embodiment of the present application;

[0021] Figure 5 It is a schematic diagram of the circuit structure of the first detection unit provided by an embodiment of the present application;

[0022] Figure 6 It is a structural block diagram of the second sampling module provided by an embodiment of the present application;

[0023] Figure 7 It is a schematic diagram of the circuit structure of the third sampling unit provided by an embodiment of the present application;

[0024] Figure 8 It is a schematic diagram of the circuit structure of the second detection unit provided by an embodiment of the present application;

[0025] Figure 9 It is a structural block diagram of the parallel operation control module provided by an embodiment of the present application;

[0026] Figure 10 It is a schematic diagram of the circuit structure of the switch unit provided by an embodiment of the present application;

[0027] Figure 11 It is a schematic diagram of the circuit structure of the control unit provided by an embodiment of the present application;

[0028] Figure 12 It is a structural block diagram of the parallel operation detection control circuit provided by another embodiment of the present application;

[0029] Figure 13 It is a schematic diagram of the circuit structure of the indication module provided by an embodiment of the present application. Detailed implementation manners

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and detailedly described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0031] In each of the embodiments of the present application described below, the technical features involved do not conflict with each other and can be combined with each other.

[0032] When an element is expressed as "connected to" another element, it can be directly connected to the other element, or there can be one or more intermediate elements therebetween.

[0033] The terms "first", "second", etc. in the description and claims of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are usually of the same category, and the number of objects is not limited. For example, the first object can be one or more.

[0034] In addition, "and / or" in the description and claims means at least one of the connected objects, and the character " / " generally means that the associated objects before and after are in an "or" relationship.

[0035] Please refer to Figure 1 , Figure 1 which is a structural block diagram of the parallel connection detection and control circuit 100 provided by an embodiment of the present application.

[0036] An embodiment of the present application provides a parallel connection detection and control circuit 100. The parallel connection detection and control circuit 100 is connected to a two-phase hot wire parallel connection circuit, and the two-phase hot wire parallel connection circuit includes a first energy storage system and a second energy storage system. As Figure 1 shown, the first energy storage system includes a first hot wire AC_L1 and a first neutral wire AC_N1, and the second energy storage system includes a second hot wire AC_L2 and a second neutral wire AC_N2.

[0037] The parallel connection detection and control circuit 100 provided by the embodiment of the present application includes a first sampling module 10, a second sampling module 20, and a parallel connection control module 30.

[0038] Among them, the first sampling module 10 is respectively connected to the parallel connection control module 30, the first hot wire AC_L1, the first neutral wire AC_N1, the second hot wire AC_L2, and the second neutral wire AC_N2. The second sampling module 20 is respectively connected to the parallel connection control module 30, the first hot wire AC_L1, and the second hot wire AC_L2. The parallel connection control module 30 is also respectively connected to the first neutral wire AC_N1 and the second neutral wire AC_N2.

[0039] Specifically, the first sampling module 10 is configured to collect a first voltage and a second voltage, and output a first control signal when the phases of the first voltage and the second voltage are complementary. Herein, the first voltage is the voltage between the first live wire AC_L1 and the first neutral wire AC_N1, and the second voltage is the voltage between the second live wire AC_L2 and the second neutral wire AC_N2. The second sampling module 20 is configured to collect a third voltage, and output a second control signal when the third voltage is greater than a preset threshold. Herein, the third voltage is the voltage between the first live wire AC_L1 and the second live wire AC_L2. The parallel connection control module 30 is configured to control the connection between the first neutral wire AC_N1 and the second neutral wire AC_N2 when receiving the first control signal and the second control signal.

[0040] In practical applications, as Figure 2 shown, when the first energy storage system and the second energy storage system are successfully paralleled, the phases of the voltages of the first live wire AC_L1 and the second live wire AC_L2 will differ by 180 degrees. It should be noted that in the embodiments of the present application, the phases of the voltages of the first live wire AC_L1 and the second live wire AC_L2 are controlled by a controller, and there are two cases for the first live wire AC_L1 and the second live wire AC_L2: in-phase and a phase difference of 180 degrees.

[0041] Based on this, the parallel connection detection and control circuit 100 provided in the embodiments of the present application includes a first sampling module 10, a second sampling module 20, and a parallel connection control module 30. The first sampling module 10 is used to detect whether the first voltage and the second voltage are complementary in phase, and output a first control signal when the first voltage and the second voltage are complementary in phase. The second sampling module 20 is used to detect whether the third voltage is greater than a preset threshold, and output a second control signal when the third voltage is greater than the preset threshold. Finally, when the parallel connection control module 30 receives the first control signal and the second control signal, the parallel connection control module 30 will control the connection between the first neutral wire AC_N1 and the second neutral wire AC_N2.

[0042] In the embodiments of the present application, by first detecting whether the phases between the first live wire AC_L1 and the second live wire AC_L2 are complementary, and then controlling the connection between the first neutral wire AC_N1 and the second neutral wire AC_N2 only when the phases of the first live wire AC_L1 and the second live wire AC_L2 are complementary, the parallel connection of the first energy storage system and the second energy storage system is completed. When the phases of the first live wire AC_L1 and the second live wire AC_L2 are not complementary, the first neutral wire AC_N1 and the second neutral wire AC_N2 will not be connected, effectively avoiding the occurrence of abnormal parallel connection. It should be noted that in this embodiment, phase complementarity means a phase difference of 180°, that is, the voltage phases output by the two energy storage systems differ by 180°.

[0043] Please refer to Figure 3 , Figure 3It is a structural block diagram of the first sampling module 10 provided by an embodiment of the present application.

[0044] In some embodiments, the first sampling module 10 includes a first sampling unit 11, a second sampling unit 12, and a first detection unit 13.

[0045] Among them, the first input terminal of the first sampling unit 11 is connected to the first live wire AC_L1, the second input terminal of the first sampling unit 11 is connected to the first neutral wire AC_N1, the first input terminal of the second sampling unit 12 is connected to the second live wire AC_L2, the second input terminal of the second sampling unit 12 is connected to the second neutral wire AC_N2, the output terminals of the first sampling unit 11 and the second sampling unit 12 are both connected to the input terminal of the first detection unit 13, and the output terminal of the first detection unit 13 is connected to the parallel machine control module 30.

[0046] Specifically, the first sampling unit 11 is used to collect the voltage of the first live wire AC_L1 and the voltage of the first neutral wire AC_N1, and generate a first voltage. The second sampling unit 12 is used to collect the voltage of the second live wire AC_L2 and the voltage of the second neutral wire AC_N2, and generate a second voltage. The first detection unit 13 is used to output a first control signal when the phase of the first voltage is complementary to the phase of the second voltage.

[0047] In some embodiments, the first detection unit 13 includes a first charge and discharge sub-unit 131 and a first detection sub-unit 132.

[0048] Among them, the input terminal of the first charge and discharge sub-unit 131 is connected to both the output terminals of the first sampling unit 11 and the second sampling unit 12, the output terminal of the first charge and discharge sub-unit 131 is connected to the input terminal of the first detection sub-unit 132, and the output terminal of the first detection sub-unit 132 is connected to the parallel machine control module 30.

[0049] Specifically, the first charge and discharge sub-unit 131 is used to cut off when the phase of the first voltage is complementary to the phase of the second voltage. The first detection sub-unit 132 is used to output a first control signal when the first charge and discharge sub-unit 131 cuts off.

[0050] Please refer to Figure 4 , Figure 4 It is a schematic circuit diagram of the first sampling unit 11 and the second sampling unit 12 provided by an embodiment of the present application.

[0051] In some embodiments, as Figure 2 and Figure 4 shown, the first sampling unit 11 includes an amplifier U1A, resistors R5, R8, R9, R10, R11, R43, R44, R101, R102, capacitors C4, C8.

[0052] Specifically, the first end of resistor R8 is connected to the first live wire AC_L1 through resistor R102, and the first end of resistor R10 is connected to the first neutral wire AC_N1 through resistor R101. The first end of resistor R8 is also connected to the first end of resistor R9, and the first end of resistor R10 is also connected to the second end of resistor R9. The non-inverting input terminal of amplifier U1A is connected to the second end of resistor R8, the first end of resistor R5, and the first end of capacitor C4. The second end of capacitor C4 and the second end of resistor R5 are connected and grounded. The inverting input terminal of amplifier U1A is connected to the second end of resistor R10, the first end of resistor R11, and the first end of capacitor C8. The output terminal of amplifier U1A is connected to resistor R43, and the second end of resistor R43 is connected to the second end of resistor R11, the second end of capacitor C8, and the first end of resistor R44. The second end of resistor R44 is connected to the first detection unit 13.

[0053] In some embodiments, as Figure 2 and Figure 4 shown, the second sampling unit 12 includes amplifier U1B, resistors R17, R22, R23, R27, R30, R45, R46, R104, R105, capacitors C10, C17.

[0054] Specifically, the first end of resistor R22 is connected to the second live wire AC_L2 through resistor R105, and the first end of resistor R27 is connected to the second neutral wire AC_N2 through resistor R104. The first end of resistor R22 is also connected to the first end of resistor R23, and the first end of resistor R27 is also connected to the second end of resistor R23. The non-inverting input terminal of amplifier U1B is connected to the second end of resistor R22, the first end of resistor R17, and the first end of capacitor C10. The second end of capacitor C10 and the second end of resistor R17 are connected and grounded. The inverting input terminal of amplifier U1B is connected to the second end of resistor R27, the first end of resistor R30, and the first end of capacitor C17. The output terminal of amplifier U1B is connected to resistor R45, and the second end of resistor R45 is connected to the second end of resistor R30, the second end of capacitor C17, and the first end of resistor R46. The second end of resistor R46 is connected to the first detection unit 13.

[0055] Please refer to Figure 5 , Figure 5 which is a schematic circuit diagram of the first detection unit 13 provided by an embodiment of the present application.

[0056] In some embodiments, as Figure 5 shown, the first charge and discharge sub-unit 131 includes diode D3, resistors R3, R6 and capacitor C6.

[0057] Specifically, the positive electrode of diode D3, the first end of resistor R6, the output end of the first sampling unit 11, and the output end of the second sampling unit 12 are all connected. The negative electrode of diode D3 is connected to the first end of resistor R3. The second end of resistor R6, the second end of resistor R3, the first end of capacitor C6, and the input end of the first detection sub-unit 132 are all connected. The second end of capacitor C6 is grounded.

[0058] In some embodiments, as Figure 5 shown, the first detection sub-unit 132 includes comparator U2A, resistors R12, R13, R14, R15, R16, resistor 18, resistor R19, and diode D4.

[0059] Specifically, the first end of resistor R12 is connected to the output end of the first charge and discharge sub-unit 131. The second end of resistor R12, the first end of resistor R14, and the inverting input end of comparator U2A are all connected. The first end of resistor R16 is connected to the second power supply. The second end of resistor R16, the first end of resistor R19, the non-inverting input end of comparator U2A, and the positive electrode of diode D4 are all connected. The negative electrode of diode D4 is connected to the first end of resistor R18. The second ends of resistor R14 and resistor R19 are both grounded. The output end of comparator U2A is connected to the first end of resistor R15 and the second end of resistor R18. The first end of resistor R13 is connected to the first power supply. The second end of resistor R15 is connected to the second end of resistor R13 and the parallel machine control module 30.

[0060] Among them, the first power supply is a +12V DC power supply. The second power supply is a 2.5V DC power supply. In some other embodiments, the voltages of the first power supply and the second power supply can be set according to actual situations.

[0061] The following combines Figure 2 、 Figure 4 and Figure 5 to illustrate the working principle of the first sampling module 10.

[0062] As Figure 2 shown, AC_L1_smp+ and AC_N1_smp- are the voltage sampling signals output from the first energy storage system to the first sampling module 10, and AC_L2_smp+ and AC_N2_smp- are the voltage sampling signals output from the second energy storage system to the first sampling module 10. Figure 4 The amplifiers U1A and U1B in

[0063] When the phases of the first live wire AC_L1 and the second live wire AC_L2 differ by 180 degrees, the voltage values of the first live wire AC_L1 and the second live wire AC_L2 are opposite numbers. The voltage values of the two sine waves collected by the amplifier U1A and the amplifier U1B differ by 180 degrees, that is, the voltage values of the two sine waves collected by the amplifier U1A and the amplifier U1B are superimposed to 0V. At this time, as Figure 4 shown, that is, the voltage at point A is 0V. At this time, the diode D3 is in the cut-off state, the voltage at the inverting input terminal of the comparator U2A is 0V, and the voltage at the non-inverting input terminal of the comparator U2A can be obtained by dividing the voltage by the resistors R19 and R16 to set the threshold value of the comparator U2A (for example, 0.625V). At this time, the voltage at the non-inverting input terminal of the comparator U2A is greater than the voltage at the inverting input terminal. Therefore, the comparator U2A does not flip, and the output terminal of the comparator U2A outputs a high level. As Figure 5 shown, RLY_N_B is pulled high by the first power supply (+12V power supply), that is, the voltage of RLY_N_B is pulled high. At this time, the voltage signal at RLY_N_B is the first control signal.

[0064] When the phases of the first live wire AC_L1 and the second live wire AC_L2 are the same, there are two cases. One case is that the voltages output by the first energy storage system and the second energy storage system are both in the positive half-axis, and the other case is that the voltages output by the first energy storage system and the second energy storage system are both in the negative half-axis. Taking the first sampling unit 11 as an example, the principle of the second sampling unit 12 is similar to that of the first sampling unit 11. At this time, the voltage at the output terminal of the amplifier U1A is the sampled value of the voltage output by the first energy storage system (for example, 100V), and AC_L1_smp+ and AC_N1_smp- are differentially amplified to the diode D3.

[0065] When the voltages output by the first energy storage system and the second energy storage system are both in the positive half-axis, a part of the voltage output by the first energy storage system charges the capacitor C6. Specifically, the capacitor C6 is charged through the amplifier U1A, the resistors R43, R44, R6, and the capacitor C6. Another part of the voltage output by the first energy storage system flows to the comparator U2A. Specifically, it flows to the comparator U2A through the amplifier U1A, the resistors R43, R44, the diode D3, the resistor R3, and the resistor R12. At this time, the voltage at the inverting input terminal of the comparator U2A is the first voltage value (for example, 1.71V), and the voltage at the non-inverting input terminal of the comparator U2A can be obtained by dividing the voltage by the resistors R19 and R16 to set the threshold value (for example, 0.625V). At this time, the comparator U2A will flip, and the output terminal of the comparator U2A outputs a low level, that is, the voltage of RLY_N_B is pulled low.

[0066] When the voltages output by the first energy storage system and the second energy storage system are both on the positive half-axis, the output at the output terminal of the amplifier U1A is a negative voltage at this time, and the capacitor C6 will start to discharge. By adjusting the resistance values of the resistor R6, the resistor R12, and the resistor R19, the charging voltage of the capacitor C6 can be made greater than the discharge voltage value of the capacitor C6, that is, the charging time of the capacitor C6 is faster than the discharge time in each cycle, which can make the capacitor C6 in a continuous charging process until the capacitor C6 is full. At this time, within 0.01 seconds on the negative half-axis, the voltage at the inverting input terminal of the comparator U2A is always greater than the voltage at the non-inverting input terminal, the comparator U2A flips, and the output terminal of the comparator U2A will output a low level, and the voltage of the RLY_N_B is pulled down.

[0067] In the first sampling module 10, the first sampling unit 11 collects the first voltage, and the second sampling unit 12 collects the second voltage. When the phases of the first voltage and the second voltage are complementary, the sum of the voltages at the output terminals of the first sampling unit 11 and the second sampling unit 12 is 0, and the first detection unit outputs a first control signal at this time. When the phases of the first voltage and the second voltage are the same (not complementary), the phases of the voltages at the output terminals of the first sampling unit 11 and the second sampling unit 12 are the same, and the voltage at the output terminal of the first detection unit 13 is pulled down at this time.

[0068] Please refer to Figure 6 , Figure 6 which is the structural block diagram of the second sampling module 20 provided by an embodiment of the present application.

[0069] In some embodiments, the second sampling module 20 includes a third sampling unit 21 and a second detection unit 22.

[0070] Among them, the first input terminal of the third sampling unit 21 is connected to the first live wire AC_L1, the second input terminal of the third sampling unit 21 is connected to the second live wire AC_L2, the output terminal of the third sampling unit 21 is connected to the input terminal of the second detection unit 22, and the output terminal of the second detection unit 22 is connected to the parallel machine control module 30.

[0071] Specifically, the third sampling unit 21 is used to collect the voltage of the first live wire AC_L1 and the voltage of the second live wire AC_L2, and generate a third voltage. The second detection unit 22 is used to output a second control signal when the third voltage is greater than a preset threshold.

[0072] Among them, the preset threshold is related to the components in the circuit and the connection relationship between the components, and can be set according to actual needs, and no specific limitation is made here.

[0073] In some embodiments, the second detection unit 22 includes a second charge and discharge sub-unit 221 and a second detection sub-unit 222.

[0074] Among them, the input end of the second charge and discharge sub-unit 221 is connected to the output end of the third sampling unit 21, the output end of the second charge and discharge sub-unit is connected to the input end of the second detection sub-unit 222, and the output end of the second detection sub-unit 222 is connected to the parallel machine control module 30.

[0075] Specifically, the second charge and discharge sub-unit 221 is configured to output a first voltage signal when the third voltage is greater than a preset threshold. The second detection sub-unit 222 is configured to output a second control signal when receiving the first voltage signal.

[0076] Please refer to Figure 7 , Figure 7 which is a schematic circuit diagram of the third sampling unit 21 provided by an embodiment of the present application.

[0077] In some embodiments, as shown in Figure 2 and Figure 7 , the third sampling unit 21 includes an amplifier U1C, resistors R20, R25, R26, R35, R41, R47, R103, R106, a capacitor C16, and a capacitor C21.

[0078] Specifically, the first end of the resistor R25 is connected to the first live wire AC_L1 through the resistor R103, and the first end of the resistor R35 is connected to the second live wire AC_L2 through the resistor R106. The first end of the resistor R25 is also connected to the first end of the resistor R26, and the first end of the resistor R35 is also connected to the second end of the resistor R26. The non-inverting input end of the amplifier U1C is connected to the second end of the resistor R25, the first end of the resistor R20, and the first end of the capacitor C16. The second end of the capacitor C16 and the second end of the resistor R20 are connected and grounded. The inverting input end of the amplifier U1C is connected to the second end of the resistor R35, the first end of the resistor R41, and the first end of the capacitor C21. The output end of the amplifier U1C is connected to the first end of the resistor R47, and the second end of the resistor R47 is connected to the second end of the resistor R41 and the second end of the capacitor C21. The second end of the resistor R47 is also connected to the second detection unit 22.

[0079] Please refer to Figure 8 , Figure 8 which is a schematic circuit diagram of the second detection unit 22 provided by an embodiment of the present application.

[0080] In some embodiments, as shown in Figure 8 , the second charge and discharge sub-unit 221 includes a diode D5, resistors R21, R31, and a capacitor C20.

[0081] Specifically, the positive electrode of diode D5, the first end of resistor R31, and the output end of the third sampling unit 21 are all connected. The negative electrode of diode D5 is connected to the first end of resistor R21. The second end of resistor R21, the second end of resistor R31, the first end of capacitor C20, and the input end of the second detection sub-unit 222 are all connected. The second end of capacitor C20 is grounded.

[0082] In some embodiments, as Figure 8 shown, the second detection sub-unit 222 includes comparator U2B, resistors R24, R29, R32, R38, R40, R42, R48, and diode D6.

[0083] Specifically, the first end of resistor R24 is connected to the output end of the second charge and discharge sub-unit 221. The second end of resistor R24, the first end of resistor R29, and the inverting input terminal of comparator U2B are all connected. The first end of resistor R38 is connected to the second power supply. The second end of resistor R38, the first end of resistor R42, the non-inverting input terminal of comparator U2B, and the positive electrode of diode D6 are all connected. The negative electrode of diode D6 is connected to the first end of resistor R40. The second ends of resistors R29 and R42 are both grounded. The output end of comparator U2B is connected to the first end of resistor R32 and the second end of resistor R40. The first end of resistor R48 is connected to the first power supply. The second end of resistor R48 is connected to the second end of resistor R32 and the parallel machine control module 30.

[0084] The following combines Figure 2 、 Figure 7 、 Figure 8 to illustrate the operating principle of the second sampling module 20.

[0085] When the phases of the first live wire AC_L1 and the second live wire AC_L2 differ by 180 degrees, AC_LL_smp+ is the voltage sampling signal output from the first energy storage system to the second sampling module 20, and AC_LL_smp- is the voltage sampling signal output from the second energy storage system to the second sampling module 20. At this time, the outputs of the two live wires after the amplifier U1C are sinusoidal high voltages (for example, the outputs of both live wires are 100V at a relatively low voltage. Since the phases of the two live wires are complementary at this time, the output of the amplifier U1C is a sampling voltage of 200V, so it can be called a high voltage). AC_LL_smp+ and AC_LL_smp- go through differential amplification to the resistors R47, diode D5, resistor R21, resistor R24, and reach the inverting input terminal of the comparator U2B. The voltage at the non-inverting input terminal of the comparator U2B is the voltage divided by resistor R42 after resistors R42 and R38 are connected in series. Among them, the threshold of the comparator U2B can be set by adjusting the resistance values of resistors R38 and R42 (for example, 2.08V). When the phases of the first live wire AC_L1 and the second live wire AC_L2 differ by 180 degrees, the voltage (for example, 2.5V) at the inverting input terminal of the comparator U2B is greater than the voltage (for example, 2.08V) at the non-inverting input terminal of the comparator U2B, and the comparator U2B will flip, pulling down RLY_N_A. At this time, the voltage of RLY_N_A is the second control signal.

[0086] When the phases of the first live wire AC_L1 and the second live wire AC_L2 are the same, or when the live wires and the neutral wires of the two energy storage systems are not connected, AC_LL_smp+ and AC_LL_smp- go through differential amplification to the resistors R47, diode D5, resistor R21, resistor R24, and the voltage at the inverting input terminal of the comparator U2B is less than the voltage (for example, 2.08V) at the non-inverting input terminal of the comparator U2B. At this time, the comparator U2B does not flip, and the voltage of RLY_N_A is pulled up.

[0087] In the first sampling module 10, the third voltage is collected by the third sampling unit. When the third voltage is greater than the preset threshold, the voltage at the output terminal of the third sampling unit 11 is relatively high. At this time, the second detection unit 22 outputs the second control signal. When the phases of the first voltage and the second voltage are the same (not complementary), the voltage at the output terminal of the third sampling unit 11 is relatively high. At this time, the output of the second detection unit 22 is pulled up.

[0088] Please refer to Figure 9 , Figure 9 which is the structural block diagram of the parallel control module 30 provided by an embodiment of the present application.

[0089] In some embodiments, the parallel control module 30 includes a switch unit 31 and a control unit 32.

[0090] Among them, the first input end of the switch unit 31 is connected to the second sampling module 20, the second input end of the switch unit 31 is connected to the first sampling module 10, the output end of the switch unit 31 is connected to the control end of the control unit 32, and the control unit 32 is also respectively connected to the first neutral line AC_N1 and the second neutral line AC_N2;

[0091] Specifically, the switch unit 31 is configured to output a first level signal when receiving a first control signal and a second control signal. The control unit 32 is configured to control the connection between the first neutral line AC_N1 and the second neutral line AC_N2 when receiving the first level signal.

[0092] In some embodiments, the switch unit 31 includes a first switch sub-unit 311, a second switch sub-unit 312, and a third switch sub-unit 313.

[0093] Among them, the control end of the first switch sub-unit 311 is connected to the output end of the second sampling module 20, the output end of the first switch sub-unit 311 is connected to the control end of the second switch sub-unit 312, the output end of the second switch sub-unit 312 is connected to the control end of the third switch sub-unit 313, the input end of the third switch sub-unit 313 is connected to the output end of the first sampling module 10, and the output end of the third switch sub-unit 313 is connected to the control unit 32.

[0094] Specifically, the first switch sub-unit 311 is configured to conduct when receiving the second control signal. The second switch sub-unit 312 is configured to conduct when the first switch sub-unit 311 conducts. The third switch sub-unit 313 is configured to output a first level signal when receiving the first control signal and the second switch sub-unit 312 conducts.

[0095] Please refer to Figure 10 , Figure 10 which is a schematic circuit diagram of the switch unit 31 provided by an embodiment of the present application.

[0096] In one embodiment, the first switch sub-unit 311 includes a switching transistor Q2, a resistor R1, and a resistor R4. Specifically, the control end of the switching transistor Q2 is connected to the output end of the second sampling module 20 through the resistor R4, the second end of the switching transistor Q2 is connected to the first power supply through the resistor R1, and the third end of the switching transistor Q2 is connected to the control end of the second switch sub-unit 312.

[0097] In this embodiment, the switching transistor Q2 is a PNP type triode. Among them, the base of the triode is the control end of the switching transistor Q2, the emitter of the triode is the second end of the switching transistor Q2, and the collector of the triode is the third end of the switching transistor Q2. In some other embodiments, the switching transistor Q2 can be an NPN type triode, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or other suitable switching transistors.

[0098] In some embodiments, the second switching sub-unit 312 includes a switching transistor Q3, a resistor R33, a resistor 36, and a resistor R39. Specifically, the control end of the switching transistor Q3 is connected to the output end of the first switching sub-unit 311 through the resistor R36. The control end of the switching transistor Q3 is also connected to the second end of the resistor R39. The second end of the switching transistor Q3 is connected to the first end of the resistor R39 and grounded. The third end of the switching transistor Q3 is connected to the first power supply through the resistor R33. The third end of the switching transistor Q3 is also connected to the control end of the third switching sub-unit 313.

[0099] In this embodiment, the switching transistor Q3 is an NPN type triode. Among them, the base of the triode is the control end of the switching transistor Q3, the emitter of the triode is the second end of the switching transistor Q3, and the collector of the triode is the third end of the switching transistor Q3. In some other embodiments, the switching transistor Q3 can be a PNP type triode, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or other suitable switching transistors.

[0100] In some embodiments, the third switching sub-unit 313 includes a switching transistor Q1, a resistor R34, and a resistor R37. Specifically, the control end of the switching transistor Q1 is connected to the output end of the second switching sub-unit 312 through the resistor R34. The second end of the switching transistor Q1 is connected to the output end of the first sampling module 10. The third end of the switching transistor Q1 is grounded through the resistor R37. The third end of the switching transistor Q1 is also connected to the control unit 32.

[0101] In this embodiment, the switching transistor Q1 is a PNP type triode. Among them, the base of the triode is the control end of the switching transistor Q1, the emitter of the triode is the second end of the switching transistor Q1, and the collector of the triode is the third end of the switching transistor Q1. In some other embodiments, the switching transistor Q1 can be an NPN type triode, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or other suitable switching transistors.

[0102] Please refer to Figure 11 , Figure 11 which is a schematic circuit diagram of the control unit 32 provided by an embodiment of the present application.

[0103] In some embodiments, as Figure 11 shown, the control unit 32 includes a switching transistor Q4, a relay RLY1, a resistor R2, and a resistor R28. Among them, the first end of the resistor R2 is connected to the output end of the third switching sub-unit 313, the second end of the resistor R2 is connected to the control end of the switching transistor Q4 and the first end of the resistor R28, the first end of the switching transistor Q4 is connected to the first power supply through the coil of the relay RLY1, the third end of the switching transistor Q4 is connected to the second end of the resistor R28 and grounded, the common contact of the relay RLY1 is connected to the first neutral line AC_N1, and the normally open contact of the relay RLY1 is connected to the second neutral line AC_N2.

[0104] In this embodiment, the switching transistor Q4 is an NPN-type triode. Among them, the base of the triode is the control end of the switching transistor Q4, the emitter of the triode is the third end of the switching transistor Q4, and the collector of the triode is the first end of the switching transistor Q4. In some other embodiments, the switching transistor Q4 can be a PNP-type triode, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or other suitable switching transistors.

[0105] The following combines Figure 10 and Figure 11 to illustrate the working principle of the parallel control module 30.

[0106] When the phases of the first live wire AC_L1 and the second live wire AC_L2 differ by 180 degrees, as Figure 10 shown, RLY_N_A is pulled low, passes through the resistor R4 to the base of the switching transistor Q2, and the switching transistor Q2 is turned on. Passes through the resistor R36 to the base of the switching transistor Q3, and the switching transistor Q3 is turned on. At this time, the resistor R34 is pulled low, so that the base of the switching transistor Q1 is pulled low, causing the switching transistor Q1 to be turned on. At this time, RLY_N and RLY_N_B are connected and pulled high, as Figure 11 shown, passes through the resistor R2 to the switching transistor Q4. The base of the switching transistor Q4 is pulled high, and the switching transistor Q4 is turned on. Thus, the relay RLY1 closes. At this time, the first live wire AC_L1 and the second live wire AC_L2 are the combined output L / N wires.

[0107] When the phases of the first live wire AC_L1 and the second live wire AC_L2 are the same, as Figure 10As shown, RLY_N_A is pulled high, passing through resistor R4 to the base of switch transistor Q2, and switch transistor Q2 is cut off and non-conductive. At this time, as Figure 11 shown, RLY_N is at a low level. Therefore, relay RLY1 is not closed, and the first live wire AC_L1 and the second live wire AC_L2 are not the L / N wires of the combined output.

[0108] Please refer to Figure 12 , Figure 12 which is the structural block diagram of the parallel operation detection and control circuit 100 provided by another embodiment of the present application.

[0109] In some embodiments, the parallel operation detection and control circuit 100 further includes an indication module 40. Among them, the indication module 40 is connected to the parallel operation control module 30.

[0110] Specifically, the indication module 40 is used to indicate the working state of the parallel operation detection and control circuit 100.

[0111] Among them, the working state of the parallel operation detection and control circuit 100 includes the state of parallel operation and the state of non-parallel operation.

[0112] Please refer to Figure 13 , Figure 13 which is the schematic circuit diagram of the indication module 40 provided by an embodiment of the present application.

[0113] In some embodiments, the indication module 40 includes a light-emitting diode LED1, a switch transistor Q5, a resistor R49, a resistor R50, a resistor R51, and a resistor R52.

[0114] Specifically, the control end of the switch transistor Q5 is connected to the parallel operation control module 30 through the resistor R51. The first end of the switch transistor Q5 is also connected to the second end of the resistor R52. The second end of the switch transistor Q5 is connected to the first end of the resistor R52 and grounded. The third end of the switch transistor Q5 is connected to the negative electrode of the light-emitting diode LED1. The positive electrode of the light-emitting diode LED1 is sequentially connected to the first power supply through the resistor R50 and the resistor R49.

[0115] In this embodiment, the switch transistor Q5 is an NPN-type triode. Among them, the base of the triode is the control end of the switch transistor Q5, the emitter of the triode is the second end of the switch transistor Q5, and the collector of the triode is the third end of the switch transistor Q5. In some other embodiments, the switch transistor Q5 can be a PNP-type triode, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or other suitable switch transistors.

[0116] The following will explain the operating principle of the indication module 40 in combination with Figure 13 this.

[0117] As Figure 13 shown, when RLY_N is pulled high, it goes through resistor R51 to the base of switching transistor Q5. At this time, switching transistor Q5 is turned on, and then light-emitting diode LED1 lights up. Thus, it indicates that the operating state of the parallel connection detection control circuit 100 is the parallel connection state.

[0118] When RLY_N is pulled low, switching transistor Q5 is cut off and does not work. At this time, light-emitting diode LED1 does not light up. Thus, it indicates that the operating state of the parallel connection detection control circuit 100 is the non-parallel connection state.

[0119] The embodiment of the present application provides a parallel connection detection control circuit 100. The parallel connection detection control circuit 100 samples the voltages at the output ends of two energy storage systems, and determines whether the voltage phases output by the two energy storage systems are complementary. When the voltage phases output by the two energy storage systems are complementary, it controls the connection of the neutral lines of the two energy storage systems, which can avoid the situation of abnormal parallel connection. By accurately detecting parameters such as voltage and phase, it ensures that the two energy storage systems are connected in parallel under appropriate conditions, reduces system fluctuations and faults caused by improper parallel connection, and improves the stability of the operation of the entire parallel connection system. The accurate detection and control mechanism reduces the risk of errors in the parallel connection operation, improves the reliability of the entire parallel connection system, and reduces the possibility of unexpected shutdowns and equipment damage.

[0120] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; under the idea of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other variations in different aspects of the present invention as described above. For the sake of brevity, they are not provided in detail; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A parallel detection control circuit, characterized in that: The parallel detection control circuit is connected to a dual-live parallel circuit, the dual-live parallel circuit includes a first energy storage system and a second energy storage system, the first energy storage system includes a first live wire and a first neutral wire, and the second energy storage system includes a second live wire and a second neutral wire; The parallel detection control circuit includes a first sampling module, a second sampling module and a parallel control module; The first sampling module is respectively connected to the parallel control module, the first live wire, the first neutral wire, the second live wire and the second neutral wire, the second sampling module is respectively connected to the parallel control module, the first live wire and the second live wire, and the parallel control module is also respectively connected to the first neutral wire and the second neutral wire; The first sampling module is used to collect a first voltage and a second voltage, and output a first control signal when the phase of the first voltage is complementary to the phase of the second voltage; wherein the first voltage is the voltage between the first live wire and the first neutral wire, and the second voltage is the voltage between the second live wire and the second neutral wire; The second sampling module is used to collect a third voltage and output a second control signal when the third voltage is greater than a preset threshold; wherein the third voltage is a voltage between the first live wire and the second live wire; The parallel control module is used for controlling the first neutral line to be connected to the second neutral line when receiving the first control signal and the second control signal.

2. The parallel detection control circuit according to claim 1, characterized in that: The parallel control module includes a switch unit and a control unit; The first input end of the switch unit is connected to the second sampling module, the second input end of the switch unit is connected to the first sampling module, the output end of the switch unit is connected to the control end of the control unit, and the control unit is also connected to the first neutral line and the second neutral line respectively; The switch unit is used for outputting a first level signal when receiving the first control signal and the second control signal; The control unit is used for controlling the first neutral line to be connected to the second neutral line when receiving the first level signal.

3. The parallel detection control circuit according to claim 2, characterized in that: The switch unit includes a first switch sub-unit, a second switch sub-unit and a third switch sub-unit; The control end of the first switch subunit is connected to the output end of the second sampling module, the output end of the first switch subunit is connected to the control end of the second switch subunit, the output end of the second switch subunit is connected to the control end of the third switch subunit, the input end of the third switch subunit is connected to the output end of the first sampling module, and the output end of the third switch subunit is connected to the control unit; The first switch subunit is configured to be turned on upon receiving the second control signal; The second switch subunit is used to be turned on when the first switch subunit is turned on; The third switch sub-unit is configured to output the first level signal when the first control signal is received and the second switch sub-unit is turned on.

4. The parallel detection control circuit according to claim 3, characterized in that: The control unit includes a switch tube Q4, a relay RLY1, a resistor R2 and a resistor R28; The first end of the resistor R2 is connected to the output end of the third switch sub-unit, the second end of the resistor R2 is connected to the control end of the switch tube Q4 and the first end of the resistor R28, the first end of the switch tube Q4 is connected to the first power supply through the coil of the relay RLY1, the third end of the switch tube Q4 is connected to the second end of the resistor R28 and grounded, the common contact of the relay RLY1 is connected to the first neutral line, and the normally open contact of the relay RLY1 is connected to the second neutral line.

5. The parallel detection control circuit according to claim 1, characterized in that: The first sampling module includes a first sampling unit, a second sampling unit and a first detection unit; The first input end of the first sampling unit is connected to the first live wire, the second input end of the first sampling unit is connected to the first neutral wire, the first input end of the second sampling unit is connected to the second live wire, the second input end of the second sampling unit is connected to the second neutral wire, the output end of the first sampling unit and the output end of the second sampling unit are both connected to the input end of the first detection unit, and the output end of the first detection unit is connected to the parallel control module; The first sampling unit is used for collecting the voltage of the first live line and the voltage of the first neutral line, and generating the first voltage; The second sampling unit is used for collecting the voltage of the second live line and the voltage of the second neutral line, and generating the second voltage; The first detection unit is configured to output the first control signal when a phase of the first voltage is complementary to a phase of the second voltage.

6. The parallel detection control circuit according to claim 5, characterized in that: The first detection unit includes a first charge and discharge electronic unit and a first detection subunit; The input end of the first charge-discharge electronic unit is connected to the output end of the first sampling unit and the output end of the second sampling unit, the output end of the first charge-discharge electronic unit is connected to the input end of the first detection subunit, and the output end of the first detection subunit is connected to the parallel control module; The first charge-discharge electronic unit is used to be cut off when the phase of the first voltage is complementary to the phase of the second voltage; The first detection subunit is used to output the first control signal when the first charge and discharge electronic unit is turned off.

7. The parallel detection control circuit according to claim 6, characterized in that: The first charge-discharge electronic unit includes a diode D3, a resistor R3, a resistor R6 and a capacitor C6; The anode of the diode D3, the first end of the resistor R6, the output end of the first sampling unit, and the output end of the second sampling unit are all connected, the cathode of the diode D3 is connected to the first end of the resistor R3, the second end of the resistor R6, the second end of the resistor R3, the first end of the capacitor C6, and the input end of the first detection subunit are all connected, and the second end of the capacitor C6 is grounded.

8. The parallel detection control circuit according to claim 1, characterized in that: The second sampling module includes a third sampling unit and a second detection unit; The first input end of the third sampling unit is connected to the first live wire, the second input end of the third sampling unit is connected to the second live wire, the output end of the third sampling unit is connected to the input end of the second detection unit, and the output end of the second detection unit is connected to the parallel control module; The third sampling unit is used for collecting the voltage of the first live wire and the voltage of the second live wire, and generating the third voltage; The second detection unit is used to output the second control signal when the third voltage is greater than the preset threshold.

9. The parallel detection control circuit according to claim 8, characterized in that: The second detection unit includes a second charge and discharge electronic unit and a second detection subunit; The input end of the second charge-discharge electronic unit is connected to the output end of the third sampling unit, the output end of the second charge-discharge electronic unit is connected to the input end of the second detection subunit, and the output end of the second detection subunit is connected to the parallel control module; The second charge-discharge electronic unit is used to output a first voltage signal when the third voltage is greater than a preset threshold; The second detection subunit is configured to output the second control signal upon receiving the first voltage signal.

10. The parallel detection control circuit according to any one of claims 1 to 9, characterized in that: The parallel detection control circuit also includes an indication module; The indication module is connected to the parallel control module; The indication module is used to indicate the working state of the parallel detection control circuit.

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