Asymmetric filter multi-way switch and communication equipment

Abstract

The utility model discloses an asymmetric filter multi-way switch and communication equipment. The asymmetric filter multi-way switch comprises a switch subset, a segmented filter bank, a second switch subset and a control circuit, wherein the high-frequency connection part in the first switch subset is connected with the input end of the segmented filter bank through one switch, and the low-frequency connection part in the first switch subset is connected with the input end of the segmented filter bank through at least two switches; the output end of the segmented filter bank is connected with the second switch subset; the control circuit is connected with the first switch subset and the second switch subset. The communication device comprises an asymmetric filter multi-way switch. According to the embodiment of the utility model, through the arrangement of the asymmetric switch structure, the number of single-end parallel sub-switch units in the whole switch structure can be reduced, so that the insertion loss caused by on-resistance and off-capacitance is reduced, and the insertion loss, the isolation degree and the bearing power of the switch can be greatly improved.

Description

Technical Field

[0001] The utility model relates to the technical field of radio frequency switches, in particular to an asymmetric filter multi-way switch and a communication device. Background Art

[0002] In the field of traditional high-power radio frequency switches, single-pole multi-throw radio frequency switches are basically symmetric. The symmetric switches are used for broadband multi-band ICs (the full name is Integrated Circuit, indicating integrated circuits) and radio frequency front-ends, and the insertion loss, isolation, and linearity of each switch path are almost the same.

[0003] On each switch path, insertion loss can also be achieved by means of gain compensation. For example, a grounded switch is added to each switch path to improve isolation, and a switch with a larger capacity is selected to improve power and linearity. However, each switch path has inherent characteristics of R_on (on-resistance) and C_off (off-capacitance) of the die unit, and it is difficult to achieve large fluctuations in insertion loss, power, isolation, linearity, and frequency response. Summary of the Invention

[0004] The utility model provides an asymmetric filter multi-way switch and a communication device, aiming to solve the problem that in the field of traditional high-power radio frequency switches in the prior art, symmetric switches are used, and the insertion loss, isolation, and linearity of each switch path are almost the same, and it is difficult to achieve large fluctuations in insertion loss, power, isolation, linearity, and frequency response.

[0005] In a first aspect, the utility model proposes an asymmetric filter multi-way switch, which includes: a first switch subset, a segmented filter group, a second switch subset, and a control circuit;

[0006] Wherein, the high-frequency connection part in the first switch subset is connected to the input end of the segmented filter group through a switch, and the low-frequency connection part in the first switch subset is connected to the input end of the segmented filter group through at least two switches; the output end of the segmented filter group is connected to the second switch subset; the control circuit is connected to both the first switch subset and the second switch subset.

[0007] According to an embodiment of the present application, the switch subset includes two or more switch subsets, and the first switch subset is sequentially denoted as the first-level switch subset to the Nth-level switch subset in ascending order; where N is the total number of switch subsets included in the switch subset.

[0008] According to an embodiment of the present application, the first-stage switch in the first switch subset and the input end of the subset are used to be connected to the transmitting path, and the Nth-stage switch and the output end of the subset are sequentially connected to the antenna port through the segmented filter bank and the second switch subset, or connected to the receiving path.

[0009] According to an embodiment of the present application, the first switch subset includes two switch subsets, which are sequentially denoted as the first-stage switch subset and the second-stage switch subset in the order from the lower level to the higher level.

[0010] According to an embodiment of the present application, the first end of the first-stage switch subset is used to be connected to the transmitting path, the second end of the first-stage switch subset is connected to the first end of the second-stage switch subset, and the second end of the first-stage switch subset is also connected to the segmented filter bank; the second end of the second-stage switch subset is connected to the segmented filter bank.

[0011] According to an embodiment of the present application, the segmented filter bank includes at least two segmented filter bank subsets, which are respectively denoted as the first segmented filter bank subset and the second segmented filter bank subset; wherein, the second end of the first-stage switch subset is connected to the first segmented filter bank subset, and the second end of the second-stage switch subset is connected to the second segmented filter bank subset.

[0012] According to an embodiment of the present application, the first-stage switch subset includes a first single-pole four-throw switch; the second-stage switch subset includes a second single-pole four-throw switch;

[0013] The first end of the first single-pole four-throw switch is used as the first input end of the first switch and is connected to the transmitting path; one of the output ends of the second end of the first single-pole four-throw switch is used as the fourth output end of the first switch and is connected to the first end of the second single-pole four-throw switch; the first output end of the first switch, the second output end of the first switch, and the third output end of the first switch among the second ends of the first single-pole four-throw switch form the high-frequency connection part, and are respectively connected to the first segmented filter bank subset in a parallel manner; the second output end of the second switch to the fourth output end of the second switch among the second ends of the second single-pole four-throw switch form the low-frequency connection part, and are respectively connected to the second segmented filter bank subset in a parallel manner.

[0014] According to an embodiment of the present application, the first segmented filter bank subset includes a first filter, a second filter, and a third filter; the input end of the first filter is connected to the first output end of the first switch, the input end of the second filter is connected to the second output end of the first switch, and the input end of the third filter is connected to the third output end of the first switch;

[0015] The second sub - set of the segmented filter bank includes a fourth filter, a fifth filter, a sixth filter, and a seventh filter; the input end of the fourth filter is connected to the first output end of the second switch, the input end of the fifth filter is connected to the second output end of the second switch, the input end of the sixth filter is connected to the third output end of the second switch, and the input end of the seventh filter is connected to the fourth output end of the second switch.

[0016] According to an embodiment of the present application, the control circuit includes a third single - pole four - throw switch and a fourth single - pole four - throw switch;

[0017] The first input end of the third switch in the third single - pole four - throw switch is connected to the output end of the fourth filter; the second input end of the third switch in the third single - pole four - throw switch is connected to the output end of the fifth filter; the third input end of the third switch in the third single - pole four - throw switch is connected to the output end of the sixth filter; the fourth input end of the third switch in the third single - pole four - throw switch is connected to the output end of the seventh filter;

[0018] The first input end of the fourth switch in the fourth single - pole four - throw switch is connected to the output end of the first filter; the second input end of the fourth switch in the fourth single - pole four - throw switch is connected to the output end of the second filter; the third input end of the fourth switch in the fourth single - pole four - throw switch is connected to the output end of the third filter; the fourth input end of the fourth switch in the fourth single - pole four - throw switch is connected to the output end of the third switch in the third single - pole four - throw switch; the output end of the fourth switch in the fourth single - pole four - throw switch is used to be connected to an antenna port or a receiving path.

[0019] According to an embodiment of the present application, the reference frequencies corresponding to the first filter to the seventh filter decrease in sequence.

[0020] According to an embodiment of the present application, the first filter to the seventh filter are all low - pass filters, or the first filter to the seventh filter are all band - pass filters.

[0021] In a second aspect, the present utility model also proposes a communication device, including the asymmetric filter multiplexer according to any one of the first aspects above.

[0022] Compared with the prior art, the asymmetric filter multiplexer and communication device provided by the present utility model. The asymmetric filter multiplexer includes a switch subset, a segmented filter bank, a second switch subset, and a control circuit. Among them, the high-frequency connection part in the first switch subset is connected to the input end of the segmented filter bank through one switch, and the low-frequency connection part in the first switch subset is connected to the input end of the segmented filter bank through at least two switches. The output end of the segmented filter bank is connected to the second switch subset. The control circuit is connected to both the first switch subset and the second switch subset. The communication device includes the asymmetric filter multiplexer. By setting the asymmetric switch structure in the embodiments of the present utility model, the number of single-ended parallel sub-switch units in the entire switch structure can be reduced, thereby reducing the insertion loss caused by on-resistance and off-capacitance, and greatly improving the insertion loss, isolation degree, and power handling capacity of the switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0024] Figure 1 Schematic block diagram of an asymmetric filter multiplexer provided by an embodiment of the present utility model;

[0025] Figure 2 Another schematic block diagram of an asymmetric filter multiplexer provided by an embodiment of the present utility model;

[0026] Figure 3 Still another schematic block diagram of an asymmetric filter multiplexer provided by an embodiment of the present utility model;

[0027] Figure 4 Schematic circuit structure diagram of an asymmetric filter multiplexer provided by an embodiment of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] The following will clearly and completely describe the technical solutions in the embodiments of the present utility model with reference to the drawings in the embodiments of the present utility model. Obviously, the described embodiments are some, but not all, of the embodiments of the present utility model. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts fall within the scope of protection of the present utility model.

[0029] The directional terms mentioned in the present utility model, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side surface", etc., are only references to the directions in the attached drawings. Therefore, the directional terms used are for explaining and understanding the present utility model, rather than for limiting the present utility model. In addition, in the drawings, structures that are similar or identical are denoted by the same reference numerals.

[0030] It should be understood that when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0031] It should also be understood that the terms used in the specification of the present utility model are merely for the purpose of describing specific embodiments and are not intended to limit the present utility model. As used in the specification of the present utility model and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms.

[0032] It should be further understood that the term "and / or" used in the specification of the present utility model and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0033] Please refer to Figure 1 , which is a schematic block diagram of an asymmetric filter multiplexer provided by an embodiment of the present utility model. As Figure 1 shown, the embodiment of the present utility model provides an asymmetric filter multiplexer, including: a first switch subset 10, a segmented filter bank 20, a second switch subset 30, and a control circuit 40; wherein, the high-frequency connection part 10A in the first switch subset 10 is connected to the input end of the segmented filter bank 20 through a switch, and the low-frequency connection part 10B in the first switch subset 10 is connected to the input end of the segmented filter bank 20 through at least two switches; the output end of the segmented filter bank 20 is connected to the second switch subset 30; the control circuit 40 is connected to both the first switch subset 10 and the second switch subset 20.

[0034] In this embodiment, the first switch subset 10 is divided into a high-frequency connection part 10A and a low-frequency connection part 10B. Since the number of switches connecting the high-frequency connection part 10A to the input end of the segmented filter bank 20 is one, and the low-frequency connection part 10B is connected to the input end of the segmented filter bank 20 through at least two switches, an asymmetric switch structure is formed due to the different numbers of switches in the high-frequency connection part 10A and the low-frequency connection part 10B of the first switch subset 10. By setting the above-mentioned asymmetric switch structure, the number of single-ended parallel sub-switch units in the entire switch structure can be reduced, thereby reducing the insertion loss caused by R_on (i.e., on-resistance) and C_off (i.e., off-capacitance).

[0035] Moreover, an asymmetric first switch subset 10 is provided in the asymmetric filter multiplexer. After the first switch subset 10 is connected to the segmented filter bank 20, it is still a multi-branch circuit structure. Then, a second switch subset 30, which is the corresponding mirror switch subset of the first switch subset 10, can be used for combining paths. After combining paths, the output end of the second switch subset 30 can be connected to other subsequent circuits or components (such as an antenna port or a receiving path, etc.). Among them, the control circuit 40 is used to control the on / off of the switches specifically included in the first switch subset 10 and the second switch subset 30.

[0036] In one embodiment, as the first embodiment of the first switch subset 10, the first switch subset 10 includes two or more switch subsets, and the switch subsets are sequentially denoted as the first-level switch subset to the N-level switch subset in ascending order; where N is the total number of switch subsets including switches in the switch subsets.

[0037] In this embodiment, as the first embodiment of the first switch subset 10, when the number of levels of the switch subsets included in the first switch subset 10 is set to two or more, more switch paths can be formed to meet the actual usage requirements. It should be noted that N is a positive integer greater than 2.

[0038] For example, in specific implementation, the first switch subset 10 can be set to include three switch subsets, which are respectively denoted as the first-level switch subset, the second-level switch subset, and the third-level switch subset; three switches can be set in the first-level switch subset, three switches can be set in the second-level switch subset, and two switches can be set in the third-level switch subset. If the commonly used symmetric switch structure also includes at least two switch subsets, the total number of switches included in each level of switch subset is 2 n (where n is a positive integer). The total number of switches corresponding to each level of switch subset in the first switch subset 10 in the above example does not have the requirement that the total number of switches must be 2 n for this requirement.

[0039] In one embodiment, the first-stage switch in the first switch subset 10 and the input end of the subset are used to be connected to the transmitting path, and the Nth-stage switch and the output end of the subset are sequentially connected to the antenna port through the segmented filter bank 20 and the second switch subset 30, or connected to the receiving path.

[0040] In this embodiment, still referring to the first embodiment of the first switch subset 10, when the switches in the first switch subset 10 are sequentially denoted as the first-stage switch and subset to the Nth-stage switch and subset in ascending order, the first-stage switch and subset to the Nth-stage switch and subset are sequentially connected in ascending order. The input end of the first-stage switch and subset is generally used as the input end of the entire switch subset 10 to be connected to the transmitting path (if the transmitting path is denoted as TX). The output end of the Nth-stage switch and subset is generally used as the output end of the entire switch subset 10 and is sequentially connected to the segmented filter bank 20 and the second switch subset 30. Moreover, the output end of the second switch subset 30 is connected to one of the antenna port (if the antenna port is denoted as ANT) or the receiving path (if the receiving path is denoted as RX). Furthermore, the output end of at least one switch and subset among the first-stage switch and subset to the (N - 1)th-stage switch and subset can be directly connected to the segmented filter bank 20. It can be seen that by setting the asymmetric filter multiplexer with the above structure, the number of single-ended parallel sub-switch units in the entire switch structure is reduced, thereby reducing the insertion loss caused by R_on (i.e., on-resistance) and C_off (i.e., off-capacitance).

[0041] In one embodiment, as the second embodiment of the first switch subset 10, as Figure 2 shown, the first switch subset 10 includes two switches and subsets, and is sequentially denoted as the first-stage switch and subset 11 and the second-stage switch and subset 12 in ascending order.

[0042] In this embodiment, as the second embodiment of the first switch subset 10, when the number of stages of the switches and subsets included in the first switch subset 10 is set to two, a multiplexer path can be formed to meet the actual usage requirements. Similarly, in the first switch subset 10 including two stages of switches and subsets, the total number of switches corresponding to each stage of the switches and subsets does not have the requirement that the total number of switches must be 2 n this requirement.

[0043] In one embodiment, as Figure 2As shown, the first - stage switch and the first end of subset 11 are used to connect to the transmission path TX. The second end of the first - stage switch and subset 11 is connected to the first end of the second - stage switch and subset 12, and the second end of the first - stage switch and subset 11 is also connected to the segmented filter bank 20. The second end of the second - stage switch and subset 12 is connected to the segmented filter bank 20.

[0044] In this embodiment, still referring to the second embodiment of the first switch subset 10, when the first - stage switch and subset to the second - stage switch and subset in the first switch subset 10 are sequentially numbered from low - level to high - level, the first end of the first - stage switch and subset 11 is used as the input end to connect to the transmission path TX. The second end of the first - stage switch and subset 11 is connected to the first end of the second - stage switch and subset 12 and is also connected to the segmented filter bank 20. The second end of the second - stage switch and subset 12 is connected to the segmented filter bank 20. The segmented filter bank 20 is also connected to the second switch subset 30, and the output end of the second switch subset 30 can be connected to one of the antenna port (denoted as ANT for example) or the receiving path (denoted as RX for example) in specific implementation.

[0045] Among them, please refer to Figure 1 and Figure 2 simultaneously. When the first - stage switch and subset 11 is connected to the segmented filter bank 20, this path can be regarded as the high - frequency connection part 10A in the first switch subset 10 being connected to the input end of the segmented filter bank 20. The second end of the first - stage switch and subset 11 is connected to the first end of the second - stage switch and subset 12, and the second end of the second - stage switch and subset 12 is connected to the segmented filter bank 20. This path can be regarded as the low - frequency connection part 10B in the first switch subset 10 being connected to the input end of the segmented filter bank 20. Similarly, for each stage of the switch and subset in the switch subset including two - stage switches and subsets, there is no requirement that the total number of corresponding switches of the switch and subset must be 2 n This reduces the number of single - ended parallel sub - switch units in the entire switch structure, thereby reducing the insertion loss caused by R_on and C_off.

[0046] In one embodiment, as Figure 3 shown, the segmented filter bank 20 includes at least two segmented filter bank subsets, which are respectively denoted as the first segmented filter bank subset 21 and the second segmented filter bank subset 22. Among them, the second end of the first - stage switch and subset 11 is connected to the first segmented filter bank subset 11, and the second end of the second - stage switch and subset 12 is connected to the second segmented filter bank subset 22.

[0047] In this embodiment, when the second end of the first-stage switch and subset 11 is directly connected to the first-stage filter bank subset 11 in addition to being connected to the first end of the second-stage switch and subset 12, the number of single-ended parallel sub-switch units between the second end of the first-stage switch and subset 11 and the first-stage filter bank subset 11 is reduced, and the insertion loss caused by R_on and C_off is reduced.

[0048] Moreover, one switch structure composed of the first-stage switch and subset 11, the second-stage switch and subset 12, and the second-stage filter bank subset 22, and another switch structure composed of the first-stage switch and subset 11 and the first-stage filter bank subset 21 have different total numbers of switches, and together they form an asymmetric switch structure, so that each switch structure has different insertion losses, isolations, linearities, etc.

[0049] In one embodiment, as Figure 1 、 Figure 3 and Figure 4 shown, the first-stage switch and subset 11 include a first single-pole four-throw switch K1; the second-stage switch and subset 12 include a second single-pole four-throw switch K2;

[0050] The first end of the first single-pole four-throw switch K1 is used as the first input terminal of the first switch and is connected to the transmit path TX; one of the second ends of the first single-pole four-throw switch K1 is used as the fourth output terminal of the first switch and is connected to the first end of the second single-pole four-throw switch K2; the first output terminal of the first switch, the second output terminal of the first switch, and the third output terminal of the first switch among the second ends of the first single-pole four-throw switch K1 form the high-frequency connection part 10A and are directly connected to the first-stage filter bank subset 21 in parallel; the second output terminal of the second switch to the fourth output terminal of the second switch among the second ends of the second single-pole four-throw switch K2 form the low-frequency connection part 10B and are connected to the second-stage filter bank subset 22 in parallel.

[0051] In this embodiment, when the first-stage switch and subset 11 is set to include a first single-pole four-throw switch K1, and the second-stage switch and subset 12 is set to include a second single-pole four-throw switch K2, the first-stage switch and subset 11 includes one switch, and the second-stage switch and subset 12 includes one switch. The total number of switches in each stage of switch and subset is not 2 n each, reducing the number of single-ended parallel sub-switch units in the entire switch structure, thereby reducing the insertion loss caused by R_on and C_off.

[0052] In one embodiment, as Figure 1 、 Figure 3 andFigure 4 As shown, the first sub - set of the segmented filter bank 21 includes a first filter Z1, a second filter Z2, and a third filter Z3; the input end of the first filter Z1 is connected to the first output end of the first switch, the input end of the second filter Z2 is connected to the second output end of the first switch, and the input end of the third filter Z3 is connected to the third output end of the first switch;

[0053] The second sub - set of the segmented filter bank 22 includes a fourth filter Z4, a fifth filter Z5, a sixth filter Z6, and a seventh filter Z7; the input end of the fourth filter Z4 is connected to the first output end of the second switch, the input end of the fifth filter Z5 is connected to the second output end of the second switch, the input end of the sixth filter Z6 is connected to the third output end of the second switch, and the input end of the seventh filter Z7 is connected to the fourth output end of the second switch.

[0054] In this embodiment, the first sub - set of the segmented filter bank 21 can be regarded as a high - frequency filter bank and is connected to the high - frequency connection part 10A, and the second sub - set of the segmented filter bank 22 can be regarded as a low - frequency filter bank and is connected to the low - frequency connection part 10B. Specifically, the first filter Z1 to the seventh filter Z7 are all low - pass filters or band - pass filters, and the reference frequencies corresponding to the first filter Z1 to the seventh filter Z7 decrease in sequence. Moreover, in order to improve the segment frequency response insertion loss of each path where the first filter Z1 to the seventh filter Z7 are located, an inductor can also be connected in series at the output end of each of the first filter Z1 to the seventh filter Z7.

[0055] More specifically, the frequency band of the first filter Z1 is 342 - 512 MHz, the frequency band of the second filter Z2 is 228 - 342 MHz, the frequency band of the third filter Z3 is 152 - 228 MHz, the frequency band of the fourth filter Z4 is 01 - 152 MHz, the frequency band of the fifth filter Z5 is 67.5 - 101 MHz, the frequency band of the sixth filter Z6 is 45 - 67.5 MHz, and the frequency band of the seventh filter Z7 is 30 - 45 MHz. The frequency bands of the above seven filters are 30 - 512 MHz and span 17 octaves; and the first filter Z1 to the seventh filter Z7 all adopt low-pass filters (such as 9th-order elliptical low-pass filters), and the low-pass harmonic requirement is -60 dBc. When the above 7 filters are adopted in the asymmetric filter multiplexer of the present application, through test experiments, the insertion loss fluctuation at the transmitting end can be obtained as 0.2 dB and the insertion loss fluctuation at the receiving end can be obtained as 0.06 dB; when a symmetric switch structure is adopted between the transmitting end and the receiving end, through test experiments, the insertion loss fluctuation at the transmitting end can be obtained as 0.42 dB and the insertion loss fluctuation at the receiving end can be obtained as 0.19 dB. From the comparison of the above test data, it can be seen that the fluctuation and insertion loss of the asymmetric filter multiplexer of the present application are much better than those of the symmetric switch.

[0056] In one embodiment, as Figure 1 , Figure 3 and Figure 4 shown, the second switch subset 30 includes a third single-pole four-throw switch K3 and a fourth single-pole four-throw switch K4;

[0057] In the third single-pole four-throw switch K3, the first input terminal of the third switch is connected to the output terminal of the fourth filter Z4; the second input terminal of the third switch in the third single-pole four-throw switch K3 is connected to the output terminal of the fifth filter Z5; the third input terminal of the third switch in the third single-pole four-throw switch K3 is connected to the output terminal of the sixth filter Z6; the fourth input terminal of the third switch in the third single-pole four-throw switch K3 is connected to the output terminal of the seventh filter Z7;

[0058] In the fourth single-pole four-throw switch K4, the first input terminal of the fourth switch is connected to the output terminal of the first filter Z1; the second input terminal of the fourth switch in the fourth single-pole four-throw switch K4 is connected to the output terminal of the second filter Z2; the third input terminal of the fourth switch in the fourth single-pole four-throw switch K4 is connected to the output terminal of the third filter Z3; the fourth input terminal of the fourth switch in the fourth single-pole four-throw switch K4 is connected to the output terminal of the third switch in the third single-pole four-throw switch K3; the output terminal of the fourth switch in the fourth single-pole four-throw switch K4 is used to be connected to the antenna port ANT or to the receiving path RX.

[0059] In this embodiment, after adopting the second switch subset 30 with the above circuit structure (the second switch subset 30 can be regarded as a mirror switch subset of the first switch subset 10, and the number and type of switches included in both are the same), the transmission path TX first passes through the first single-pole four-throw switch K1, and then three of the first single-pole four-throw switch K1 are connected to three low-pass filters, namely the first filter Z1, the second filter Z2, and the third filter Z3. The remaining one path of the first single-pole four-throw switch K1 is then connected to the input of the second single-pole four-throw switch K2, and then the four outputs of the second single-pole four-throw switch K2 are connected to four low-pass filters, namely the fourth filter Z4, the fifth filter Z5, the sixth filter Z6, and the seventh filter Z7. The first filter Z1 to the seventh filter Z7 form a segmented filter bank; after the segmented filter bank is combined into one by the third single-pole four-throw switch K3 and the fourth single-pole four-throw switch K4 in the second switch subset 30, it is then connected to the antenna port ANT or to the receiving path RX.

[0060] Specifically, please refer to Figure 4 , one path of the fourth switch output terminal of the fourth single-pole four-throw switch K4 goes to the antenna port ANT through the single-pole double-throw switch K5, and the other path of the single-pole double-throw switch K5 outputs to the receiving path RX (that is, the fifth switch input terminal of the single-pole double-throw switch K5 is connected to the fourth switch output terminal of the fourth single-pole four-throw switch K4; the first output terminal of the fifth switch of the single-pole double-throw switch K5 is used to connect to the antenna port ANT; the second output terminal of the fifth switch of the single-pole double-throw switch K5 is used to connect to the receiving path RX). More specifically, the first single-pole four-throw switch K1, the second single-pole four-throw switch K2, the third single-pole four-throw switch K3, and the fourth single-pole four-throw switch K4 all adopt single-pole four-throw gallium nitride switches. After adopting the above asymmetric filter multiplexer switch, the core indexes such as the insertion loss, isolation degree, and power handling capacity of the switch can be greatly improved, and the problems of insertion loss and uneven frequency response of the broadband multi-band integrated IC and the radio frequency front end can be solved, which is particularly suitable for the antenna port of multi-band radios (especially as a high-power switch for the filter band selection path of the antenna port).

[0061] Moreover, compared with the symmetric switch obtained by combining the asymmetric filter multiplexer switch of the present application with the existing PIN diodes, the volume is reduced and the power consumption is lowered, and the problems existing in the indexes such as power handling capacity, frequency response of insertion loss, and isolation of the symmetric switch can also be solved.

[0062] In the above embodiments of the present application, the asymmetric filter multiplexer switch can also be used as a switch circuit unit, and multiple switch circuit units are arranged in parallel in a complete switch circuit structure to form more paths, and can better meet the insertion loss, power, isolation, linearity, flatness of frequency response, and any shape of the frequency response curve.

[0063] Another embodiment of the present application provides a communication device, which includes the above-mentioned asymmetric filter multiplexer. Specifically, the communication device in this embodiment may be a multi-band radio or the like, and is not limited within the understanding of those skilled in the art.

[0064] In summary, the present utility model provides an asymmetric filter multiplexer and a communication device. The asymmetric filter multiplexer includes a switch subset, a segmented filter bank, a second switch subset, and a control circuit. Among them, the high-frequency connection part in the first switch subset is connected to the input end of the segmented filter bank through a switch, and the low-frequency connection part in the first switch subset is connected to the input end of the segmented filter bank through at least two switches. The output end of the segmented filter bank is connected to the second switch subset. The control circuit is connected to both the first switch subset and the second switch subset. The communication device includes the asymmetric filter multiplexer. By setting the asymmetric switch structure in the embodiment of the present utility model, the number of single-ended parallel sub-switch units in the entire switch structure can be reduced, thereby reducing the insertion loss caused by the on-resistance and off-capacitance, and greatly improving the insertion loss, isolation degree, and power handling capacity of the switch.

[0065] The above is only the specific embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or substitutions within the technical scope disclosed by the present utility model, and these modifications or substitutions should be covered within the protection scope of the present utility model. Therefore, the protection scope of the present utility model shall be subject to the protection scope of the claims.

Claims

1. An asymmetric filter multi-way switch, characterized in that: comprising a first switch subset, a segmented filter bank, a second switch subset and a control circuit; Among them, the high-frequency connection part in the first switch subset is connected to the input end of the segmented filter group through a switch, and the low-frequency connection part in the first switch subset is connected to the input end of the segmented filter group through at least two switches; the output end of the segmented filter group is connected to the second switch subset; and the control circuit is connected to both the first switch subset and the second switch subset.

2. The asymmetric filter multi-way switch according to claim 1, characterized in that: The first switch subset includes more than two switches and subsets, and the switch subsets are recorded in order from low level to high level as first-level switches and subsets to Nth-level switches and subsets; wherein N is the total number of switches and subsets included in the switch subset.

3. The asymmetric filter multi-way switch according to claim 2, characterized in that: The input end of the first switch and subset in the first switch subset is used to connect to the transmission path, and the output end of the Nth switch and subset is connected to the antenna port or the receiving path through the segmented filter group and the second switch subset in sequence.

4. The asymmetric filter multi-way switch according to claim 1, characterized in that: The first switch subset includes two switches and subsets, which are sequentially recorded as first-level switches and subsets and second-level switches and subsets in order from low level to high level.

5. The asymmetric filter multi-way switch according to claim 4, characterized in that: The first end of the first-stage switch and subset is used to connect to the transmission path, the second end of the first-stage switch and subset is connected to the first end of the second-stage switch and subset, and the second end of the first-stage switch and subset is also connected to the segmented filter group; the second end of the second-stage switch and subset is connected to the segmented filter group.

6. The asymmetric filter multi-way switch according to claim 5, characterized in that: The segmented filter group includes at least two segmented filter group subsets, which are respectively recorded as a first segmented filter group subset and a second segmented filter group subset; wherein the second end of the first-stage switch and the subset is connected to the first segmented filter group subset, and the second end of the second-stage switch and the subset is connected to the second segmented filter group subset.

7. The asymmetric filter multi-way switch according to claim 6, characterized in that: The first stage switch and subset include a first single-pole four-throw switch; the second stage switch and subset include a second single-pole four-throw switch; The first end of the first single-pole four-throw switch is connected to the transmitting path as the first input end of the first switch; one of the output ends of the second end of the first single-pole four-throw switch is connected to the first end of the second single-pole four-throw switch as the fourth output end of the first switch; the first output end of the first switch, the second output end of the first switch and the third output end of the first switch in the second end of the first single-pole four-throw switch constitute the high-frequency connection part, and are respectively connected to the first segmented filter group subset in parallel; the second end of the second single-pole four-throw switch from the first output end of the second switch to the fourth output end of the second switch constitute the low-frequency connection part, and are respectively connected to the second segmented filter group subset in parallel.

8. The asymmetric filter multi-way switch according to claim 7, characterized in that: The first segmented filter bank subset includes a first filter, a second filter and a third filter; an input end of the first filter is connected to a first output end of the first switch, an input end of the second filter is connected to a second output end of the first switch, and an input end of the third filter is connected to a third output end of the first switch; The second segmented filter group subset includes a fourth filter, a fifth filter, a sixth filter and a seventh filter; the input end of the fourth filter is connected to the first output end of the second switch, the input end of the fifth filter is connected to the second output end of the second switch, the input end of the sixth filter is connected to the third output end of the second switch, and the input end of the seventh filter is connected to the fourth output end of the second switch.

9. The asymmetric filter multi-way switch according to claim 8, characterized in that: The second switch subset includes a third single-pole four-throw switch and a fourth single-pole four-throw switch; The first input end of the third switch in the third single-pole four-throw switch is connected to the output end of the fourth filter; the second input end of the third switch in the third single-pole four-throw switch is connected to the output end of the fifth filter; the third input end of the third switch in the third single-pole four-throw switch is connected to the output end of the sixth filter; the fourth input end of the third switch in the third single-pole four-throw switch is connected to the output end of the seventh filter; The first input end of the fourth switch in the fourth single-pole four-throw switch is connected to the output end of the first filter; the second input end of the fourth switch in the fourth single-pole four-throw switch is connected to the output end of the second filter; the third input end of the fourth switch in the fourth single-pole four-throw switch is connected to the output end of the third filter; the fourth input end of the fourth switch in the fourth single-pole four-throw switch is connected to the output end of the third switch in the third single-pole four-throw switch; the output end of the fourth switch in the fourth single-pole four-throw switch is used to be connected to the antenna port or to the receiving path.

10. A communication device, characterized in that: The invention comprises at least one asymmetric filter multi-way switch as claimed in any one of claims 1 to 9.

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