Semiconductor structure

Abstract

A semiconductor structure includes a substrate, a trench in the substrate, an alignment mark in the trench, and a gate pattern on the alignment mark, the gate pattern including a metal portion, where a top surface of the metal layer is lower than a top surface of the trench.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and provides a semiconductor structure. More specifically, it provides a semiconductor structure with alignment marks. Background Art

[0002] In the manufacturing process of modern integrated circuits, different mask patterns need to be overlapped on the wafer. Depending on the process, there may be more than dozens of mask overlapping steps. The lithography process is the process of forming masks in semiconductor production. To ensure that subsequent semiconductor patterns are formed at the correct relative positions with respect to the previous layer patterns, the mask pattern of each layer needs to be accurately overlapped with the previous layer, which is called overlay, representing the quality index of the overlapping of the previous lithography process layer and the current lithography process layer.

[0003] Existing overlay inspection methods mainly judge the quality of the overlap between the two previous and subsequent lithography levels by testing specific overlay marks (or called alignment marks) through an overlay test device. The overlay marks used for measurement by the overlay test device are generally composed of rectangular or square patterns. An overlay pattern is designed in each of the two lithography levels, and the smaller overlay pattern is designed to be exactly nested in the larger overlay pattern. By measuring the distance between the corresponding sides of the two patterns and performing calculations, the overlay-related values can be obtained. Summary of the Utility Model

[0004] This application proposes a semiconductor structure with alignment marks, and the formed alignment marks have special gate patterns.

[0005] One aspect of this application proposes a semiconductor structure, comprising: a substrate; a trench located in the substrate; an alignment mark located in the trench; and a gate pattern located on the alignment mark, the gate pattern comprising a metal part, wherein the top surface of the metal part is lower than the top surface of the trench.

[0006] In some embodiments, the trench comprises a first trench and a second trench, and the top surface of the alignment mark in the first trench is higher than the top surface of the alignment mark in the second trench.

[0007] In some embodiments, the gate pattern includes a first gate pattern located on the first trench and a second gate pattern located on the second trench.

[0008] In some embodiments, the first gate pattern on the first trench comprises a first part and a second part, and the first part and the second part are respectively located at both ends of the alignment mark and are respectively at a first distance and a second distance from the side walls of the first trench.

[0009] In some embodiments, the first part and the second part respectively have a first width and a second width, the second gate pattern has a third width, and both the first width and the second width are smaller than the third width.

[0010] In some embodiments, the second gate pattern on the second trench is located in the middle of the alignment mark and is at a third distance from the sidewall of the second trench.

[0011] In some embodiments, the third distance is smaller than the first distance and the second distance.

[0012] In some embodiments, the gate pattern further includes a semiconductor part and a hard mask part, and the semiconductor part, the metal part, and the hard mask part are sequentially stacked on the alignment mark.

[0013] In some embodiments, the top surface of the hard mask part is higher than the top surface of the trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The specification drawings forming a part of the present application are used to provide a further understanding of the present application. The schematic embodiments and descriptions thereof of the present application are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0015] Figures 1 to 4 is a cross-sectional schematic view of a process flow of a semiconductor structure with alignment marks according to an embodiment of the present application;

[0016] Figure 5 is a top view schematic view of a semiconductor structure with alignment marks according to an embodiment of the present application; and

[0017] Figure 6 is a cross-sectional schematic view of a semiconductor structure with alignment marks according to another embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0019] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0020] It should be noted that the terms "first", "second", etc. in the description, claims and above-mentioned drawings of this application are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so as to implement the embodiments of the present application described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0021] In this article, each figure is divided into left and right halves, which respectively represent the structural patterns on different alignment marks on the same substrate. The evolution process of these different structural patterns will be demonstrated in the embodiments, so that those skilled in the art can clearly understand this application.

[0022] First, please refer to Figure 1 . The semiconductor structure of this application is fabricated on a semiconductor substrate 100, such as a silicon substrate, a germanium substrate, and / or a silicon germanium substrate, etc. In an embodiment, trenches 102a, 102b are formed on the substrate 100, which are filled with an isolation material, thus forming alignment marks (or called registration marks) 104a, 104b in the semiconductor structure of this application. The alignment marks 104a, 104b can be formed by first forming a dielectric layer that fills the trenches 102a, 102b on the substrate 100, and then using an etch-back process to etch the dielectric layer. The material of the dielectric layer can be silicon oxide, silicon nitride, or a multi-layer structure thereof.

[0023] The alignment marks 104a, 104b of this application can be located in the scribe line of the wafer, which is used to test the overlap quality of the mask pattern and the previous layer pattern in the registration step. The alignment marks 104a, 104b can also be formed in the same process as the structures in other regions. For example, the alignment marks 104a, 104b can be formed together with the shallow trench isolation structure (STI) in the storage cell area and / or the peripheral area. Specifically, the trenches can be formed through the same lithography process, and the isolation material can be filled in the trenches to form the alignment marks 104a, 104b on the scribe line and the shallow trench isolation structure on the storage cell area respectively. It should be noted that in the embodiments of this application, the alignment marks 104a, 104b in the left and right trenches 102a, 102b can have different heights, which may be due to the different widths of the trenches 102a, 102b. Thus, on the basis of the same trench depth, the alignment marks 104a, 104b formed in the same deposition process will have different heights. Take Figure 1For example, if the width of trench 102a is designed to be smaller than that of trench 102b, the height H1 of alignment mark 104a formed therein will be higher than the height H2 of alignment mark 104b. In this application, the width of the trench and the height of the alignment mark are also the reasons for the differences in the semiconductor structures formed thereon subsequently.

[0024] Still referring to Figure 1 . After alignment marks 104a and 104b are formed, gate material layers such as semiconductor layer 106, metal layer 108, and hard mask layer 110 are sequentially and conformally formed on substrate 100 and alignment marks 104a and 104b. Similar to alignment marks 104a and 104b, in the embodiments of this application, the above layer structures can be formed in the same process as those in other regions. For example, semiconductor layer 106, metal layer 108, and hard mask layer 110 can be simultaneously formed above the scribe line region, the memory cell region, and / or the peripheral region, and are formed through the same deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. The material of semiconductor layer 106 can be doped polysilicon, the material of metal layer 108 can be metal nitride, such as titanium nitride, tantalum nitride, and / or tungsten nitride, etc., or low-resistance metal, such as tungsten, aluminum, titanium, or tantalum, etc., or a composite layer combination of both. The material of hard mask layer 110 can be silicon nitride or silicon oxynitride. The semiconductor layer 106, metal layer 108, and hard mask layer 110 formed on the memory cell region and the peripheral region can be used as the material layers of the bitline and the gate structure of the peripheral circuit, respectively.

[0025] Please refer to Figure 2 . After alignment marks 104a and 104b and layer structures such as semiconductor layer 106, metal layer 108, and hard mask layer 110 are formed, a photolithography material layer is then formed on hard mask layer 110. The photolithography material layer can include a silicon-containing anti-reflection layer (SiARC) 112 and a bottom anti-reflection layer (BARC) 114, etc., but is not limited thereto. It should be noted that in the embodiments of this application, due to the differences in the width of the aforementioned trench and the height of the alignment mark, the thicknesses of the bottom anti-reflection layer 114 and the silicon-containing anti-reflection layer 112 formed on alignment marks 104a and 104b in the direction perpendicular to the substrate will also be different. Generally speaking, the thickness of the bottom anti-reflection layer 114 formed on alignment mark 104b will be greater than the thickness of the bottom anti-reflection layer 114 formed on alignment mark 104a, and the thickness of the reflection layer part closer to the trench wall will be thicker. In the embodiments of this application, this difference in thickness will result in differences in the photolithography patterns formed after the subsequent photolithography process.

[0026] Please refer to Figure 3After the bottom anti-reflection layer 114 and the silicon-containing anti-reflection layer 112 are formed, next, a photolithography process is used to pattern the bottom anti-reflection layer 114 and the silicon-containing anti-reflection layer 112 to form a desired mask pattern. In the embodiment of the present application, the photolithography process may specifically include forming a photoresist on the bottom anti-reflection layer 114, exposing layer structures such as the photoresist, the bottom anti-reflection layer 114, and the silicon-containing anti-reflection layer 112, and developing to remove unnecessary parts in these layer structures to form a photoresist pattern. In the embodiment of the present application, the formed photolithography pattern may be a bit line pattern on the storage unit area and / or a gate pattern on the peripheral area, which can be used as an etching mask in subsequent etching processes to pattern layer structures such as the underlying semiconductor layer 106, metal layer 108, and hard mask layer 110 into storage node contacts and / or gates and other structures.

[0027] It should be noted that in the embodiment of the present application, layer structures such as the semiconductor layer 106, metal layer 108, and hard mask layer 110 on the scribed area (i.e., the alignment mark area in the icon) are intended to be removed, so after the above photolithography process, there should be no residue of photolithography materials such as the bottom anti-reflection layer 114 and the silicon-containing anti-reflection layer 112 on the alignment marks 104a, 104b. However, due to the fact that the thickness of the silicon-containing anti-reflection layer 112 formed on the alignment marks 104a, 104b is relatively thicker than that in other areas, part of it is likely to remain on the alignment marks 104a, 104b due to incomplete exposure after the aforementioned exposure step. As Figure 3 shown, for the alignment mark 104a, the bottom anti-reflection layer 114 and the silicon-containing anti-reflection layer 112 thereon will remain at positions close to the trench walls, thus forming photolithography material patterns 10a, 10b that are respectively at a first distance D1 and a second distance D2 from the two side trench walls. For the alignment mark 104b, since the overall thickness of the silicon-containing anti-reflection layer 112 thereon is relatively thicker, it will not only remain at positions close to the trench walls but also in the middle part, thus forming a photolithography material pattern 20 that almost covers the entire alignment mark 104b. The photolithography material pattern 20 has a third distance D3 and a fourth distance D4 from the two side trench walls respectively. In addition, since the exposure effect on the bottom anti-reflection layer 114 and the silicon-containing anti-reflection layer 112 near the trench walls is stronger, they are more easily removed in the developing step. Therefore, despite the relatively thick thickness, the remaining parts of the bottom anti-reflection layer 114 and the silicon-containing anti-reflection layer 112 are at a certain distance from the adjacent trench walls and do not contact the trench walls. The above uncompletely removed photolithography pattern will cause part of the layer structures such as the semiconductor layer 106, metal layer 108, and hard mask layer 110 on the subsequent alignment marks to remain.

[0028] Please refer to Figure 4 After the photolithography process, then, with the formed photolithography material pattern (including such asFigure 3 Etching processes are performed on 10a, 10b, and 20) shown as etching masks to pattern layer structures such as the underlying hard mask layer 110, metal layer 108, and semiconductor layer 106, thereby forming bit lines on the storage cell region and / or gates on the peripheral region (such as Figure 6 gate 33 in). Among them, the remaining metal layer after patterning forms a metal part, the remaining hard mask layer after patterning forms a hard mask part, and the remaining semiconductor layer after patterning forms a semiconductor part. In the embodiments of the present application, since there are photolithography material patterns 10a, 10b, 20 as shown Figure 3 remaining on the alignment marks 104a, 104b, corresponding gate patterns will be formed on the alignment marks 104a, 104b. As shown Figure 4 in, a first gate pattern including a first part 11a and a second part 11b is formed on the alignment mark 104a. A whole second gate pattern 22 is formed on the alignment mark 104b. Both the above-mentioned first gate pattern and the above-mentioned second gate pattern include the above-mentioned metal part. It should be noted that like the photolithography material patterns 10a, 10b, 20 shown Figure 3 in, the first part 11a and the second part 11b of the first gate pattern are respectively close to the trench walls on both sides, and have a first distance D1 and a second distance D2 from the adjacent trench walls respectively. The second gate pattern 22 almost covers the entire alignment mark 104b, and has a third distance D3 and a fourth distance D4 from the adjacent trench walls on both sides respectively. Furthermore, the first part 11a and the second part 11b of the first gate pattern have a first width W1 and a second width W2 respectively, and the second gate pattern 22 has a third width W3. Both the first width W1 and the second width W2 are smaller than the third width W3.

[0029] Please refer to Figure 5 which is a top view schematic diagram of the semiconductor structure with alignment marks in the foregoing Figure 4 . As shown in the figure, the rectangular dark parts in the figure are the alignment marks 104a, 104b in the present application. For Figure 5 the lower half, the first part 11a and the second part 11b of the first gate pattern are located on the alignment mark 104a near the two ends of the long axis. For Figure 5 the upper half, the alignment mark 104b is almost completely covered by the second gate pattern 22, and only the parts near the periphery are not covered. And as can be seen from the right figure, due to the stronger exposure effect closer to the middle part, the width of the finally formed second gate pattern 22 will gradually become smaller from the two ends of the long axis to the middle part.

[0030] Please refer to Figure 6 . In the embodiments of the present application, formed on Figure 1The first gate pattern (including the first part 11a and the second part 11b) in the trenches 102a, 102b and the metal layer 108 in the second gate pattern 22 will be lower than the top surface of the trenches 102a, 102b. In some embodiments with a relatively thick hard mask layer 110, the top surface of the hard mask layer 110 in the first gate pattern (including the first part 11a and the second part 11b) and the second gate pattern 22 will be higher than the top surface of the trenches 102a, 102b. The metal layer 108 of the first part 11a and the second part 11b of the first gate pattern is higher than the metal layer 108 of the second gate pattern 22. Since the gate 33 located in the peripheral region is formed on the substrate 100 rather than in a trench, its layer structure will be higher than the layer structures of the gate patterns 11a, 11b.

[0031] The above are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor structure, characterized in that: Include: substrate; a groove located in the substrate; an alignment mark located in the groove; as well as A gate pattern, located on the alignment mark, the gate pattern comprising a metal portion; Wherein, a top surface of the metal portion is lower than a top surface of the groove.

2. The semiconductor structure according to claim 1, wherein: The trench includes a first trench and a second trench, and a top surface of the alignment mark in the first trench is higher than a top surface of the alignment mark in the second trench.

3. The semiconductor structure according to claim 2, wherein: The gate pattern includes a first gate pattern located on the first trench and a second gate pattern located on the second trench.

4. The semiconductor structure according to claim 3, characterized in that The first gate pattern on the first trench includes a first portion and a second portion. The first portion and the second portion are respectively located at two ends of the alignment mark and are respectively spaced apart from the sidewall of the first trench by a first distance and a second distance.

5. The semiconductor structure according to claim 4, characterized in that The first portion and the second portion have a first width and a second width, respectively. The second gate pattern has a third width. Both the first width and the second width are smaller than the third width.

6. The semiconductor structure according to claim 4, wherein: The second gate pattern on the second trench is located in the middle of the alignment mark and is spaced a third distance from a sidewall of the second trench.

7. The semiconductor structure according to claim 6, wherein: The third distance is smaller than the first distance and the second distance.

8. The semiconductor structure according to claim 1, wherein: The gate pattern further includes a semiconductor portion and a hard mask portion, and the semiconductor portion, the metal portion and the hard mask portion are sequentially stacked on the alignment mark.

9. The semiconductor structure according to claim 8, characterized in that A top surface of the hard mask portion is higher than a top surface of the trench.

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