Display panel

Abstract

There is provided a display panel including: a base layer in which an emission region and a peripheral region adjacent to the emission region are defined; an insulating layer disposed on the base layer and in which a groove overlapping the emission region is defined; a pixel defining film disposed on the insulating layer and in which an emission opening portion overlapping the groove is defined; a partition wall disposed on the pixel defining film and in which a partition wall opening portion overlapping the emission opening portion is defined; and a light emitting element disposed in the partition wall opening portion, the light emitting element including an anode, an intermediate layer, and a cathode in contact with the partition wall. The insulating layer includes an inner side surface defining a slot and inclined at a first angle relative to a top surface of the base layer.

Description

[0001] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2023-0097545, filed on July 26, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure herein relates to a display panel and a method of manufacturing the same, and more particularly, to a display panel having improved reliability and a method of manufacturing the same. Background Art

[0003] A display device that provides an image to a user, such as, for example, a television, a monitor, a smart phone, and a tablet computer, may include a display panel that displays an image. A variety of display panels (such as, for example, a liquid crystal display panel, an organic light emitting display panel, an electro-wetting display panel, and an electrophoretic display panel) have been developed as display panels.

[0004] The organic light emitting display panel may include an anode, a cathode, and an emission pattern. In some cases, the emission pattern may be separated for each emission region, and the cathode may supply a common voltage to each emission region. Summary of the Utility Model

[0005] The present disclosure provides a display panel and a method for manufacturing a display panel, the display panel providing a light emitting element without using a metal mask and having improved process reliability.

[0006] An embodiment supported by aspects of the present disclosure provides a display panel including: a base layer in which an emission region and an outer peripheral region adjacent to the emission region are defined; an insulating layer disposed on the base layer, and a groove overlapping with the emission region is defined in the insulating layer; a pixel defining film disposed on the insulating layer, and an emission opening portion overlapping with the groove is defined in the pixel defining film; a partition wall disposed on the pixel defining film, and a partition wall opening portion overlapping with the emission opening portion is defined in the partition wall; and a light emitting element disposed in the partition wall opening portion, the light emitting element including an anode, an intermediate layer, and a cathode in contact with the partition wall. The insulating layer includes an inner surface that defines the groove and is inclined at a first angle with respect to the top surface of the base layer, and at least a part of the partition wall has a shape extending along the inner surface.

[0007] In one embodiment, the partition wall may include an end portion extending along the inner surface and protruding toward the center of the anode.

[0008] In one embodiment, the end portion may include a first end portion extending along the inner surface and inclined at a second angle with respect to the top surface of the base layer, and a second end portion extending from the first end portion in a direction parallel to the top surface of the base layer.

[0009] In one embodiment, the second angle may be substantially equal to the first angle.

[0010] In one embodiment, the isolation wall may include a first isolation wall layer disposed on the pixel defining film and in contact with the cathode, and a second isolation wall layer disposed on the first isolation wall layer and including an end portion protruding from the inner surface of the first isolation wall layer.

[0011] In one embodiment, the second isolation wall layer may include a first portion overlapping with the outer peripheral region and having a flat top surface, a second portion extending from the first portion along the inner surface of the insulating layer, and a third portion extending from the second portion in a direction parallel to the top surface of the base layer, and sub-portions of the second portion and sub-portions of the third portion may define the end portion.

[0012] In one embodiment, the first isolation wall layer may include a first isolation wall portion disposed between the first portion and the pixel defining film, and a second isolation wall portion disposed between the second portion and the inner surface of the insulating layer.

[0013] In one embodiment, the length of the end portion may be about 0.6 μm to about 1.5 μm.

[0014] In one embodiment, at least a portion of the pixel defining film may have a shape extending along the inner surface.

[0015] In one embodiment, the display panel may further include a sacrificial pattern disposed in the groove and between the anode and the pixel defining film, and a sacrificial opening portion overlapping with the emission opening portion is defined in the sacrificial pattern.

[0016] In one embodiment, the insulating layer may further include a top surface, the top surface including a first surface overlapping with the outer peripheral region and a second surface having a height difference from the first surface and defining the groove together with the inner surface.

[0017] In one embodiment, the display panel may further include a packaging layer disposed on the light emitting element and including a plurality of thin films, and the packaging layer may include an inorganic packaging pattern covering the light emitting element and including a portion in contact with the isolation wall.

[0018] In one embodiment, the display panel may further include a first dummy pattern disposed on the partition wall and including the same material as the emission pattern included in the intermediate layer, wherein the second dummy pattern is spaced apart from the emission pattern. The display panel may further include a second dummy pattern disposed on the first dummy pattern and including the same material as the cathode, wherein the second dummy pattern is spaced apart from the cathode.

[0019] In one embodiment supported by aspects of the present disclosure, a display panel includes: a base layer in which an emission region and a peripheral region adjacent to the emission region are defined; an anode disposed on the base layer; a pixel defining film exposing at least a portion of the anode, and an emission opening portion overlapping with the emission region is defined in the pixel defining film; a partition wall disposed on the pixel defining film, and a partition wall opening portion overlapping with the emission opening portion is defined in the partition wall; an emission pattern disposed in the partition wall opening portion; and a cathode disposed in the partition wall opening portion and in contact with the partition wall. The partition wall includes a terminal portion protruding toward the center of the anode, and the terminal portion includes a first terminal portion inclined at a predetermined angle with respect to the top surface of the base layer and a second terminal portion extending in a direction parallel to the top surface of the base layer from the first terminal portion.

[0020] In one embodiment supported by aspects of the present disclosure, a method for manufacturing a display panel is described, the method including: preparing a base layer in which an emission region and a peripheral region adjacent to the emission region are defined; forming an insulating layer on the base layer, and a groove overlapping with the emission region is defined in the insulating layer; forming an anode in the groove defined in the insulating layer. The method includes forming a pixel defining film on the insulating layer, and an emission opening portion overlapping with the anode is defined in the pixel defining film. The method includes forming a partition wall on the pixel defining film, and a partition wall opening portion overlapping with the emission opening portion is defined in the partition wall. The method includes forming an emission pattern including at least a portion disposed in the emission opening portion, and forming a cathode including at least a portion disposed in the partition wall opening portion, wherein the cathode is in contact with an inner surface of the partition wall defining the partition wall opening portion. The insulating layer includes an inner surface defining the groove and inclined at a first angle with respect to the top surface of the base layer, and at least a portion of the partition wall has a shape extending along the inner surface of the insulating layer.

[0021] In one embodiment, the forming of the anode may include forming a conductive layer on the insulating layer and patterning the conductive layer to form an anode overlapping with the groove.

[0022] In one embodiment, the method may further include forming a preliminary sacrificial pattern on the anode before forming the pixel defining film, and the forming of the anode and the forming of the preliminary sacrificial pattern may be performed by the same process.

[0023] In one embodiment, the forming of the anode and the preliminary sacrificial pattern may include forming a conductive layer on the insulating layer, forming a sacrificial layer on the conductive layer, and patterning the conductive layer and the sacrificial layer to form the anode and the preliminary sacrificial pattern, wherein the anode and the preliminary sacrificial pattern overlap with the trench.

[0024] In one embodiment, the method may further include forming the sacrificial pattern, and a sacrificial opening portion overlapping with the isolation wall opening portion is defined in the sacrificial pattern, wherein the forming of the sacrificial pattern includes etching the preliminary sacrificial pattern and is after the forming of the isolation wall.

[0025] In one embodiment, in the forming of the isolation wall, a part of the preliminary sacrificial pattern may be removed to form the sacrificial pattern, and a sacrificial opening portion corresponding to the emission opening portion is defined in the sacrificial pattern.

[0026] In one embodiment, the forming of the insulating layer may include forming a preliminary insulating layer on the base layer, exposing the preliminary insulating layer to light by using a mask, defining a transmission region corresponding to the emission region and a semi-transmission region corresponding to the outer peripheral region in the mask, and developing the preliminary insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the aspects of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the aspects of the present disclosure and, together with the description, are used to explain the principles of the aspects of the present disclosure. In the drawings:

[0028] Figure 1A is a perspective view of a display device according to an embodiment in support of the aspects of the present disclosure;

[0029] Figure 1B is an exploded perspective view of a display device according to an embodiment in support of the aspects of the present disclosure;

[0030] Figure 2 is a cross-sectional view of a display panel according to an embodiment in support of the aspects of the present disclosure;

[0031] Figure 3 is a plan view of a display panel according to an embodiment in support of the aspects of the present disclosure;

[0032] Figure 4 An enlarged plan view of a part of a display area of a display panel according to an embodiment supported by aspects of the present disclosure;

[0033] Figure 5A A cross-sectional view taken along line I-I' in Figure 4 of a display panel according to an embodiment supported by aspects of the present disclosure;

[0034] Figure 5B A cross-sectional view illustrating some components of a display panel according to an embodiment supported by aspects of the present disclosure;

[0035] Figure 5C For Figure 5B an enlarged cross-sectional view of region AA' of a display panel according to an embodiment supported by aspects of the present disclosure in

[0036] Figure 5D A cross-sectional view taken along line II-II' in Figure 4 of a display panel according to an embodiment supported by aspects of the present disclosure;

[0037] Figure 6A A cross-sectional view taken along line I-I' in Figure 4 of a display panel according to an embodiment supported by aspects of the present disclosure;

[0038] Figure 6B A cross-sectional view taken along line II-II' in Figure 4 of a display panel according to an embodiment supported by aspects of the present disclosure;

[0039] Figures 7A to 7Q A cross-sectional view illustrating some operations of a method for manufacturing a display panel according to an embodiment supported by aspects of the present disclosure; and

[0040] Figures 8A to 8D A cross-sectional view illustrating some operations of a method for manufacturing a display panel according to an embodiment supported by aspects of the present disclosure. Detailed Description

[0041] In the present disclosure, it will be understood that when an element (or region, layer, section, etc.) is referred to as being "on" another element, "connected to" or "coupled to" another element, the element can be directly disposed on, connected to, or coupled to the other element, or a third intervening element can be disposed between these elements.

[0042] Like reference numerals or symbols refer to like elements throughout. Additionally, in the drawings, the thickness, proportions, and dimensions of elements are exaggerated for effective description of the technical content. The term "and / or" includes one or more combinations that may be defined by the relevant elements.

[0043] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are examples for distinguishing one element from another. For example, a first element may be termed a second element without departing from the teachings supported by aspects of the present disclosure, and similarly, a second element may be termed a first element. As used herein, the singular forms also include the plural forms unless the context clearly indicates otherwise.

[0044] Additionally, terms such as, for example, "below", "beneath", "above", and "on" are used to explain the relationships of the various elements shown in the drawings. The terms are relative concepts and are interpreted based on the directions shown in the drawings.

[0045] It will be further understood that terms such as, for example, "comprising" and "having", when used herein, indicate the presence of the recited features, numbers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof.

[0046] As used herein, the term "directly disposed" may mean that there is no additional layer, film, region, plate, etc. between a component such as, for example, a layer, film, region, or plate and another component. For example, "directly disposed" may mean that two layers or two members are disposed without an additional member such as, for example, an adhesive member.

[0047] As used herein, the term "about" or "approximately" includes the recited value and includes an appropriate range of deviation from the particular value determined by one of ordinary skill in the art in view of the measurements discussed and the errors associated with the measurement of a particular quantity. The term "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the recited value.

[0048] As used herein, the term "substantially" may mean to a great or significant extent in most cases or in essence. As used herein, the term "substantially equal" means approximately or actually equal (e.g., within an equal threshold percentage). As used herein, the term "substantially the same" means approximately or actually the same (e.g., within a threshold difference).

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0050] In the following, embodiments supported by aspects of the present disclosure will be described with reference to the accompanying drawings.

[0051] Figure 1A FIG. is a perspective view of a display device according to an embodiment supported by aspects of the present disclosure. Figure 1B FIG. is an exploded perspective view of a display device according to an embodiment supported by aspects of the present disclosure. Figure 2 FIG. is a cross-sectional view of a display panel according to an embodiment supported by aspects of the present disclosure.

[0052] In one embodiment, the display device DD may be a large display device, such as, for example, a television, a monitor, or an outdoor billboard. The display device DD may also be a small or medium-sized display device, such as, for example, a personal computer, a notebook computer, a personal digital assistant, a vehicle navigation unit, a game console, a smart phone, a tablet computer, and a camera. The foregoing devices are provided as examples, and the display device DD may also be employed as another display device without departing from the scope of the present disclosure. In an exemplary embodiment, a smart phone is illustrated as an example of the display device DD.

[0053] Referring to Figure 1A 、 Figure 1B and Figure 2 , the display device DD may display an image IM in a third direction DR3 on a display surface FS parallel to each of a first direction DR1 and a second direction DR2. The image IM may include a moving image and, in some cases, a still image. Figure 1A A clock window and an icon are illustrated as examples of the image IM. The display surface FS on which the image IM is displayed may correspond to the front surface of the display device DD.

[0054] In an exemplary embodiment, the front surface (or top surface) and the rear surface (or bottom surface) of each component are defined based on the direction of the displayed image IM. The front surface and the rear surface may be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. In some aspects, the directions indicated by the first to third directions DR1, DR2, and DR3 are relative concepts and may be changed to other directions. The phrase "in a plane" used herein may mean a state when viewed in the third direction DR3 (e.g., according to a plan view).

[0055] As Figure 1B illustrated, a display device DD according to one or more embodiments may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be coupled to each other to form an appearance of the display device DD.

[0056] The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. A front surface of the window WP may define a display surface FS of the display device DD. The display surface FS may include a transmissive area TA and a bezel area BZA. The transmissive area TA may be an optically transparent area. For example, the transmissive area TA may be an area having a visible light transmittance of about 90% or higher.

[0057] The bezel area BZA may be an area having a relatively low transmittance compared to the transmissive area TA. The bezel area BZA may define a shape of the transmissive area TA. The bezel area BZA may be adjacent to and surround the transmissive area TA. However, embodiments of the present disclosure are not limited to Figure 1B the illustrated examples, and according to an embodiment supported by aspects of the present disclosure, the bezel area BZA may be omitted in the window WP. The window WP may include at least one functional layer of an anti-fingerprint layer, a hard coat, and an anti-reflection layer, and is not limited to any one embodiment.

[0058] The display module DM may be disposed under the window WP. The display module DM may be a component that substantially generates an image IM. The image IM generated by the display module DM may be displayed on a display surface IS of the display module DM and be visible to an outside user through the transmissive area TA.

[0059] The display module DM may include a display area DA and a non-display area NDA. The display area DA may be an area activated in response to an electrical signal. The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA may be an area covered by the bezel area BZA and not visible from the outside.

[0060] As Figure 2 illustrated, a display module DM according to one or more embodiments may include a display panel DP and an input sensor INS. Although not separately illustrated, a display device DD according to an embodiment supported by aspects of the present disclosure may further include a protection member disposed on a bottom surface of the display panel DP. Additionally or alternatively, the display device DD may further include an anti-reflection member and / or a window member disposed on a top surface of the input sensor INS.

[0061] The display panel DP can be a light-emitting display panel, but is not particularly limited thereto. For example, the display panel DP can be an organic light-emitting display panel or an inorganic light-emitting display panel. The emission layer in the organic light-emitting display panel includes an organic light-emitting material. The emission layer in the inorganic light-emitting display panel includes quantum dots, quantum rods, or micro LEDs. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0062] The display panel DP may include a base layer BL. The display panel DP may further include a circuit element layer D-CL, a display element layer D-OL, and a packaging layer TFE disposed on the base layer BL. The input sensor INS can be directly disposed on the packaging layer TFE. In the present disclosure, the term "component A is directly disposed on component B" means that no intermediate component (e.g., an adhesive layer) is disposed between component A and component B.

[0063] The base layer BL may include at least one plastic film. The base layer BL can be a flexible substrate and includes a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite substrate, etc. In the present disclosure, the display area DA and the non-display area NDA can be considered to be defined in the base layer BL. Here, the components disposed on the base layer BL can be considered to overlap with the display area DA or the non-display area NDA.

[0064] The circuit element layer D-CL includes at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines and driving circuits of pixels, etc.

[0065] The display element layer D-OL includes partition walls and light-emitting elements. The light-emitting elements can include an anode, an emission pattern, and a cathode, and the emission pattern can include at least an emission layer.

[0066] The packaging layer TFE includes a plurality of thin films. Some thin films are provided to improve the optical efficiency, and some thin films are provided to protect the organic light-emitting diodes.

[0067] The input sensor INS obtains coordinate information of an external input. The input sensor INS can have a multi-layer structure. The input sensor INS can include a conductive layer having a single-layer structure or a multi-layer structure. The input sensor INS can include an insulating layer having a single-layer structure or a multi-layer structure. The input sensor INS can detect an external input by, for example, using a capacitive method. However, in the present disclosure, the operation method of the input sensor INS is not particularly limited, and the input sensor INS according to an embodiment supported by various aspects of the present disclosure can also detect an external input by using an electromagnetic induction method or a pressure detection method. In another embodiment supported by various aspects of the present disclosure, the input sensor INS can be omitted.

[0068] As Figure 1BAs an example, the housing HAU may be coupled to the window WP. The housing HAU may be coupled to the window WP to provide a predetermined interior space. The display module DM may be accommodated in the interior space.

[0069] The housing HAU may include a material having relatively high rigidity. For example, the housing HAU may include a plurality of frames and / or plates, each of the frames and / or plates including glass, plastic, or metal or formed of a combination of glass, plastic, and / or metal. The housing HAU may stably protect the components of the display device DD accommodated in the interior space from external impacts.

[0070] Figure 3 A plan view of a display panel according to an embodiment supported by aspects of the present disclosure.

[0071] Reference Figure 3 , the display panel DP may include a base layer BL divided into a display area DA and a non-display area NDA, as in reference Figure 2 described.

[0072] The display panel DP may include pixels PX disposed in the display area DA and signal lines SGL electrically connected to the pixels PX. The display panel DP may include a driving circuit GDC and a pad portion PLD disposed in the non-display area NDA.

[0073] The pixels PX are arranged in a first direction DR1 and a second direction DR2. The pixels PX may include a plurality of pixel rows extending in the first direction DR1 and arranged in the second direction DR2 and a plurality of pixel columns extending in the second direction DR2 and arranged in the first direction DR1.

[0074] The signal lines SGL may include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. Each of the gate lines GL may be connected to a corresponding one of the pixels PX in the pixels PX, and each of the data lines DL may be connected to a corresponding one of the pixels PX in the pixels PX. The power line PL may be electrically connected to the pixels PX. The control signal line CSL may be connected to the driving circuit GDC and provide a control signal to the driving circuit GDC.

[0075] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a gate signal and sequentially output the generated gate signal to the gate lines GL. The gate driving circuit may further output another control signal to the pixel driving circuit.

[0076] The pad portion PLD may be a portion connected to the flexible circuit board. The pad portion PLD may include pixel pads D-PD, and the pixel pads D-PD may be pads for connecting the flexible circuit board to the display panel DP. Each of the pixel pads D-PD may be connected to a corresponding signal line in the signal lines SGL. The pixel pads D-PD may be connected to the corresponding pixels PX through the signal lines SGL respectively. Additionally, one of the pixel pads D-PD may be connected to the driving circuit GDC.

[0077] The pad portion PLD may further include input pads. The input pads may be pads for connecting the flexible circuit board to the input sensor INS (see Figure 2 ). However, the embodiments supported by the present disclosure are not limited thereto, and the input pads may be provided in the input sensor INS (see Figure 2 ) and connected to a separate circuit board from the pixel pads D-PD. Alternatively, the input sensor INS (see Figure 2 ) may be omitted, and the pad portion PLD may further not include the input pads.

[0078] Figure 4 An enlarged plan view of a part of the display area of a display panel according to an embodiment supported by aspects of the present disclosure. Figure 4 Illustrates the plane of the display module DM (see Figure 2 ) when viewed on the display surface IS (see Figure 1B ) of the display module DM (see Figure 2 ), and illustrates the arrangement of the emission regions PXA-R, PXA-G, and PXA-B.

[0079] Refer to Figure 4 , the display area DA may include first to third emission regions PXA-R, PXA-G, and PXA-B and a peripheral region NPXA surrounding the first to third emission regions PXA-R, PXA-G, and PXA-B. The first to third emission regions PXA-R, PXA-G, and PXA-B may respectively correspond to regions from which light provided by the light-emitting elements ED1, ED2, and ED3 (see Figure 5D ) emits. The first to third emission regions PXA-R, PXA-G, and PXA-B may be divided according to the color of the light emitted externally toward the display module DM (see Figure 2 ).

[0080] The first to third emission regions PXA-R, PXA-G, and PXA-B may respectively provide light of first to third different colors from each other. For example, the light of the first color may be red light, the light of the second color may be green light, and the light of the third color may be blue light. However, the examples of the light of the first to third colors are not necessarily limited to the foregoing examples.

[0081] Each of the first to third emission regions PXA-R, PXA-G, and PXA-B may be defined as a region where the top surface of the anode is exposed by an emission opening portion described later in this document. The outer peripheral region NPXA may set the boundaries of each of the first to third emission regions PXA-R, PXA-G, and PXA-B and prevent color mixing between the first to third emission regions PXA-R, PXA-G, and PXA-B.

[0082] Each of the first to third emission regions PXA-R, PXA-G, and PXA-B may be provided in a plurality to have a predetermined arrangement shape and be repeatedly arranged in the display region DA. For example, the first emission region PXA-R and the third emission region PXA-B may be alternately arranged in the first direction DR1 and constitute a "first group". In the example, the second emission region PXA-G may be arranged in the first direction DR1 and constitute a "second group". Each of the "first group" and the "second group" may be provided in a plurality, and the "first group" and the "second group" may be alternately arranged in the second direction DR2.

[0083] The second emission region PXA-G may be arranged such that the second emission region PXA-G is spaced apart from the first emission region PXA-R or the third emission region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0084] Figure 4 The arrangement shapes of the first to third emission regions PXA-R, PXA-G, and PXA-B illustrated in the example are examples and are not limited thereto. The first to third emission regions PXA-R, PXA-G, and PXA-B may be arranged in various shapes. In one embodiment, the first to third emission regions PXA-R, PXA-G, and PXA-B may have an arrangement shape as Figure 4 illustrated. Alternatively, the first to third emission regions PXA-R, PXA-G, and PXA-B may have a stripe arrangement shape or a diamond (DiamondPixel TM ) arrangement shape.

[0085] Each of the first to third emission regions PXA-R, PXA-G, and PXA-B may have various shapes on a plane. For example, each of the first to third emission regions PXA-R, PXA-G, and PXA-B may have a shape such as a polygon, a circle, or an ellipse. As an example, Figure 4 the first emission region PXA-R and the third emission region PXA-B each having a square (or diamond) shape on the plane and the second emission region PXA-G having an octagonal shape are illustrated.

[0086] The first to third emission regions PXA-R, PXA-G, and PXA-B may have the same shape, or at least some of the first to third emission regions PXA-R, PXA-G, and PXA-B may have different shapes on a plane. As an example, Figure 4 illustrates the first emission region PXA-R and the third emission region PXA-B having the same shape on a plane and the second emission region PXA-G having a different shape from the first emission region PXA-R and the third emission region PXA-B.

[0087] In some embodiments, at least some of the first to third emission regions PXA-R, PXA-G, and PXA-B may have different areas on a plane. In one embodiment, the area of the first emission region PXA-R that emits red light may be greater than the area of the second emission region PXA-G that emits green light and less than the area of the third emission region PXA-B that emits blue light. However, the magnitude relationship of the areas of the first to third emission regions PXA-R, PXA-G, and PXA-B is not limited to this according to the color of the emitted light, and may be various according to the design of the display module DM (see Figure 2 ). Embodiments supported by the present disclosure are not limited to this, and the areas of the first to third emission regions PXA-R, PXA-G, and PXA-B may be the same on a plane.

[0088] According to an embodiment supported by aspects of the present disclosure, the shapes, areas, arrangements, etc. of the first to third emission regions PXA-R, PXA-G, and PXA-B of the display module DM (see Figure 2 ) may be designed in various ways according to the color of the emitted light or the size or configuration of the display module DM (see Figure 2 ), and are not limited to Figure 4 the embodiments illustrated therein.

[0089] Figure 5A is an enlarged cross-sectional view of a partial region of a display panel DP according to an embodiment supported by aspects of the present disclosure. Figure 5A is a cross-sectional view of a display panel DP according to an embodiment supported by aspects of the present disclosure taken along the line I-I' in Figure 4 .

[0090] Figure 5B is a cross-sectional view illustrating some components of a display panel DP according to an embodiment supported by aspects of the present disclosure. Figure 5B Illustrates some components of the display panel DP provided under the partition wall PW among the components of the display panel DP illustrated in Figure 5A . That is, Figure 5B illustrates in Figure 5AThe base layer BL, circuit element layer D-CL, fifth insulating layer 50, anode AE, pixel defining film PDL, and partition wall PW illustrated therein are shown, and the cathode CE and encapsulation layer TFE are omitted. Figure 5C is an embodiment supported by aspects of the present disclosure according to Figure 5B an enlarged cross-sectional view of a region AA' of a display panel DP.

[0091] Figure 5A An enlarged view of an emission region PXA in the illustrated display area DA (see Figure 3 ) is shown, and Figure 5A the emission region PXA in Figure 4 may correspond to any one of the first to third emission regions PXA-R, PXA-G, and PXA-B in

[0092] Referring to Figure 5A and Figure 5B , the display panel DP may include a base layer BL, a circuit element layer D-CL, a fifth insulating layer 50, a display element layer D-OL, and an encapsulation layer TFE.

[0093] The display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. In one example, the insulating layer, semiconductor layer, and conductive layer are formed by coating or deposition, etc. Thereafter, the insulating layer, semiconductor layer, and conductive layer may be selectively patterned by performing a photolithography process and an etching process. The semiconductor patterns, conductive patterns, signal lines, etc. included in the circuit element layer D-CL or the display element layer D-OL may be formed by the processes (e.g., coating, deposition, photolithography, and etching, etc.).

[0094] The circuit element layer D-CL may be disposed on the base layer BL. The circuit element layer D-CL may include a buffer layer BFL, a transistor TR1, a signal transmission region SCL, first to fourth insulating layers 10, 20, 30, and 40, an electrode EE, and a plurality of connection electrodes CNE1, CNE2.

[0095] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may improve the adhesion between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer (not illustrated). The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0096] The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon. However, the embodiments supported by the present disclosure are not limited thereto, and the semiconductor pattern may also include amorphous silicon or metal oxide. Figure 5A A part of the semiconductor pattern is illustrated, and the semiconductor pattern may be further disposed in the plurality of emission regions PXA-R, PXA-G, and PXA-B (see Figure 4) therein. The semiconductor pattern can be arranged throughout a plurality of emission regions PXA-R, PXA-G, and PXA-B according to specific rules (see Figure 4 ). Based on whether the semiconductor pattern is doped, the semiconductor pattern can have different electrical characteristics. The semiconductor pattern can include a first region with a high doping concentration and a second region with a low doping concentration. The first region can be doped with an n-type dopant or a p-type dopant. The p-type transistor can include a first region doped with a p-type dopant.

[0097] The first region can have higher conductivity than the second region and basically serves as an electrode or a signal line. The second region can basically serve as the active region (or channel) of the transistor. In other words, a part of the semiconductor pattern can be the active region of the transistor, another part can be the source or drain of the transistor, and yet another part can be a conductive region.

[0098] The source S, the active region A, and the drain D of the transistor TR1 can be formed by the semiconductor pattern. Figure 5A An example of a part of the signal transmission region SCL formed by the semiconductor pattern is shown. Although not shown separately, the signal transmission region SCL can be connected to the drain D of the transistor TR1 in the plane.

[0099] The first insulating layer 10 to the fourth insulating layer 40 can be provided on the buffer layer BFL. Each of the first insulating layer 10 to the fourth insulating layer 40 can be an inorganic layer or an organic layer.

[0100] The first insulating layer 10 can be provided on the buffer layer BFL. The gate G can be provided on the first insulating layer 10. The second insulating layer 20 can be provided on the first insulating layer 10 such that the second insulating layer 20 covers the gate G. The electrode EE can be provided on the second insulating layer 20. The third insulating layer 30 can be provided on the second insulating layer 20 such that the third insulating layer 30 covers the electrode EE.

[0101] The first connection electrode CNE1 can be provided on the third insulating layer 30. The first connection electrode CNE1 can be connected to the signal transmission region SCL through a contact hole CNT-1 passing through the first insulating layer 10 to the third insulating layer 30. The fourth insulating layer 40 can be provided on the third insulating layer 30 such that the fourth insulating layer 40 covers the first connection electrode CNE1. The fourth insulating layer 40 can be an organic layer.

[0102] The second connection electrode CNE2 can be provided on the fourth insulating layer 40. The second connection electrode CNE2 can be connected to the first connection electrode CNE1 through a contact hole CNT-2 passing through the fourth insulating layer 40.

[0103] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may cover the second connection electrode CNE2. The fifth insulating layer 50 may be an inorganic layer or an organic layer. In the example illustrated herein, the fifth insulating layer 50 may be composed of a single film.

[0104] A groove HP may be defined in the fifth insulating layer 50. The groove HP may overlap with the emission region PXA in a plane. As Figure 5A illustrated, a part of the groove HP may overlap with the outer peripheral region NPXA. The groove HP may be provided by removing a part of the fifth insulating layer 50 from the top surface of the fifth insulating layer 50. The anode AE may be disposed in the groove HP defined in the fifth insulating layer 50.

[0105] The top surface of the fifth insulating layer 50 may include a first surface UF1-I overlapping with the outer peripheral region NPXA and a second surface UF2-I overlapping with the emission region PXA. With respect to the thickness direction as the third direction DR3, a step portion may be present between the first surface UF1-I and the second surface UF2-I. The step portion between the first surface UF1-I and the second surface UF2-I may be defined as the height difference between the first surface UF1-I and the second surface UF2-I in the third direction DR3. The top surface of the fifth insulating layer 50 may include an inner surface IF-I connecting the first surface UF1-I to the second surface UF2-I. The inner surface IF-I and the second surface UF2-I may define the groove HP.

[0106] The inner surface IF-I defining the groove HP may be provided with a predetermined inclination. The inner surface IF-I provided on the fifth insulating layer 50 may be an inclined surface. Therefore, the groove HP may have a shape with a width gradually increasing from the lower part to the upper part of the fifth insulating layer 50. The inner surface IF-I defining the groove HP may have a shape inclined at a first angle θ1 with respect to the top surface of the base layer BL. The first angle θ1 may be an acute angle. The first angle θ1 may be greater than about 0° and less than about 90°. For example, the first angle θ1 may be about 45° to about 85°.

[0107] The display element layer D-OL may be disposed on the fifth insulating layer 50. The display element layer D-OL may include a light-emitting element ED, a sacrificial pattern SP, a pixel defining film PDL, a partition wall PW, and a dummy pattern DMP.

[0108] The light-emitting element ED may include an anode AE (or a first electrode), an emission pattern EP, and a cathode CE (or a second electrode). Each of the first to third light-emitting elements ED1, ED2, and ED3 (see Figure 5D ) to be described later herein may include Figure 5Acomponents that are substantially the same as the light-emitting element ED therein. The same / similar descriptions of the anode AE, the emission pattern EP, and the cathode CE can be applied to the anodes, the emission patterns, and the cathodes of each of the first to third light-emitting elements ED1, ED2, and ED3 (see Figure 5D ).

[0109] At least a part of the anode AE can be disposed in the groove HP of the fifth insulating layer 50. The anode AE can be patterned and provided for each emission region PXA. The anode AE can be disposed on the second surface UF2-I and the inner surface IF-I of the fifth insulating layer 50. Alternatively, or additionally, as Figure 5A illustrated therein, a part of the anode AE can be disposed on the first surface UF1-I of the fifth insulating layer 50. That is, the anode AE can be provided in a shape such that the anode AE is disposed on the first surface UF1-I, the second surface UF2-I, and the inner surface IF-I, the anode AE does not extend continuously, and the anode AE has a part that is disconnected on the first surface UF1-I. Expressed in another way, the anode AE can partially extend on the first surface UF1-I or partially overlap with the first surface UF1-I. However, embodiments of the present disclosure are not limited thereto, and the anode AE can be disposed in the groove HP but not on the first surface UF1-I of the fifth insulating layer 50.

[0110] The anode AE can be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE can have conductivity. For example, the anode AE can be formed of various materials such as, for example, a metal, a transparent conductive oxide (TCO), or a conductive polymer material such that the anode AE can exhibit conductivity. The anode AE can be connected to the second connection electrode CNE2 through the connection contact hole CNT-3 passing through and defined in the fifth insulating layer 50. Thus, the anode AE can be electrically connected to the signal transmission region SCL through the first connection electrode CNE1 and the second connection electrode CNE2, and the anode AE can be electrically connected to the corresponding circuit element.

[0111] The sacrificial pattern SP can be disposed between the anode AE and the pixel defining film PDL. The sacrificial pattern SP can be a part of a layer provided to prevent damage to the anode AE during the process of forming the isolation wall opening portion OP-P, etc., described later herein. At least a part of the sacrificial pattern SP can be disposed in the groove HP of the fifth insulating layer 50. The sacrificial pattern SP can be shaped such that at least a part of the sacrificial pattern SP extends along the inner surface IF-I of the fifth insulating layer 50. The sacrificial pattern SP can be disposed between the pixel defining film PDL and the inner surface IF-I.

[0112] A sacrificial opening portion OP-S that exposes a part of the top surface of the exposed anode AE may be defined in the sacrificial pattern SP. The sacrificial opening portion OP-S may overlap with an emission opening portion OP-E described later herein. The sacrificial pattern SP may include an amorphous transparent conductive oxide. For example, the sacrificial pattern SP may be zinc oxide (ZnO x ) doped with aluminum (Al).

[0113] A pixel defining layer PDL may be disposed on the fifth insulating layer 50. The pixel defining layer PDL may overlap with the outer peripheral region NPXA in a plane. The pixel defining layer PDL may be disposed on the first surface UF1-I of the fifth insulating layer 50. A part of the pixel defining layer PDL may be disposed in the groove HP of the fifth insulating layer 50. As Figure 5A illustrated, the pixel defining layer PDL may have a shape disposed on the first surface UF1-I of the fifth insulating layer 50 and extending along the inner surface IF-I of the fifth insulating layer 50. A part of the pixel defining layer PDL may be disposed on the second surface UF2-I of the fifth insulating layer 50. The emission opening portion OP-E may be defined in the pixel defining layer PDL. The pixel defining layer PDL may expose at least a part of the anode AE through the emission opening portion OP-E. The emission opening portion OP-E may correspond to the sacrificial opening portion OP-S. In one embodiment, the emission opening portion OP-E may overlap with the groove HP.

[0114] The area of the emission opening portion OP-E may be equal to or larger than the area of the sacrificial opening portion OP-S in a plane. As Figure 5A illustrated, the inner surface of the pixel defining layer PDL that defines the emission opening portion OP-E may be substantially aligned with the inner surface of the sacrificial pattern SP that defines the sacrificial opening portion OP-S. However, embodiments supported by the present disclosure are not limited thereto, and the inner surface of the pixel defining layer PDL that defines the emission opening portion OP-E may be closer to the center of the anode AE than the inner surface of the sacrificial pattern SP that defines the sacrificial opening portion OP-S. Here, the emission region PXA may be considered as the region of the anode AE exposed by the corresponding sacrificial opening portion OP-S.

[0115] The pixel defining layer PDL may include an inorganic insulating material. For example, the pixel defining layer PDL may include silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride. Thus, for example, moisture release from the pixel defining layer PDL during subsequent patterning processes may be prevented. The pixel defining layer PDL may be disposed between the anode AE and the isolation wall PW and prevent an electrical connection between the anode AE and the isolation wall PW.

[0116] The partition wall PW (or the conductive partition wall) may be provided on the pixel defining film PDL. The partition wall opening portion OP-P may be defined in the partition wall PW. The partition wall opening portion OP-P may correspond to the emission opening portion OP-E and may expose at least a part of the anode AE.

[0117] At least a part of the partition wall PW may have a shape extending along the inner surface IF-I of the fifth insulating layer 50. In other words, at least a part of the partition wall PW may extend along the inner surface IF-I of the fifth insulating layer 50. The partition wall PW may be divided into a plurality of parts in the extending direction. The partition wall PW may include a first flat part extending in a first extending direction, a bent part extending in a second extending direction, and a second flat part extending in a third extending direction.

[0118] The first flat part may be provided on the first surface UF1-I of the fifth insulating layer 50. The first extending direction in which the first flat part extends may be parallel to the top surface of the base layer BL. The bent part may extend from the end of the first flat part along the inner surface IF-I of the fifth insulating layer 50. The second extending direction in which the bent part extends may be parallel to a straight line inclined at a predetermined angle with respect to the top surface of the base layer BL. For example, the second extending direction may be the same as the extending direction of the inner surface IF-I of the fifth insulating layer 50. That is, the angle at which the bent part is inclined with respect to the top surface of the base layer BL may be substantially equal to the angle at which the inner surface IF-I is inclined with respect to the top surface of the base layer BL.

[0119] The second flat part may have a step difference from the first flat part in the third direction DR3. The third extending direction in which the second flat part extends may be parallel to the top surface of the base layer BL. The third extending direction in which the second flat part extends may be substantially the same as the first extending direction in which the first flat part extends. However, embodiments of the present disclosure are not limited thereto, and the third extending direction and the first extending direction may be different from each other.

[0120] The bent part of the partition wall PW may have a shape inclined at a second angle θ2 with respect to the top surface of the base layer BL. The second angle θ2 may be an acute angle. The second angle θ2 may be greater than about 0° and less than about 90°. For example, the second angle θ2 may be about 45° to about 85°. In one embodiment, the second angle θ2 may be substantially equal to the first angle θ1.

[0121] The isolation wall PW may have an undercut shape in cross-section. The isolation wall PW may include a terminal portion TP protruding from a part of the isolation wall PW in cross-section. A part of the second flat portion and the bent portion of the isolation wall PW may define the terminal portion TP. The terminal portion TP may include a first terminal portion protruding from the part of the isolation wall PW in the bent portion in a second extension direction in which the bent portion extends, and the terminal portion TP may include a second terminal portion extending from the first terminal portion in a third extension direction.

[0122] The second terminal portion may correspond to the second flat portion described herein. The first terminal portion may extend along the inner surface IF-I, and the first terminal portion may have a shape inclined at a second angle θ2 with respect to the top surface of the base layer BL. The second terminal portion may have a shape extending from the first terminal portion in a direction parallel to the top surface of the base layer BL.

[0123] The isolation wall PW may include a plurality of layers stacked in order, and in the stacked layers included in the plurality of layers, at least one of the adjacent stacked layers may include a terminal portion protruding from the other adjacent stacked layers. For example, the uppermost layer among the plurality of layers included in the isolation wall PW may include a terminal portion protruding from the remaining adjacent layers included in the isolation wall PW. As an example, Figure 5A An isolation wall PW in which two layers (for example, a first isolation wall layer L1 and a second isolation wall layer L2) are stacked is illustrated, and the layer (for example, the second isolation wall layer L2) provided on the upper side of these two layers includes a protruding terminal portion TP. However, embodiments of the present disclosure are not limited thereto. For example, the isolation wall PW may have a structure in which three or more layers are stacked, and the layer provided on the uppermost side of the three or more layers may include a protruding terminal portion.

[0124] In an exemplary embodiment, the isolation wall PW may include a first isolation wall layer L1 and a second isolation wall layer L2. The first isolation wall layer L1 may be provided on the pixel defining layer PDL, and the second isolation wall layer L2 may be provided on the first isolation wall layer L1. The first isolation wall layer L1 may be directly provided on the pixel defining layer PDL, and the second isolation wall layer L2 may be directly provided on the first isolation wall layer L1.

[0125] The first isolation wall layer L1 may have a thickness greater than the thickness of the second isolation wall layer L2. In the present disclosure, the thickness of the first isolation wall layer L1 may mean the distance between the bottom surface and the top surface of the first isolation wall layer L1 measured with respect to the third direction DR3 on the first surface UF1-I of the fifth insulating layer 50. Additionally, the thickness of the second isolation wall layer L2 may mean the distance between the bottom surface and the top surface of the second isolation wall layer L2 measured with respect to the third direction DR3 on the first surface UF1-I of the fifth insulating layer 50.

[0126] The first isolation wall layer L1 may have a first conductivity, and the second isolation wall layer L2 may have a second conductivity. In one embodiment, the first conductivity of the first isolation wall layer L1 may be higher than the second conductivity of the second isolation wall layer L2. In some embodiments, the first conductivity of the first isolation wall layer L1 may be the same as the second conductivity of the second isolation wall layer L2.

[0127] The second isolation wall layer L2 may be formed of a material that supports etching according to a first etching rate, and the first isolation wall layer L1 may be formed of a material that supports etching according to a second etching rate higher than the first etching rate. In the present disclosure, each of the first etching rate and the second etching rate may mean an etching rate supported by an etchant used in a "undercut etching process" described later herein. In the "undercut etching process", since the etching rate of the first isolation wall layer L1 is higher than the etching rate of the second isolation wall layer L2, the inner surface of the first isolation wall layer L1 may be etched more than the inner surface of the second isolation wall layer L2. Alternatively, due to the second etching rate associated with the second isolation wall layer L2, the second isolation wall layer L2 may not be etched or may be substantially unetched in the "undercut etching process".

[0128] Compared with the second isolation wall layer L2, the first isolation wall layer L1 may be relatively recessed from the emission region PXA. That is, for example, the first isolation wall layer L1 may be undercut relative to the second isolation wall layer L2. The first isolation wall layer L1 may include a first inner surface S1-P, and the second isolation wall layer L2 may include a second inner surface S2-P. The first inner surface S1-P of the first isolation wall layer L1 and the second inner surface S2-P of the second isolation wall layer L2 may define an isolation wall opening portion OP-P of the isolation wall PW.

[0129] Compared with the second inner surface S2-P of the second isolation wall layer L2, the first inner surface S1-P of the first isolation wall layer L1 may be relatively further inwardly disposed compared to the emission region PXA. That is, for example, the first inner surface S1-P generated by the undercut etching process described herein may be recessed from the second inner surface S2-P in a direction away from the emission region PXA. The first inner surface S1-P may be undercut relative to the second inner surface S2-P. The portion of the second isolation wall layer L2 that protrudes from the first isolation wall layer L1 toward the emission region PXA may define a terminal portion TP.

[0130] Reference Figure 5B and Figure 5C, the second isolation wall layer L2 may include a plurality of first to third portions P1, P2, and P3. The second isolation wall layer L2 may be divided into a first portion P1, a second portion P2, and a third portion P3. The first portion P1 may overlap with the outer peripheral region NPXA. The first portion P1 of the second isolation wall layer L2 may be the portion disposed on the first surface UF1-I of the fifth insulating layer 50. The first portion P1 may include a flat top surface.

[0131] The second portion P2 may be the portion extending from the first portion P1 along the inner surface IF-I. The second portion P2 may have a shape extending from the end of the first portion P1 and inclined at a second angle θ2 with respect to the top surface of the base layer BL. The third portion P3 may be the portion extending from the end of the second portion P2. The third portion P3 may have a step difference from the first portion P1 in the third direction DR3. The third portion P3 may have a shape extending at a third angle different from the second angle θ2. The third angle may be less than the second angle θ2. For example, the third angle may be 0° or approximately 0°. That is, for example, the third portion P3 may have a shape extending in a direction parallel to the top surface of the base layer BL.

[0132] The first isolation wall layer L1 may include a plurality of isolation wall portions P1-W, P2-W. For example, the first isolation wall layer L1 may include a first isolation wall portion P1-W and a second isolation wall portion P2-W. The first isolation wall portion P1-W may be disposed between the first portion P1 of the second isolation wall layer L2 and the pixel defining film PDL. The first isolation wall portion P1-W may overlap with the outer peripheral region NPXA.

[0133] The second isolation wall portion P2-W may be the portion extending from the first isolation wall portion P1-W along the inner surface IF-I. The second isolation wall portion P2-W may be disposed between the second portion P2 of the second isolation wall layer L2 and the inner surface IF-I of the fifth insulating layer 50. The second isolation wall portion P2-W may have a shape extending from the end of the first isolation wall portion P1-W and inclined at a second angle θ2 with respect to the top surface of the base layer BL.

[0134] The first partition wall portion P1-W of the first partition wall layer L1 may include a first bottom surface adjacent to the pixel defining layer PDL, and the first partition wall portion P1-W may include a first top surface opposite to the first bottom surface in the third direction DR3. The second partition wall portion P2-W of the first partition wall layer L1 may include a second bottom surface extending along the inner surface IF-I from the first bottom surface. The second partition wall portion P2-W of the first partition wall layer L1 may include a second top surface opposite to the second bottom surface and extending along the inner surface IF-I from the first top surface. The second partition wall portion P2-W of the first partition wall layer L1 may include a connecting surface connecting the second bottom surface to the second top surface. Each of the second bottom surface and the second top surface may be an inclined surface inclined at a second angle θ2 with respect to the top surface of the base layer BL. The connecting surface of the second partition wall portion P2-W may correspond to the inner surface of the first partition wall layer L1.

[0135] In the second partition wall layer L2, a part of the second portion P2 (also referred to as a sub-portion herein) and a part of the third portion P3 (also referred to as a sub-portion herein) may define an end portion TP. Refer to Figure 5C , the second portion P2 of the second partition wall layer L2 may include a first sub-portion P2-1 and a second sub-portion P2-2. In one embodiment, the first sub-portion P2-1 contacts the second partition wall portion P2-W of the first partition wall layer L1, and the second sub-portion P2-2 protrudes from the inner surface of the second partition wall portion P2-W. The second sub-portion P2-2 may not contact the second partition wall portion P2-W. The second sub-portion P2-2 may correspond to the first end portion of the end portion TP described herein.

[0136] The second partition wall layer L2 may have an inner surface protruding from the inner surface of the first partition wall layer L1. A part of the inner surface of the first partition wall layer L1 may overlap the end portion TP in cross-section. When viewed in a fourth direction DR4 perpendicular to the third direction DR3, at least a part of the inner surface of the first partition wall layer L1 may overlap the end portion TP. For example, when viewed in the fourth direction DR4, the above-mentioned part of the inner surface of the first partition wall layer L1 may overlap the end portion TP, and other parts may not overlap the end portion TP.

[0137] The portion of the inner surface of the first spacer layer L1 that overlaps with the end portion TP may be covered by the end portion TP and may not be exposed when viewed in the fourth direction DR4. Additionally, the portion of the inner surface of the first spacer layer L1 that does not overlap with the end portion TP may be exposed by the end portion TP when viewed in the fourth direction DR4. However, embodiments of the present disclosure are not limited thereto, and when viewed in the fourth direction DR4, the entire region of the inner surface of the first spacer layer L1 may overlap with the end portion TP. In this case, the entire inner surface of the first spacer layer L1 may be covered so that the entire inner surface of the first spacer layer L1 is not exposed by the end portion TP when viewed in the fourth direction DR4.

[0138] The length of the end portion TP may be in the range of about 0.6 μm to about 1.5 μm. Example embodiments in which the length of the end portion TP satisfies this range may prevent step coverage and the like. For example, in some cases, during the formation of the emission pattern EP, step coverage and the like may be formed as an organic layer deposited on the inner surface of the first spacer layer L1 along the bottom surface of the end portion TP. Thus, for example, water vapor transmission through step coverage can be prevented, ensuring the reliability of the display device. In the present disclosure, the length of the end portion TP may refer to the sum of the first length d1 of the third portion P3 of the second spacer layer L2 and the second length d2 of the second sub-portion P2-2 of the second portion P2 of the second spacer layer L2.

[0139] In one embodiment, the length (d1 + d2) of the end portion TP may be represented by Equation 1 below. The length (d1 + d2) of the end portion TP defined by Equation 1 below may be about 0.6 μm to about 1.5 μm.

[0140] [Equation 1]

[0141] End portion length = a + (b / cosθ2)

[0142] In Equation 1, a represents the first length d1 of the bottom surface of the third portion P3.

[0143] In Equation 1, b represents the length measured from one end of the second sub-portion P2-2 adjacent to the third portion P3 to the other end of the second sub-portion P2-2 spaced apart from the third portion P3 in a direction in which the third portion P3 extends. That is, b means the distance d between the first point PT1 and the second point PT2 a, where the first point PT1 is defined as the first point where the bottom surface of the second part P2 is connected to the bottom surface of the third part P3. The second point PT2 is defined as the second point where a first virtual line IL1 extending from the point of contact between the bottom surface of the second part P2 and the inner surface of the first isolation wall layer L1 in a direction perpendicular to the above-mentioned one direction intersects a second virtual line IL2 extending from the first point PT1 in a direction parallel to the above-mentioned one direction.

[0144] In Equation 1, θ2 represents the second angle.

[0145] Reference Figure 5C , the first virtual line IL1 can be defined as extending from the point of contact between the bottom surface of the second part P2 and the inner surface of the first isolation wall layer L1 in a direction perpendicular to the direction in which the third part P3 extends. For example, the first virtual line IL1 can be a straight line extending from the point of contact between the bottom surface of the second part P2 and the inner surface of the first isolation wall layer L1 in a third direction DR3 perpendicular to a direction parallel to the top surface of the base layer BL. Additionally, the second virtual line IL2 can be defined as extending from the first point PT1 where the bottom surface of the second part P2 is connected to the bottom surface of the third part P3 in the direction in which the third part P3 extends. For example, the second virtual line IL2 can be a straight line extending in the above-mentioned one direction parallel to the top surface of the base layer BL. Here, the bottom surface of the second sub-part P2-2 of the second part P2, the first virtual line IL1, and the second virtual line IL2 can be connected to each other to form a right triangle. The angle formed between the bottom surface of the second sub-part P2-2 of the second part P2 and the second virtual line IL2 can be the second angle θ2. The second length d2 of the second sub-part P2-2 can be b / cosθ2. Therefore, the length (d1 + d2) of the portion protruding from the end portion TP can be the sum of the first length d1 and the second length d2 corresponding to b / cosθ2.

[0146] When the end portion does not include a bent portion and includes a flat portion extending in one direction (e.g., only includes a flat portion extending in one direction instead of including a flat portion and a bent portion), step coverage may occur, where in the process of depositing an emission pattern in the isolation wall opening portion, the organic layer is deposited from the bottom surface of the end portion along the concave inner surface of the isolation wall. Step coverage can serve as a transmission path for foreign substances such as moisture or oxygen, and can cause defects such as pixel shrinkage. To prevent the formation of step coverage, aspects of the present disclosure described herein support methods such as increasing the length of the end portion in a given region of the emission region or adjusting the deposition incident angle of the organic material. However, in some cases, there may be limitations to increasing the length of the end portion in a given region of the emission region, and even if the deposition incident angle is adjusted, it may be difficult to fully control the formation of step coverage.

[0147] In a display panel according to an embodiment supported by aspects of the present disclosure, since the end portion includes a first portion inclined at a predetermined angle, the length per unit area of the end portion can be provided to be greater than the length per unit area of the existing end portion, thereby preventing step coverage in which an organic material is deposited on the bottom surface of the end portion. In some aspects, even if the deposition incident angle of the organic material is not adjusted, during the deposition of the emission pattern, the bottom surface of the end portion corresponding to the first portion can be blocked by the first portion, so that step coverage caused by the deposition of the organic material is not formed. For example, even if the deposition incident angle is about 0°, a part of the bottom surface of the end portion can be blocked by the first portion to prevent the organic material from being deposited along the end portion onto a part of the inner surface of the partition wall. That is, for example, even if the organic material is introduced from one end of the end portion adjacent to the center of the emission region PXA in a direction parallel to the top surface of the base layer BL, the bottom surface of the end portion corresponding to the first end portion can be blocked by the first portion, thereby preventing the organic material from being deposited along the end portion onto a part of the inner surface of the partition wall. Therefore, defects such as pixel shrinkage that may occur due to step coverage of the end portion can be prevented. In some aspects, even without an additional device for adjusting the deposition incident angle, step coverage formation can be suppressed, thereby reducing the manufacturing cost associated with the display panel, simplifying the process, and also reducing the defect rate during manufacturing.

[0148] Refer again to Figure 5A , the first partition wall layer L1 may include a conductive material. The conductive material may include: a metal, a transparent conductive oxide (TCO), or a combination of a metal and a transparent conductive oxide (TCO). For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy of any one of gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), and copper (Cu). The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide.

[0149] The second partition wall layer L2 may be provided on the first partition wall layer L1. The second partition wall layer L2 may be directly provided on the first partition wall layer L1. The second partition wall layer L2 may define an end portion provided on the partition wall PW. The top surface of the second partition wall layer L2 may constitute the uppermost surface of the partition wall PW and may define the top surface of the end portion provided on the partition wall PW.

[0150] The second isolation wall layer L2 may include a material having lower conductivity but higher strength than the material of the first isolation wall layer L1. The second isolation wall layer L2 may include a material having a high Young's modulus of, for example, about 300 GPa or more. For the case where the second isolation wall layer L2 includes the material having a high Young's modulus described herein, the deformation of the second isolation wall layer L2 can be reduced. Since the deformation of the second isolation wall layer L2 constituting the uppermost surface of the isolation wall PW is reduced, the robustness of the undercut shape of the isolation wall PW can be increased. Therefore, the shape of the drooping of the end portion of the isolation wall PW can be reduced or removed, and the shape of the end portion blocking the inner surface of the isolation wall PW (in contact with the cathode CE) can be reduced or removed.

[0151] In one embodiment, the second isolation wall layer L2 may include a second metal or a silicon-based compound.

[0152] In one embodiment, the second isolation wall layer L2 may include a second metal. The second metal included in the second isolation wall layer L2 may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy of gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), or copper (Cu). The second isolation wall layer L2 may include a metal material different from the metal material of the first isolation wall layer L1. The second isolation wall layer L2 may include, for example, titanium (Ti). The second isolation wall layer L2 may have a thickness of about 400 angstroms to about 800 angstroms.

[0153] In one embodiment, different from the first isolation wall layer L1 including a metal material, the second isolation wall layer L2 may not include a metal material. That is, for example, the second isolation wall layer L2 may include a non-metal material. The second isolation wall layer L2 may include a silicon-based compound. The second isolation wall layer L2 may include at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon oxynitride (SiO x N y ). The second isolation wall layer L2 may include, for example, silicon oxide (SiO x ). Different from the first isolation wall layer L1 in contact with the cathode CE, the second isolation wall layer L2 is a component not in contact with the cathode CE. The second isolation wall layer L2 has an end portion that confines the cathode CE to the emission region PXA, and thus the second isolation wall layer L2 may also include a silicon-based compound as an insulating material.

[0154] The emission pattern EP can be provided on the anode AE. The emission pattern EP can include an emission layer including a light-emitting material. The emission pattern EP can further include a hole injection layer (HIL) and a hole transport layer (HTL) provided between the anode AE and the emission layer. The emission pattern EP can further include an electron transport layer (ETL) and an electron injection layer (EIL) provided on the emission layer. The emission pattern EP can be referred to as an "organic layer" or an "intermediate layer".

[0155] The emission pattern EP can be patterned by a terminal portion TP defined in the partition wall PW. The emission pattern EP can be provided inside the sacrificial opening portion OP-S, the emission opening portion OP-E, and the partition wall opening portion OP-P. The emission pattern EP can cover a portion of the top surface of the pixel defining film PDL exposed from the partition wall opening portion OP-P.

[0156] The cathode CE can be provided on the emission pattern EP. The cathode CE can be patterned by a terminal portion TP defined in the partition wall PW. The cathode CE can be in contact with a first inner surface S-L1 of the first partition wall layer L1. The cathode CE can have conductivity. The cathode CE can be formed of various materials such as, for example, a metal, a transparent conductive oxide (TCO), or a conductive polymer material so that the cathode CE can exhibit conductivity.

[0157] The partition wall PW can receive a bias voltage. Since the cathode CE is in direct contact with the partition wall PW, the cathode CE and the partition wall PW can be electrically connected to each other and receive the bias voltage.

[0158] As an example, Figure 5A An example of a state where the emission pattern EP is not in contact with the first inner surface S1-P of the first partition wall layer L1 is illustrated. However, embodiments supported by the present disclosure are not limited thereto, and a part of the emission pattern EP can be in contact with the first inner surface S1-P.

[0159] According to an embodiment supported by aspects of the present disclosure, the display panel DP can further include a capping pattern CP. The capping pattern CP can be provided in the partition wall opening portion OP-P and on the cathode CE. The capping pattern CP can be patterned by a terminal portion TP provided on the partition wall PW. The capping pattern CP can include at least one of an inorganic layer and an organic layer. The capping pattern CP can protect the light-emitting element ED provided thereunder.

[0160] The dummy pattern DMP can be provided on the partition wall PW. The dummy pattern DMP can include a first dummy pattern D1, a second dummy pattern D2, and a third dummy pattern D3. The first to third dummy patterns D1, D2, and D3 can be sequentially stacked on the top surface of the second partition wall layer L2 of the partition wall PW in a third direction DR3.

[0161] The first dummy pattern D1 may include an organic material. For example, the first dummy pattern D1 may include the same material as the emission pattern EP. The first dummy pattern D1 may be formed simultaneously with the emission pattern EP through one process, and then separated from the emission pattern EP by the undercut shape of the partition wall PW.

[0162] The second dummy pattern D2 may include a conductive material. For example, the second dummy pattern D2 may include the same material as the cathode CE. The second dummy pattern D2 may be formed simultaneously with the cathode CE through one process, and then the second dummy pattern D2 may be separated from the cathode CE by the undercut shape of the partition wall PW.

[0163] The third dummy pattern D3 may include at least one of an inorganic layer and an organic layer. The third dummy pattern D3 may include the same material as the capping pattern CP. The third dummy pattern D3 may be formed simultaneously with the capping pattern CP through one process, and then the third dummy pattern D3 may be separated from the capping pattern CP by the undercut shape of the partition wall PW.

[0164] A dummy opening portion OP-D may be defined in the dummy pattern DMP. The dummy opening portion OP-D may correspond to the emission opening portion OP-E. The dummy opening portion OP-D may be defined by the respective inner surfaces of the first to third dummy patterns D1, D2, and D3. In one embodiment, the respective inner surfaces of the first to third dummy patterns D1, D2, and D3 may be substantially aligned and may define the overall opening space of the dummy opening portion OP-D. Each of the first to third dummy patterns D1, D2, and D3 may have a closed line shape in a plane surrounding the corresponding emission region PXA.

[0165] As an example, Figure 5A Illustrate the state where the respective inner surfaces of the first to third dummy patterns D1, D2, and D3 are aligned with the second inner surface S2-P of the second partition wall layer L2. However, the embodiments supported by the present disclosure are not limited thereto, and the inner surfaces of the first to third dummy patterns D1, D2, and D3 may cover at least a part of the second inner surface S2-P of the second partition wall layer L2.

[0166] The encapsulation layer TFE may be provided on the display element layer D-OL. The encapsulation layer TFE may include a lower inorganic encapsulation pattern LIL, an organic encapsulation film OL, and an upper inorganic encapsulation film UIL.

[0167] The lower inorganic encapsulation pattern LIL may correspond to the emission opening portion OP-E. The lower inorganic encapsulation pattern LIL may cover the light-emitting element ED and the dummy pattern DMP, and a part of the lower inorganic encapsulation pattern LIL may be provided inside the partition wall opening portion OP-P and in contact with the partition wall PW.

[0168] The organic encapsulation film OL can cover the underlying inorganic encapsulation pattern LIL and provide a flat top surface. The upper inorganic encapsulation film UIL can be disposed on the organic encapsulation film OL.

[0169] The underlying inorganic encapsulation pattern LIL and the upper inorganic encapsulation film UIL can protect the display element layer D-OL from moisture / oxygen, and the organic encapsulation film OL can protect the display element layer D-OL from foreign substances such as dust particles.

[0170] Figure 5D A cross-sectional view taken along line II-II' in a display panel according to an embodiment supported by aspects of the present disclosure. Figure 4 in the figure. Figure 5D An enlarged view illustrating the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B. Figures 5A to 5C The same / similar description of one emission region PXA in the figure can be applied to each of the first to third emission regions PXA-R, PXA-G, and PXA-B.

[0171] Referring to Figure 5D , a display panel DP according to one or more embodiments may include a base layer BL, a circuit element layer D-CL, a fifth insulating layer 50, a display element layer D-OL, and a encapsulation layer TFE. The display element layer D-OL may include light-emitting elements ED1, ED2, and ED3, sacrificial patterns SP1, SP2, and SP3, a pixel defining film PDL, a partition wall PW, and a dummy pattern DMP.

[0172] The light-emitting elements ED1, ED2, and ED3 may include a first light-emitting element ED1, a second light-emitting element ED2, and a third light-emitting element ED3.

[0173] The first light-emitting element ED1 may include a first anode AE1 (or a first electrode 1-1), a first emission pattern EP1, and a first cathode CE1 (or a second electrode 2-1). The second light-emitting element ED2 may include a second anode AE2 (or a first electrode 1-2), a second emission pattern EP2, and a second cathode CE2 (or a second electrode 2-2). The third light-emitting element ED3 may include a third anode AE3 (or a first electrode 1-3), a third emission pattern EP3, and a third cathode CE3 (or a second electrode 2-3). The first to third anodes AE1, AE2, and AE3 may be provided as a plurality of patterns. In one embodiment, the first emission pattern EP1 may provide red light, the second emission pattern EP2 may provide green light, and the third emission pattern EP3 may provide blue light.

[0174] In an exemplary embodiment, the first to third emission opening portions OP1-E, OP2-E, and OP3-E may be defined in the pixel defining film PDL.

[0175] The first emission opening portion OP1-E may expose at least a portion of the first anode AE1. The first emission region PXA-R may be defined as the region of the top surface of the first anode AE1 that is exposed by the first emission opening portion OP1-E. The second emission opening portion OP2-E may expose at least a portion of the second anode AE2. The second emission region PXA-G may be defined as the region of the top surface of the second anode AE2 that is exposed by the second emission opening portion OP2-E. The third emission opening portion OP3-E may expose at least a portion of the third anode AE3. The third emission region PXA-B may be defined as the region of the top surface of the third anode AE3 that is exposed by the third emission opening portion OP3-E.

[0176] In an exemplary embodiment, the sacrificial patterns SP1, SP2, and SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. The first to third sacrificial patterns SP1, SP2, and SP3 may be disposed on the top surfaces of the first to third anodes AE1, AE2, and AE3, respectively. First to third sacrificial opening portions OP1-S, OP2-S, and OP3-S that overlap with the first to third emission opening portions OP1-E, OP2-E, and OP3-E may be defined in the first to third sacrificial patterns SP1, SP2, and SP3, respectively.

[0177] In an exemplary embodiment, first to third isolation wall opening portions OP1-P, OP2-P, and OP3-P that overlap with the first to third emission opening portions OP1-E, OP2-E, and OP3-E may be defined in the isolation wall PW. The first emission pattern EP1 and the first cathode CE1 may be disposed in the first isolation wall opening portion OP1-P, the second emission pattern EP2 and the second cathode CE2 may be disposed in the second isolation wall opening portion OP2-P, and the third emission pattern EP3 and the third cathode CE3 may be disposed in the third isolation wall opening portion OP3-. Each of the first to third cathodes CE1, CE2, and CE3 may be in contact with the first inner side surface S1-P of the first isolation wall layer L1 (see Figure 5A ).

[0178] In an exemplary embodiment, the first to third cathodes CE1, CE2, and CE3 may be physically separated by the second isolation wall layer L2 at their end portions, and are respectively defined in the emission opening portions OP1-E, OP2-E, and OP3-E, and each may be in contact with the first isolation wall layer L1, and thus are electrically connected to each other to receive a common voltage. Compared with the second isolation wall layer L2, the first isolation wall layer L1 may have relatively high conductivity and a large thickness, and thus reduce the contact resistance with the first to third cathodes CE1, CE2, and CE3. Therefore, a common cathode voltage may be uniformly supplied to the emission regions PXA-R, PXA-G, and PXA-B.

[0179] In one embodiment supported by aspects of the present disclosure, multiple emission patterns EP1, EP2, and EP3 can be patterned and deposited as pixel units through end portions defined in the isolation wall PW. That is, the first emission pattern EP1 can be formed jointly using an opening mask, but can be easily separated into pixel units by the isolation wall PW.

[0180] In contrast, according to some other methods, a fine metal mask (FMM) is used to pattern the first emission pattern EP1, and support spacers protruding from the isolation wall are provided to support the fine metal mask. Since the fine metal mask is spaced from the substrate surface to be patterned by the height of the isolation wall and the spacers, the achievement of high resolution may be limited. In addition, since the fine metal mask contacts the spacers, foreign matter may remain on the spacers, or the spacers may be damaged due to the penetration of the fine metal mask after the process of patterning the first emission pattern EP1. Therefore, such other methods may result in a defective display panel.

[0181] According to one or more embodiments, since the isolation wall PW is included, physical separation between the light-emitting elements ED1, ED2, and ED3 can be easily achieved. Therefore, driving errors or current leakage between adjacent emission regions PXA-R, PXA-G, and PXA-B can be prevented, and the light-emitting elements ED1, ED2, and ED3 can be driven independently of each other.

[0182] Particularly, since multiple first emission patterns EP1 are patterned without a mask contacting internal components in the display area DA (see Figure 2 ), the defect rate can be reduced, and thus a display panel DP with improved process reliability can be provided. Since patterning can be achieved even without providing separate support spacers protruding from the isolation wall PW, the area of each of the emission regions PXA-R, PXA-G, and PXA-B can be miniaturized to provide a display panel DP that can be easily achieved with high resolution.

[0183] In addition, since the techniques described herein support omitting the manufacture of a mask with a large area from the manufacture of a display panel DP with a large area, the process cost can be reduced, and the display panel DP can be free from defects that may occur in a mask with a large area. Therefore, a display panel DP with improved process reliability can be provided.

[0184] In an exemplary embodiment, the capping patterns CP1, CP2, and CP3 may include a first capping pattern CP1, a second capping pattern CP2, and a third capping pattern CP3. The first to third capping patterns CP1, CP2, and CP3 may be respectively disposed on the first to third cathodes CE1, CE2, and CE3, and respectively disposed within the first to third barrier rib opening portions OP1-P, OP2-P, and OP3-P.

[0185] In an exemplary embodiment, the dummy pattern DMP may include a plurality of first dummy patterns D1, a plurality of second dummy patterns D2, and a plurality of third dummy patterns D3.

[0186] The first dummy pattern D1 may include first to third dummy patterns D11, D12, and D13 respectively surrounding the first to third emission regions PXA-R, PXA-G, and PXA-B on a plane. The first to third dummy patterns D11, D12, and D13 may respectively include the same materials as the first to third emission patterns EP1, EP2, and EP3, and may be respectively formed by the same processes as the first to third emission patterns EP1, EP2, and EP3.

[0187] The second dummy pattern D2 may include first to third dummy patterns D21, D22, and D23 respectively surrounding the first to third emission regions PXA-R, PXA-G, and PXA-B on a plane. The first to third dummy patterns D21, D22, and D23 may respectively include the same materials as the first to third cathodes CE1, CE2, and CE3, and may be respectively formed by the same processes as the first to third cathodes CE1, CE2, and CE3.

[0188] The third dummy pattern D3 may include first to third dummy patterns D31, D32, and D33 respectively surrounding the first to third emission regions PXA-R, PXA-G, and PXA-B on a plane. The first to third dummy patterns D31, D32, and D33 may respectively include the same materials as the first to third capping patterns CP1, CP2, and CP3, and may be respectively formed by the same processes as the first to third capping patterns CP1, CP2, and CP3.

[0189] The first to third dummy opening portions OP1-D, OP2-D, and OP3-D corresponding to the first to third emission opening portions OP1-E, OP2-E, and OP3-E may be respectively defined in the dummy pattern DMP. Each of the first to third dummy opening portions OP1-D, OP2-D, and OP3-D may include first to third regions arranged in sequence in the third direction DR3. The first dummy opening portion OP1-D may be defined by the inner surfaces of the 1-1 dummy pattern D11, the 2-1 dummy pattern D21, and the 3-1 dummy pattern D31. The second dummy opening portion OP2-D may be defined by the inner surfaces of the 1-2 dummy pattern D12, the 2-2 dummy pattern D22, and the 3-2 dummy pattern D32. And the third dummy opening portion OP3-D may be defined by the inner surfaces of the 1-3 dummy pattern D13, the 2-3 dummy pattern D23, and the 3-3 dummy pattern D33.

[0190] The encapsulation layer TFE may include lower inorganic encapsulation patterns LIL1, LIL2, and LIL3, an organic encapsulation film OL, and an upper inorganic encapsulation film UIL. In an exemplary embodiment, the lower inorganic encapsulation patterns LIL1, LIL2, and LIL3 may include a first lower inorganic encapsulation pattern LIL1, a second lower inorganic encapsulation pattern LIL2, and a third lower inorganic encapsulation pattern LIL3. The first to third lower inorganic encapsulation patterns LIL1, LIL2, and LIL3 may respectively overlap with the first to third emission opening portions OP1-E, OP2-E, and OP3-E.

[0191] The first lower inorganic encapsulation pattern LIL1 may cover the first light-emitting element ED1 and the 1-1 dummy pattern D11, the 2-1 dummy pattern D21, and the 3-1 dummy pattern D31, and have a portion disposed inside the first isolation wall opening portion OP1-P. The second lower inorganic encapsulation pattern LIL2 may cover the second light-emitting element ED2 and the 1-2 dummy pattern D12, the 2-2 dummy pattern D22, and the 3-2 dummy pattern D32, and have a portion disposed inside the second isolation wall opening portion OP2-P. The third lower inorganic encapsulation pattern LIL3 may cover the third light-emitting element ED3 and the 1-3 dummy pattern D13, the 2-3 dummy pattern D23, and the 3-3 dummy pattern D33, and have a portion disposed inside the third isolation wall opening portion OP3-P. The first to third lower inorganic encapsulation patterns LIL1, LIL2, and LIL3 may be provided in the form of patterns spaced apart from each other.

[0192] Figure 6A A cross-sectional view of a display panel according to an embodiment supported by aspects of the present disclosure taken along Figure 4 line I-I' therein. Figure 6B A cross-sectional view of a display panel according to an embodiment supported by aspects of the present disclosure. Figure 6BA display panel according to an embodiment supported by various aspects of the present disclosure is provided along Figure 4 The cross-sectional view taken along the line II-II' in FIG. Figure 6A and Figure 6B A display panel according to an embodiment supported by various aspects of the present disclosure is described. Figures 5A to 5D The same / similar components to the described components are denoted by the same / similar reference numerals or symbols, and the detailed description thereof is omitted.

[0193] refer to Figure 6A and Figure 6B In the display panel DP according to an embodiment supported by various aspects of the present disclosure, the fifth insulating layer 50-1 may include a plurality of films. In an exemplary embodiment, the fifth insulating layer 50-1 may include a lower film 50a and an upper film 50b. The lower film 50a may be provided to be completely flat, and the upper film 50b may be provided on the lower film 50a and have an inner surface IF-I defined by a penetration portion. A portion of the top surface BF-I of the lower film 50a may be exposed by the inner surface IF-I defined in the upper film 50b. The inner surface IF-I of the upper film 50b and the top surface BF-I of the lower film 50a exposed by the inner surface IF-I may define the groove HP of the fifth insulating layer 50-1. The groove HP may provide a space in which the anode AE ​​and the sacrificial pattern SP may be provided. The anode AE ​​may be provided on the top surface BF-I of the lower film 50a exposed by the inner surface IF-I and the inner surface IF-I.

[0194] Exemplary aspects of methods and processes supported by various aspects of the present disclosure are described herein. In the descriptions of methods and processes herein, the operations may be performed in an order different from that shown and / or described, or may be performed in a different order or at a different time. Certain operations may also be removed, one or more operations may be repeated, or other operations may be added.

[0195] Figures 7A to 7Q 1 is a cross-sectional view illustrating some operations of a method for manufacturing a display panel according to an embodiment supported by various aspects of the present disclosure. Figures 7A to 7Q A method for manufacturing a display panel according to an embodiment supported by aspects of the present disclosure is described. The same / similar components as those described herein are denoted by the same / similar reference numerals or symbols, and detailed descriptions thereof are omitted.

[0196] A method for manufacturing a display panel according to an embodiment supported by aspects of the present disclosure may include: preparing a base layer, an emission region and a peripheral region adjacent to the emission region being defined in the base layer. The method may include forming an insulating layer on the base layer, a groove overlapping the emission region being defined in the insulating layer. The method may include forming an anode in the groove defined in the insulating layer. The method may include forming a pixel defining film on the insulating layer, an emission opening portion overlapping the anode being defined in the pixel defining film. The method may include forming a partition wall on the pixel defining film, a partition wall opening portion overlapping the emission opening portion being defined in the partition wall. The method may include forming an emission pattern including at least a part disposed in the emission opening portion, and forming a cathode including at least a part disposed in the partition wall opening portion, wherein the cathode contacts an inner surface of the partition wall defining the partition wall opening portion.

[0197] Reference Figure 7A , a method for manufacturing a display panel according to an embodiment supported by aspects of the present disclosure may include preparing a base layer BL. A method for manufacturing a display panel according to an embodiment supported by aspects of the present disclosure may further include forming a circuit element layer D-CL on the base layer BL.

[0198] The circuit element layer D-CL may be formed by a typical process for manufacturing circuit elements, the typical process forming an insulating layer, a semiconductor layer, and a conductive layer by coating or deposition, etc., and then selectively patterning the insulating layer, the semiconductor layer, and the conductive layer by a photolithography process and an etching process to form a semiconductor pattern, a conductive pattern, signal lines, etc. An anode AE may be formed on the circuit element layer D-CL. The anode AE may be formed using various methods such as, for example, a deposition process or a sputtering process.

[0199] Reference Figures 7A to 7C , a method for manufacturing a display panel according to an embodiment supported by aspects of the present disclosure may include forming an insulating layer 50 on the base layer BL, a groove HP being defined in the insulating layer 50. The formation of the insulating layer 50 may include forming a preliminary insulating layer P-50 on the base layer BL and patterning the preliminary insulating layer P-50.

[0200] The method may include forming a preliminary insulating layer P-50 on the circuit element layer D-CL. The preliminary insulating layer P-50 may be formed on an insulating layer disposed on the uppermost side of the circuit element layer D-CL, for example, a fourth insulating layer 40 (see Figure 5A ). The preliminary insulating layer P-50 may be formed using various methods such as, for example, coating or deposition.

[0201] Reference Figure 7B and Figure 7C, the method may include patterning a preliminary insulating layer P-50 after the formation of the preliminary insulating layer P-50. The patterning of the preliminary insulating layer P-50 may include generating light and emitting the light onto the initial insulating layer P-50 (e.g., exposing the preliminary insulating layer P-50 to light) and developing the preliminary insulating layer P-50.

[0202] The method may include providing a mask MK on the preliminary insulating layer P-50 to pattern the preliminary insulating layer P-50. The mask MK may include a transmissive portion FA and a semi-transmissive portion HA. The method may include defining first to third mask opening portions OP1-M, OP2-M, and OP3-M corresponding to the transmissive portion FA in the mask MK. The position of each of the transmissive portion FA and the semi-transmissive portion HA in the mask MK may be changed according to the pattern formed by the preliminary insulating layer P-50 by using the mask MK. The mask MK may be a halftone mask including regions having different light transmittances in the mask MK.

[0203] The transmissive portion FA may be a region through which the light emitted on the mask MK passes. The semi-transmissive portion HA may be a region having a lower light transmittance than the transmissive portion FA. The shape of the preliminary insulating layer P-50 after patterning may be changed according to the level of the light transmitted to the preliminary insulating layer P-50.

[0204] The method may include disposing the mask MK on the preliminary insulating layer P-50, and the method may then include supplying light to the preliminary insulating layer P-50 to perform an exposure process on the preliminary insulating layer P-50. Due to the light passing through the transmissive portion FA of the mask MK in the supplied light, a first light amount per unit area may be supplied to the portion of the preliminary insulating layer P-50 overlapping with the transmissive portion FA. Additionally, due to the light passing through the semi-transmissive portion HA of the mask MK in the supplied light, a second light amount per unit area may be supplied to the portion of the preliminary insulating layer P-50 overlapping with the semi-transmissive portion HA. The second light amount may be less than the first light amount.

[0205] Thereafter, the method may include removing a part of the preliminary insulating layer P-50 by developing the preliminary insulating layer P-50. The chemical structure of the portion of the preliminary insulating layer P-50 overlapping with the transmissive portion FA of the mask MK may be changed due to the light passing through the transmissive portion FA and then dissolved and removed in a subsequently provided developer. That is, with respect to the portion of the preliminary insulating layer P-50 overlapping with the transmissive portion FA of the mask MK, the method may include removing this portion of the preliminary insulating layer P-50 to form a first insulating portion of the insulating layer 50. The first insulating portion may correspond to a groove HP formed by removing the preliminary insulating layer P-50.

[0206] The amount of light emitted onto the portion of the preliminary insulating layer P-50 overlapping with the semi-transmissive portion HA of the mask MK may be less than the amount of light emitted onto the portion of the preliminary insulating layer P-50 overlapping with the transmissive portion FA. Due to the light and developer passing through the semi-transmissive portion HA, the method may include removing a portion of the preliminary insulating layer P-50 in the thickness direction of the preliminary insulating layer P-50. The method may include removing the portion of the preliminary insulating layer P-50 overlapping with the semi-transmissive portion HA of the mask MK to form a second insulating portion of the insulating layer 50. Since the portion overlapping with the transmissive portion FA is exposed to a greater amount of light than the portion overlapping with the semi-transmissive portion HA, the amount removed from the portion overlapping with the transmissive portion FA may be greater than the amount removed from the portion overlapping with the semi-transmissive portion HA. Accordingly, the first insulating portion may have a thickness smaller than that of the second insulating portion. The insulating layer 50 may include a first insulating portion and a second insulating portion having different thicknesses. The first insulating portion may be formed such that the first insulating portion is recessed from the second insulating portion, and the thickness of the first insulating portion may be smaller than the thickness of the second insulating portion.

[0207] In the patterning of the preliminary insulating layer P-50, the method may include forming the insulating layer 50 in which a groove HP is defined by the preliminary insulating layer P-50. The method may include removing a region of the preliminary insulating layer P-50 to form the insulating layer 50 in which a groove HP is defined. For example, as Figure 7C illustrated, the method may include defining a first groove HP1 corresponding to a first mask opening portion OP1-M, a second groove HP2 corresponding to a second mask opening portion OP2-M, and a third groove HP3 corresponding to a third mask opening portion OP3-M in the insulating layer 50. The insulating layer 50 in which the groove HP (e.g., the first groove HP1, the second groove HP2, the third groove HP3) is defined may correspond to the fifth insulating layer 50 described herein (see Figure 5A ). Figure 5A )

[0208] A positive method of removing the portion of the preliminary insulating layer P-50 provided with light is described as a method for patterning the preliminary insulating layer P-50. However, the embodiments supported by the present disclosure are not limited thereto. For example, a negative method of removing the portion of the preliminary insulating layer P-50 not provided with light may be used to pattern the preliminary insulating layer P-50.

[0209] Reference Figure 7D, A method for manufacturing a display panel according to an embodiment supported by aspects of the present disclosure may include forming a conductive layer P-AE on an insulating layer 50, and the method may include forming a sacrificial layer P-SP on the conductive layer P-AE. Each of the conductive layer P-AE and the sacrificial layer P-SP may be formed on a base layer BL while filling grooves HP1, HP2, and HP3. Each of the conductive layer P-AE and the sacrificial layer P-SP may be formed to have an integral shape on the base layer BL. Each of the conductive layer P-AE and the sacrificial layer P-SP may be formed by a method of depositing a conductive material. For example, each of the conductive layer P-AE and the sacrificial layer P-SP may be formed by a sputtering process.

[0210] Reference Figure 7E and Figure 7F , A method for manufacturing a display panel according to an embodiment supported by aspects of the present disclosure may include patterning each of the conductive layer P-AE and the sacrificial layer P-SP.

[0211] First to third initial photoresist layers PR1-I, PR2-I, and PR3-I respectively corresponding to the first to third grooves HP1, HP2, and HP3 may be formed on the sacrificial layer P-SP. The first to third initial photoresist layers PR1-I, PR2-I, and PR3-I may respectively overlap the first to third grooves HP1, HP2, and HP3 in a plane. The first initial photoresist layer PR1-I may be formed to overlap the first groove HP1, the second initial photoresist layer PR2-I may be formed to overlap the second groove HP2, and the third initial photoresist layer PR3-I may be formed to overlap the third groove HP3.

[0212] Thereafter, the first to third initial photoresist layers PR1-I, PR2-I, and PR3-I may be used as masks to pattern the conductive layer P-AE and the sacrificial layer P-SP by etching. For example, the first to third initial photoresist layers PR1-I, PR2-I, and PR3-I may be used as masks to pattern the conductive layer P-AE and the sacrificial layer P-SP by wet etching. In the patterning of the conductive layer P-AE and the sacrificial layer P-SP, preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I may be formed from the sacrificial layer P-SP, and first to third anodes AE1, AE2, and AE3 may be formed from the conductive layer P-AE. As Figure 7FAs an example, a first anode AE1 and a first preliminary sacrificial pattern SP1-I stacked in sequence in a third direction DR3 may be formed in a first groove H1, a second anode AE2 and a second preliminary sacrificial pattern SP2-I stacked in sequence in the third direction DR3 may be formed in a second groove HP2, and a third anode AE3 and a third preliminary sacrificial pattern SP3-I stacked in sequence in the third direction DR3 may be formed in a third groove HP3. The first to third initial photoresist layers PR1-I, PR2-I, and PR3-I may be removed after patterning the conductive layer P-AE and the sacrificial layer P-SP.

[0213] Reference Figure 7G and Figure 7H , a method for manufacturing a display panel according to an embodiment supported by aspects of the present disclosure may include forming a preliminary pixel defining film P-PDL on an insulating layer 50 and patterning the preliminary pixel defining film P-PDL.

[0214] Reference Figure 7G , a preliminary pixel defining film P-PDL may be formed on the insulating layer 50. The preliminary pixel defining film P-PDL may be disposed on the insulating layer 50 and cover the first to third preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I and the first to third anodes AE1, AE2, and AE3. The preliminary pixel defining film P-PDL may be formed by a method of depositing an inorganic material. The inorganic material may be deposited on the insulating layer 50 to form the preliminary pixel defining film P-PDL on the insulating layer 50.

[0215] Then, the preliminary pixel defining film P-PDL may be patterned to form a pixel defining film PDL in which first to third emission opening portions OP1-E, OP2-E, and OP3-E respectively overlapping with the first to third anodes AE1, AE2, and AE3 are defined. The patterning of the preliminary pixel defining film P-PDL may be an operation of removing a part of the preliminary pixel defining film P-PDL by etching. For example, the patterning of the preliminary pixel defining film P-PDL may be performed by dry etching. A method such as etching may be used to remove regions of the preliminary pixel defining film P-PDL, thereby forming a pixel defining film PDL in which the first to third emission opening portions OP1-E, OP2-E, and OP3-E are defined. A first emission opening portion OP1-E corresponding to the first anode AE1, a second emission opening portion OP2-E corresponding to the second anode AE2, and a third emission opening portion OP3-E corresponding to the third anode AE3 may be defined in the pixel defining film PDL. Each of the first to third emission opening portions OP1-E, OP2-E, and OP3-E may expose a part of the top surface of the corresponding preliminary sacrificial pattern among the preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I. A part of the top surface of the first preliminary sacrificial pattern SP1-I may be exposed by the first emission opening portion OP1-E. A part of the top surface of the second preliminary sacrificial pattern SP2-I may be exposed by the second emission opening portion OP2-E. A part of the top surface of the third preliminary sacrificial pattern SP3-I may be exposed by the third emission opening portion OP3-E.

[0216] Reference Figure 7I , a method for manufacturing a display panel according to an embodiment supported by aspects of the present disclosure may include forming a preliminary partition wall P-PW on an insulating layer 50. The formation of the preliminary partition wall P-PW may include forming a first preliminary partition wall layer P-L1 on the pixel defining film PDL and forming a second preliminary partition wall layer P-L2 on the first preliminary partition wall layer P-L1.

[0217] The formation of the first preliminary partition wall layer P-L1 may be performed using a method of depositing a conductive material. In an exemplary embodiment, the conductive material for forming the first preliminary partition wall layer P-L1 may include a metal having a low resistance. For example, the conductive material for forming the first preliminary partition wall layer P-L1 may be gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), copper (Cu), or an alloy thereof. The conductive material for forming the first preliminary partition wall layer P-L1 may be aluminum (Al).

[0218] Thereafter, a second preliminary isolation wall layer P-L2 can be formed on the first preliminary isolation wall layer P-L1, thereby forming a preliminary isolation wall P-PW. The formation of the second preliminary isolation wall layer P-L2 can be carried out by a method of depositing a conductive material. In one embodiment, the conductive material for forming the second preliminary isolation wall layer P-L2 can include a metal material. For example, the conductive material for forming the second preliminary isolation wall layer P-L2 can be gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy thereof. The metal for forming the second preliminary isolation wall layer P-L2 can be different from the metal for forming the first preliminary isolation wall layer P-L1. The metal for forming the second preliminary isolation wall layer P-L2 can include, for example, titanium (Ti).

[0219] In one embodiment, the second preliminary isolation wall layer P-L2 may not include a metal material. The second preliminary isolation wall layer P-L2 can be formed of a silicon-based compound. For example, the second preliminary isolation wall layer P-L2 can include at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon oxynitride (SiO x N y ).

[0220] The preliminary isolation wall P-PW can include the first preliminary isolation wall layer P-L1 and the second preliminary isolation wall layer P-L2. The first preliminary isolation wall layer P-L1 can be formed to have an integral shape on the insulating layer 50. The second preliminary isolation wall layer P-L2 can be formed to have an integral shape on the insulating layer 50. Each of the first preliminary isolation wall layer P-L1 and the second preliminary isolation wall layer P-L2 can overlap with the grooves HP1, HP2, and HP3. Each of the first preliminary isolation wall layer P-L1 and the second preliminary isolation wall layer P-L2 can be formed to have a height difference between a portion overlapping with the grooves HP1, HP2, and HP3 and a portion not overlapping with the grooves HP1, HP2, and HP3 in the third direction DR3. Each of the first preliminary isolation wall layer P-L1 and the second preliminary isolation wall layer P-L2 can have a shape in which a region overlapping with each of the grooves HP1, HP2, and HP3 is recessed by the height difference with respect to the third direction DR3.

[0221] The first preliminary isolation wall layer P-L1 can be divided into a plurality of parts. The first preliminary isolation wall layer P-L1 can include a first preliminary isolation wall part, a second preliminary isolation wall part, and a third preliminary isolation wall part. The first preliminary isolation wall part is provided on the first insulating part of the insulating layer 50 and has a flat top surface. The second preliminary isolation wall part is provided on the second insulating part of the insulating layer 50 and has a flat top surface. The third preliminary isolation wall part connects the first preliminary isolation wall part to the second preliminary isolation wall part and is inclined at a predetermined angle along the inner surface of the groove HP defined in the insulating layer 50.

[0222] The second preliminary isolation wall layer P-L2 can be divided into multiple parts. The second preliminary isolation wall layer P-L2 can include a fourth preliminary isolation wall part, a fifth preliminary isolation wall part, and a sixth preliminary isolation wall part. The fourth preliminary isolation wall part is disposed on the first insulating part of the insulating layer 50 and has a flat top surface. The fifth preliminary isolation wall part is disposed on the second insulating part of the insulating layer 50 and has a flat top surface. The sixth preliminary isolation wall part connects the fourth preliminary isolation wall part to the fifth preliminary isolation wall part and is inclined at a predetermined angle along the inner surface of the groove HP defined in the insulating layer 50.

[0223] Reference Figure 7J and Figure 7K , a method of manufacturing a display panel according to an embodiment supported by aspects of the present disclosure may include etching a preliminary isolation wall P-PW to form an isolation wall PW in which isolation wall opening parts OP1-P, OP2-P, and OP3-P are defined. The formation of the isolation wall PW may include forming a first photoresist pattern PR1 on the preliminary isolation wall P-PW and etching the first preliminary isolation wall layer P-L1 and the second preliminary isolation wall layer P-L2.

[0224] Reference Figure 7J , a method of manufacturing a display panel according to an embodiment supported by aspects of the present disclosure may include forming a first photoresist pattern PR1 on the preliminary isolation wall P-PW. The first photoresist pattern PR1 can be formed by forming a preliminary photoresist layer on the preliminary isolation wall P-PW and then patterning the preliminary photoresist layer using a photomask. A light opening part OP-PR1 overlapping with the anode AE can be formed in the first photoresist pattern PR1 through a patterning process. The light opening part OP-PR1 can overlap with the first to third anodes AE1, AE2, and AE3.

[0225] The light opening part OP-PR1 can overlap with the first to third grooves HP1, HP2, and HP3 in a plane. The light opening part OP-PR1 defined in the first photoresist pattern PR1 can have a planar area smaller than the planar area of the lowest part of each of the grooves HP1, HP2, and HP3. That is, the planar area of the light opening part OP-PR1 defined in the first photoresist pattern PR1 can be smaller than the reference Figure 5AThe planar area of the second surface UF2-I of the fifth insulating layer 50 described is small. Thus, in the etching of the first preliminary barrier layer P-L1 and the second preliminary barrier layer P-L2, which will be described later herein, the portions of each of the first preliminary barrier layer P-L1 and the second preliminary barrier layer P-L2 provided in each of the grooves HP1, HP2, and HP3 can be retained after etching. The portion of the second preliminary barrier layer P-L2 retained after etching can form a terminal portion in the barrier wall PW.

[0226] Then, referring to Figure 7K , a method for manufacturing a display panel according to an embodiment supported by aspects of the present disclosure may include etching the first preliminary barrier layer P-L1 and the second preliminary barrier layer P-L2 to form the barrier wall PW from the preliminary barrier wall P-PW.

[0227] The etching of the preliminary barrier wall P-PW can be performed twice. The etching of the first preliminary barrier layer P-L1 and the second preliminary barrier layer P-L2 may include a first etching and a second etching.

[0228] The first etching of the first preliminary barrier layer P-L1 and the second preliminary barrier layer P-L2 can use the first photoresist pattern PR1 as a mask and include dry etching the first preliminary barrier layer P-L1 and the second preliminary barrier layer P-L2. The first dry etching according to one or more embodiments can be performed in an etching environment where the etching selectivity of the first preliminary barrier layer P-L1 and the second preliminary barrier layer P-L2 is substantially the same. The portions of each of the first preliminary barrier layer P-L1 and the second preliminary barrier layer P-L2 overlapping with the light opening portion OP-PR1 can be etched in the first dry etching. That is, a part of the first preliminary barrier portion of the first preliminary barrier layer P-L1 described with reference to Figure 7I can be removed in the first dry etching. Additionally, a part of the fourth preliminary barrier portion of the second preliminary barrier layer P-L2 described with reference to Figure 7I can be removed in the first dry etching.

[0229] Although not illustrated, since the portions of each of the first preliminary barrier layer P-L1 and the second preliminary barrier layer P-L2 overlapping with the light opening portion OP-PR1 are removed after the first dry etching, a preliminary barrier wall opening portion can be formed. Here, the inner surfaces of the first preliminary barrier layer P-L1 and the second preliminary barrier layer P-L2, each of which defines the preliminary barrier wall opening portion, can be substantially aligned with each other.

[0230] The secondary etching of the first preliminary isolation wall layer P-L1 can be performed after the primary etching of the first preliminary isolation wall layer P-L1 and the second preliminary isolation wall layer P-L2. The secondary etching of the first preliminary isolation wall layer P-L1 can use the first photoresist pattern PR1 as a mask and includes wet-etching the first preliminary isolation wall layer P-L1 to form isolation wall opening portions OP1-P, OP2-P, and OP3-P. In the present disclosure, the secondary etching of the first preliminary isolation wall layer P-L1 can be referred to as the "undercut etching process".

[0231] As Figure 7K illustrated, the first isolation wall layer L1 and the second isolation wall layer L2 can be formed in the secondary etching of the first preliminary isolation wall layer P-L1. The remaining portion of the first preliminary isolation wall portion and a part of the third preliminary isolation wall portion of the first preliminary isolation wall layer P-L1 described with reference to Figure 7I can be removed in the secondary etching of the first preliminary isolation wall layer P-L1. In the secondary etching of the first preliminary isolation wall layer P-L1, the second preliminary isolation wall layer P-L2 may not be etched or may be substantially unetched. In the secondary etching of the first preliminary isolation wall layer P-L1, since the first preliminary isolation wall layer P-L1 is selectively etched, the inner surface of the isolation wall PW can have an undercut shape in cross section. The end portion can be formed in the isolation wall PW by the portion of the second isolation wall layer L2 that protrudes from the first isolation wall layer L1 toward the center of the anodes AE.

[0232] The first isolation wall layer L1 can have a first inner surface S1-P that defines a partial region of each of the isolation wall opening portions OP1-P, OP2-P, and OP3-. The second isolation wall layer L2 can have a second inner surface S2-P that defines the remaining region of each of the isolation wall opening portions OP1-P, OP2-P, and OP3-. The second inner surface S2-P of the second isolation wall layer L2 can have a shape that protrudes from the first inner surface S1-P of the first isolation wall layer L1 toward the center of each of the anodes AE1, AE2, and AE3.

[0233] The secondary wet etching according to one or more embodiments may be performed in an etching environment where the etching selectivity difference between the first preliminary spacer layer P-L1 and the second preliminary spacer layer P-L2 is large. Accordingly, the inner surface of the spacer PW defining each of the spacer openings OP1-P, OP2-P, and OP3-P may have an undercut shape in cross section. Specifically, since the first spacer layer L1 has an etching rate higher than that of the second spacer layer L2 with respect to the etchant, the first spacer layer L1 may be etched more than the second spacer layer L2. Accordingly, the first inner surface S1-P of the first spacer layer L1 may be formed to be recessed inward from the second inner surface S2-P of the second spacer layer L2. The end portion may be formed in the spacer PW through a portion of the second spacer layer L2 protruding from the first spacer layer L1 toward the center of the anode AE.

[0234] Reference Figure 7K and Figure 7L , a method of manufacturing a display panel according to an embodiment supported by aspects of the present disclosure may include etching preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I.

[0235] The etching of the preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I may be performed using a wet etching method, or the preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I may be etched using the first photoresist pattern PR1 and the spacer PW as masks. Sacrificial openings OP1-S, OP2-S, and OP3-S overlapping the emission openings OP1-E, OP2-E, and OP3-E may be formed in the sacrificial patterns SP1, SP2, and SP3 formed by etching the preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I, respectively.

[0236] A method of manufacturing a display panel according to an embodiment supported by aspects of the present disclosure may further include additionally etching the pixel defining layer PDL before etching the preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I. The additional etching of the pixel defining layer PDL may be performed using a dry etching method, or the pixel defining layer PDL may be etched using the first photoresist pattern PR1 and the spacer PW as masks. A portion of the pixel defining layer PDL may be removed through the additional etching. However, the embodiments supported by the present disclosure are not limited thereto, and the additional etching of the pixel defining layer PDL may be omitted according to the conditions for the process.

[0237] The sacrificial patterns SP1, SP2, and SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. A first sacrificial opening portion OP1-S overlapping with the first emission opening portion OP1-E may be formed in the first sacrificial pattern SP1, a second sacrificial opening portion OP2-S overlapping with the second emission opening portion OP2-E may be formed in the second sacrificial pattern SP2, and a third sacrificial opening portion OP3-S overlapping with the third emission opening portion OP3-E may be formed in the third sacrificial pattern SP3. At least a part of the first anode AE1 may be exposed by the first sacrificial pattern SP1 and the pixel defining layer PDL through the first sacrificial opening portion OP1-S and the first emission opening portion OP1-E. At least a part of the second anode AE2 may be exposed by the second sacrificial pattern SP2 and the pixel defining layer PDL through the second sacrificial opening portion OP2-S and the second emission opening portion OP2-E. At least a part of the third anode AE3 may be exposed by the third sacrificial pattern SP3 and the pixel defining layer PDL through the third sacrificial opening portion OP3-S and the third emission opening portion OP3-E.

[0238] Etching of the sacrificial patterns SP1, SP2, and SP3 may be performed in an etching environment where the etching selectivity difference between the sacrificial patterns SP1, SP2, and SP3 and the anodes AE1, AE2, and AE3 is large, so that the anodes AE1, AE2, and AE3 can be prevented from being etched together. That is, the sacrificial patterns SP1, SP2, and SP3 having an etching rate higher than that of the anodes AE1, AE2, and AE3 may be disposed between the pixel defining layer PDL and the anodes AE1, AE2, and AE3, thereby preventing the anodes AE1, AE2, and AE3 from being etched and damaged together during etching.

[0239] Thereafter, referring to Figure 7M , a method for manufacturing a display panel according to an embodiment supported by various aspects of the present disclosure may include, after removing the first photoresist pattern PR1 (see Figure 7L ), forming a first light-emitting element ED1 by sequentially forming a first emission pattern EP1 and a first cathode CE1 on the first anode AE1 in the first isolation wall opening portion OP1-P. A method for manufacturing a display panel according to an embodiment supported by various aspects of the present disclosure may further include forming a first capping pattern CP1 on the first light-emitting element ED1. The first capping pattern CP1 may be formed to be disposed in the first isolation wall opening portion OP1-P.

[0240] The first preliminary dummy layer DMP-I may be formed on the partition wall PW when forming the first light-emitting element ED1. The first preliminary dummy layer DMP-I may be formed by the same process as the first light-emitting element ED1 and the first capping pattern CP1. The first preliminary dummy layer DMP-I may be formed on the partition wall PW and in the second partition wall opening portion OP2-P and the third partition wall opening portion OP3-P.

[0241] The first preliminary dummy layer DMP-I may include a first sub-dummy layer D1-I, a second sub-dummy layer D2-I, and a third sub-dummy layer D3-I. The first sub-dummy layer D1-I may be formed by the same process as the first emission pattern EP1, the second sub-dummy layer D2-I may be formed by the same process as the first cathode CE1, and the third sub-dummy layer D3-I may be formed by the same process as the first capping pattern CP1. The first preliminary dummy layer DMP-I may be formed to be separated from the first light-emitting element ED1 and the first capping pattern CP1 by the partition wall PW forming the end portion.

[0242] Then, referring to Figure 7N , a method of manufacturing a display panel according to an embodiment supported by aspects of the present disclosure may include forming a preliminary lower inorganic encapsulation pattern LIL-I covering the first light-emitting element ED1 after forming the first light-emitting element ED1.

[0243] The preliminary lower inorganic encapsulation pattern LIL-I may cover the first light-emitting element ED1 and cover the first preliminary dummy layer DMP-I. A part of the first preliminary dummy layer DMP-I may be disposed in the first partition wall opening portion OP1-P. The preliminary lower inorganic encapsulation pattern LIL-I may be in contact with the top surface of the first capping pattern CP1 and the top surface of the third sub-dummy layer D3-I.

[0244] Referring to Figure 7N and Figure 7O , a method of manufacturing a display panel according to an embodiment supported by aspects of the present disclosure may include patterning the preliminary lower inorganic encapsulation pattern LIL-I and the first preliminary dummy layer DMP-I. The patterning of the preliminary lower inorganic encapsulation pattern LIL-I and the first preliminary dummy layer DMP-I may include forming a second photoresist pattern PR2, patterning the preliminary lower inorganic encapsulation pattern LIL-I to form a lower inorganic encapsulation pattern LIL, and patterning the first preliminary dummy layer DMP-I to form a dummy pattern DMP1.

[0245] In the formation of the second photoresist pattern PR2, the second photoresist pattern PR2 can be formed by forming a second preliminary photoresist layer and then patterning the second preliminary photoresist layer using a photomask. The second photoresist pattern PR2 can be formed into a pattern shape corresponding to the first emission opening portion OP1-E through a patterning process.

[0246] In the patterning of the preliminary inorganic encapsulation pattern LIL-I, the preliminary inorganic encapsulation pattern LIL-I can be dry-etched to remove portions of the preliminary inorganic encapsulation pattern LIL-I that do not overlap with the second photoresist pattern PR2. That is, the preliminary inorganic encapsulation pattern LIL-I can be patterned to remove portions of the preliminary inorganic encapsulation pattern LIL-I that do not overlap with the first anode AE1. The first lower inorganic encapsulation pattern LIL1 overlapping with the first emission opening portion OP1-E can be formed from the patterned preliminary inorganic encapsulation pattern LIL-I.

[0247] In the patterning of the first preliminary dummy layer DMP-I, the first-1 dummy layer D1-I, the second-1 dummy layer D2-I, and the third-1 dummy layer D3-I can be dry-etched to remove portions of each of the first-1 dummy layer D1-I, the second-1 dummy layer D2-I, and the third-1 dummy layer D3-I that do not overlap with the second photoresist pattern PR2. That is, the first preliminary dummy layer DMP-I can be patterned to remove portions of each of the first-1 dummy layer D1-I, the second-1 dummy layer D2-I, and the third-1 dummy layer D3-I that do not overlap with the first anode AE1. The first-1 dummy pattern D11, the second-1 dummy pattern D21, and the third-1 dummy pattern D31 overlapping with the first emission opening portion OP1-E can be formed from the patterned first-1 dummy layer D1-I, second-1 dummy layer D2-I, and third-1 dummy layer D3-I, respectively. The first-1 dummy pattern D11, the second-1 dummy pattern D21, and the third-1 dummy pattern D31 can have a closed line shape in a plane surrounding the corresponding emission region PXA (see Figure 5A )

[0248] The patterning of the first preliminary dummy layer DMP-I can further include wet-etching the first-1 dummy layer D1-I, the second-1 dummy layer D2-I, and the third-1 dummy layer D3-I after the dry-etching of the first-1 dummy layer D1-I, the second-1 dummy layer D2-I, and the third-1 dummy layer D3-I.

[0249] The patterning of the first preliminary dummy layer DMP-I can be performed to remove the portions of the first preliminary dummy layer DMP-I that do not overlap with the first anode AE1. The first preliminary dummy layer DMP-I formed in the second spacer opening portion OP2-P and the third spacer opening portion OP3-P can be removed by a patterning process. Additionally, the first to third dummy layers D1-I, D2-I, and D3-I formed on the spacer PW and not overlapping with the first emission opening portion OP1-E can also be removed by a patterning process. The first emission pattern EP1 and the first cathode CE1 overlapping with the first emission opening portion OP1-E can be formed by the patterned first preliminary dummy layer DMP-I. After the patterning process, the first anode AE1, the first emission pattern EP1, and the first cathode CE1 formed in the first emission opening portion OP1-E and the first spacer opening portion OP1-P can constitute the first light-emitting element ED1.

[0250] Reference Figure 7P , a method for manufacturing a display panel according to an embodiment supported by aspects of the present disclosure may include forming a second light-emitting element ED2 and a third light-emitting element ED3. The second light-emitting element ED2 and the third light-emitting element ED3 may be sequentially formed after removing the second photoresist pattern PR2 (see Figure 7O ). The formation of the second light-emitting element ED2 and the third light-emitting element ED3 may be substantially the same as the formation of the first light-emitting element ED1 described in reference Figures 7M to 7O . Thus, a display panel DP including the first to third light-emitting elements ED1, ED2, and ED3, the first to third dummy patterns D1, D2, and D3, and the first to third lower inorganic encapsulation patterns LIL1, LIL2, and LIL3 respectively corresponding to the multiple emission regions PXA-R, PXA-G, and PXA-B illustrated in Figure 5D can be formed.

[0251] Thereafter, reference Figure 7Q , a method for manufacturing a display panel according to an embodiment supported by aspects of the present disclosure may include forming an organic encapsulation film OL on the inorganic encapsulation patterns LIL1, LIL2, and LIL3 and the spacer PW and forming an upper inorganic encapsulation film UIL on the organic encapsulation film OL. The organic encapsulation film OL and the upper inorganic encapsulation film UIL may be formed on the inorganic encapsulation patterns LIL1, LIL2, and LIL3, thereby completing the display panel DP including the encapsulation layer TFE.

[0252] Thus, a display panel DP including a base layer BL, a circuit element layer D-CL, an insulating layer 50, a display element layer D-OL, and an encapsulation layer TFE can be formed.

[0253] Figures 8A to 8DA cross-sectional view illustrating some operations of a method for manufacturing a display panel according to an embodiment supported by aspects of the present disclosure. Hereinafter, reference will be made to Figures 8A to 8D A method for manufacturing a display panel according to an embodiment supported by aspects of the present disclosure will be described. Components that are the same / similar as those described herein are denoted by the same / similar reference numerals or symbols, and their detailed descriptions are omitted.

[0254] When compared with the method for manufacturing a display panel described with reference to Figures 7A to 7Q the difference between the method for manufacturing a display panel illustrated in Figures 8A to 8D is that the insulating layer 50 has a double-layer structure.

[0255] Referring to Figure 8A , a method for manufacturing a display panel according to an embodiment supported by aspects of the present disclosure may include forming a preliminary insulating layer P-50 on a base layer BL. The formation of the preliminary insulating layer P-50 may include forming a preliminary lower film P-50a on the base layer BL and forming a preliminary upper film P-50b on the preliminary lower film P-50a. Each of the preliminary lower film P-50a and the preliminary upper film P-50b may be formed using various methods such as, for example, coating or deposition.

[0256] Referring to Figure 8B and Figure 8C , a method for manufacturing a display panel according to an embodiment supported by aspects of the present disclosure may include patterning the preliminary insulating layer P-50 to form an insulating layer 50 in which grooves HP are defined. The patterning of the preliminary insulating layer P-50 may be performed after the formation of the preliminary insulating layer P-50. The patterning of the preliminary insulating layer P-50 may include emitting light toward the preliminary upper film P-50b and developing the preliminary upper film P-50b. Thus, for example, the patterning of the preliminary insulating layer P-50 may include exposing the preliminary upper film P-50b to light by using a mask MK described herein.

[0257] A mask MK may be provided on the preliminary upper film P-50b to pattern the preliminary upper film P-50b. First to third mask opening portions OP1-M, OP2-M, and OP3-M may be defined in the mask MK used in the exposure process for the preliminary upper film P-50b. The mask MK may include a transmissive portion FA and a semi-transmissive portion HA. The transmissive portion FA may be a region overlapping with the first to third mask opening portions OP1-M, OP2-M, and OP3-M. Light in the supplied light that passes through the mask opening portions OP1-M, OP2-M, and OP3-M may be supplied to portions of the preliminary upper film P-50b that overlap with each of the mask opening portions OP1-M, OP2-M, and OP3-M. The semi-transmissive portion HA of the mask MK may block the supplied light. The light may not be supplied to portions of the preliminary upper film P-50b that overlap with the semi-transmissive portion HA.

[0258] Thereafter, the portions of the preliminary upper film P-50b overlapping with each of the mask opening portions OP1-M, OP2-M, and OP3-M can be removed by developing the preliminary upper film P-50b exposed to light. Thus, an insulating layer 50 can be formed in which first to third inner surfaces IF1-I, IF2-I, and IF3-I corresponding to the first to third mask opening portions OP1-M, OP2-M, and OP3-M are defined. The first to third inner surfaces IF1-I, IF2-I, and IF3-I can be formed by passing through the upper film 50b from the top surface to the bottom surface. A part of the top surface of the lower film 50a can be exposed by the first to third inner surfaces IF1-I, IF2-I, and IF3-I.

[0259] The insulating layer 50 in which the groove HP is defined can be formed during patterning of the preliminary insulating layer P-50. The insulating layer 50 can include a lower film 50a provided on the circuit element layer D-CL and having a uniform thickness, and an upper film 50b provided on the lower film 50a and in which the first to third inner surfaces IF1-I, IF2-I, and IF3-I are defined.

[0260] The first inner surface IF1-I of the upper film 50b and the top surface of the lower film 50a exposed by the first inner surface IF1-I can form the first groove HP1 of the insulating layer 50. The second inner surface IF2-I of the upper film 50b and the top surface of the lower film 50a exposed by the second inner surface IF2-I can form the second groove HP2 of the insulating layer 50. The third inner surface IF3-I of the upper film 50b and the top surface of the lower film 50a exposed by the third inner surface IF3-I can form the third groove HP3 of the insulating layer 50.

[0261] Reference Figure 8D , a method for manufacturing a display panel according to an embodiment supported by aspects of the present disclosure can include forming a conductive layer P-AE on the insulating layer 50 and forming a sacrificial layer P-SP on the conductive layer P-AE. Each of the conductive layer P-AE and the sacrificial layer P-SP can be formed on the base layer BL while filling the grooves HP1, HP2, and HP3. The method can include forming each of the conductive layer P-AE and the sacrificial layer P-SP to have an integral shape on the base layer BL. The method can include using a method of depositing a conductive material associated with the formation of each of the conductive layer P-AE and the sacrificial layer P-SP. For example, the method can include forming each of the conductive layer P-AE and the sacrificial layer P-SP by a sputtering process.

[0262] Thereafter, the method can include using reference Figure 7E and Figure 7FThe same techniques and methods described are used to form the base layer BL, the circuit element layer D-CL, the insulating layer 50, the first to third anodes AE1, AE2, and AE3, the first to third sacrificial patterns SP1, SP2, and SP3, the pixel defining layer PDL, the partition wall PW, the lower inorganic encapsulation pattern LIL, the organic encapsulation film OL, and the upper inorganic encapsulation film UIL, thereby forming Figure 6B the display panel DP illustrated in

[0263] According to an embodiment of a display panel supported by aspects in accordance with the present disclosure, an end portion of the partition wall may include a portion inclined at a predetermined angle, thereby preventing step coverage in which an organic material is deposited along a bottom surface of the end portion onto an inner surface of the partition wall, to improve the reliability of the display panel.

[0264] Embodiments of the present disclosure support one or more processes (methods, flowcharts) supported by the features and embodiments described herein. Descriptions of elements being "configurable", "formable", "stackable", "etchable", etc. include processes (methods, flowcharts) for configuring, forming, positioning, stacking, or modifying the elements, etc. in accordance with the exemplary aspects described herein.

[0265] Although embodiments supported by aspects of the present disclosure have been described, it should be understood that the exemplary aspects described herein should not be limited to these embodiments, and those of ordinary skill in the art may make various changes and modifications within the spirit and scope of the present disclosure as claimed hereinafter. Accordingly, the technical scope supported by aspects of the present disclosure is not limited to what is described in the detailed description of the specification, but rather should be determined by the claims.

Claims

1. A display panel, characterized in that: include: a base layer, an emission region and a peripheral region adjacent to the emission region being defined in the base layer; an insulating layer disposed on the base layer, and a groove overlapping the emission region is defined in the insulating layer; a pixel defining film disposed on the insulating layer, and an emission opening portion overlapping the groove is defined in the pixel defining film; a partition wall disposed on the pixel defining film, wherein a partition wall opening portion overlapping the emission opening portion is defined in the partition wall; and a light emitting element disposed in the partition wall opening, the light emitting element comprising an anode, an intermediate layer, and a cathode in contact with the partition wall, wherein the insulating layer includes an inner side surface defining the groove and inclined at a first angle relative to a top surface of the base layer, At least a portion of the partition wall has a shape extending along the inner side surface.

2. The display panel according to claim 1, characterized in that: The separation wall includes an end portion extending along the inner side surface and protruding toward a center of the anode.

3. The display panel according to claim 2, characterized in that: The terminal portion comprises: a first end portion extending along the inner side surface and inclined at a second angle relative to the top surface of the base layer; and a second end portion extending from the first end portion in a direction parallel to the top surface of the base layer, Wherein, the second angle is equal to the first angle.

4. The display panel according to claim 1, characterized in that: The isolation wall comprises: A first isolation wall layer disposed on the pixel definition film and in contact with the cathode; and A second barrier wall layer is disposed on the first barrier wall layer and includes an end portion protruding from an inner side surface of the first barrier wall layer.

5. The display panel according to claim 4, characterized in that: The second isolation wall layer comprises: a first portion overlapping the peripheral region and having a flat top surface; a second portion extending from the first portion along the inner side surface of the insulating layer; and a third portion extending from the second portion in a direction parallel to the top surface of the base layer, wherein a sub-portion of the second portion and a sub-portion of the third portion define the terminal portion, and The first isolation wall layer comprises: a first partition wall portion disposed between the first portion and the pixel defining film; and A second partition wall portion is provided between the second portion and the inner side surface of the insulating layer.

6. The display panel according to claim 2 or 4, characterized in that: The length of the terminal portion is 0.6 μm to 1.5 μm.

7. The display panel according to claim 1, characterized in that: At least a portion of the pixel definition film has a shape extending along the inner surface, and The display panel further includes a sacrificial pattern disposed in the groove and between the anode and the pixel defining film, and a sacrificial opening portion overlapping the emission opening portion is defined in the sacrificial pattern.

8. The display panel according to claim 1, characterized in that: The insulating layer further comprises a top surface, the top surface comprising: a first surface overlapping the peripheral region; and A second surface has a height difference with the first surface and defines the groove together with the inner side surface.

9. The display panel according to claim 1, characterized in that: The display panel further includes an encapsulation layer disposed on the light emitting element and including a plurality of thin films, wherein the encapsulation layer includes an inorganic encapsulation pattern, the inorganic encapsulation pattern covers the light emitting element and includes a portion in contact with the isolation wall, and The display panel further comprises: a first dummy pattern disposed on the partition wall and including the same material as an emission pattern included in the intermediate layer, wherein the first dummy pattern is spaced apart from the emission pattern; and A second dummy pattern is disposed on the first dummy pattern and includes a same material as the cathode, wherein the second dummy pattern is spaced apart from the cathode.

10. A display panel, characterized in that: include: a base layer, an emission region and a peripheral region adjacent to the emission region being defined in the base layer; an anode, disposed on the substrate layer; a pixel defining film exposing at least a portion of the anode and having an emission opening portion overlapping the emission region defined in the pixel defining film; a partition wall disposed on the pixel defining film, wherein a partition wall opening portion overlapping the emission opening portion is defined in the partition wall; an emission pattern disposed in the partition wall opening portion; and a cathode disposed in the partition wall opening portion and in contact with the partition wall, wherein the separator includes an end portion protruding toward the center of the anode, Wherein the terminal portion comprises: a first end portion inclined at a predetermined angle relative to a top surface of the base layer; and A second end portion extends from the first end portion in a direction parallel to the top surface of the base layer.

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