Flash memory BGA (Ball Grid Array) packaging structure

Abstract

The utility model discloses a flash memory BGA packaging structure, and relates to the technical field of chips, the flash memory BGA packaging structure comprises a substrate, the two sides of the top of the substrate are provided with bonding pads, and the bonding pads are provided with double channels; the flash memory chips are stacked in a step shape, are mounted on the two sides of the top of the substrate and are close to the edge positions of the bonding pads; the bonding wires are connected between the flash memory chips and the bonding pads on the same side; the protective layer covers the top of the substrate; and the plastic packaging adhesive is filled in a gap between the protective layer and the substrate. The beneficial effects of the utility model are that the high-speed transmission performance of the substrate is optimized, the packaging difficulty is simplified, and the cost is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of chips, and more specifically, to a four-channel flash memory BGA packaging substrate. Background Art

[0002] BGA (Ball Grid Array) is a ball grid array package, which makes an array of solder balls at the bottom of the package substrate as the I / O terminals of the circuit to be interconnected with a printed circuit board (PCB). Four-channel flash memory chips generally use BGA252 Ball, BGA272 Ball, BGA316 Ball, etc. It is mainly applied to highly integrated small-size storage products such as ultra-large-capacity server SSDs, M.2 2230 ultra-small-size SSDs, and CFexpress Cards.

[0003] The traditional four-channel BGA substrate ( Figure 1 ) adopts a method of separating 4 channels, with four rows of pads. When the substrate is etched by lead electroplating, most of the pads in at least one row of pads cannot simply pull out the leads, resulting in the remaining of the wire tails after etching, causing changes in the circuit length and affecting high-speed transmission.

[0004] Secondly, for the four rows of pads and the stepped stacking of chips, a part of the suspended space is too large, and dummy chips must be added for filling, increasing the packaging difficulty and cost. Content of the Utility Model

[0005] In order to overcome the deficiencies of the prior art, the utility model provides a flash memory BGA packaging structure, which solves the problems that the current four-channel BGA substrate affects the high-speed transmission of the substrate due to the remaining of the tail wires caused by the pad design, and increases the packaging difficulty and cost due to the chip stacking method, thereby optimizing the high-speed transmission performance of the substrate, simplifying the packaging difficulty, and reducing the cost.

[0006] The technical solution adopted by the utility model to solve its technical problems is: a flash memory BGA packaging structure, which is improved in that the flash memory BGA packaging structure includes:

[0007] A substrate, with pads provided on both sides of the top, and each pad is provided with a double channel;

[0008] Flash memory chips, stacked in a stepped manner, and installed on both sides of the top of the substrate, and close to the edge positions of the pads;

[0009] Bonding wires, connected between the flash memory chips and the pads on the same side;

[0010] A protective layer, covering the top of the substrate;

[0011] And plastic encapsulant, filling the gap between the protective layer and the substrate.

[0012] In the above structure, both of the dual channels are arranged in an IO adjacent layout.

[0013] In the above structure, the substrate includes a TOP layer, a GND layer, a POWER layer, and a BOTTOM layer, and the TOP layer, GND layer, POWER layer, and BOTTOM layer are arranged in sequence from the top to the bottom of the substrate.

[0014] In the above structure, the TOP layer and the BOTTOM layer are mesh-coated films; the GND layer and the POWER layer are solid-coated films.

[0015] In the above structure, a plurality of solder balls are provided on the BOTTOM layer, and the solder balls are arranged in an array.

[0016] In the above structure, isolated pads are distributed on the BOTTOM layer, and the isolated pads are pulled to the edge of the substrate by bonding wires for electroplating, and scribe lanes are etched at the edge of the substrate.

[0017] In the above structure, the length of the protective layer is adapted to the length of the substrate.

[0018] In the above structure, the height of the protective layer is slightly higher than the stacked height of the flash memory chips.

[0019] The beneficial effects of the present utility model are as follows: In this solution, double-row pads are designed on both sides of the substrate, and each row of pads is a dual channel, so as to form four-channel pads distributed on both sides of the substrate. This design can facilitate pulling all the pads to the edge of the substrate without wire tail residues; by stacking the flash memory chips in a stepped manner, dummy chips are not required, and the generation of air cavities and air holes can be greatly reduced during the injection of the encapsulating glue; thus, both the high-speed transmission performance of the substrate is optimized, the encapsulation difficulty is simplified, and the cost is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the overall structure of a flash BGA packaging structure of the present utility model;

[0021] Figure 2 It is a schematic diagram of the structure of the TOP layer of a flash BGA packaging structure of the present utility model;

[0022] Figure 3 It is a schematic diagram of the structure of the GND layer of a flash BGA packaging structure of the present utility model;

[0023] Figure 4 It is a schematic diagram of the structure of the POWER layer of a flash BGA packaging structure of the present utility model;

[0024] Figure 5It is a schematic diagram of the structure of the BOTTOM layer of a flash memory BGA package structure of the present utility model. Specific embodiments

[0025] The present utility model will be further described below in conjunction with the accompanying drawings and embodiments.

[0026] Hereinafter, the concept, specific structure and technical effects of the present utility model will be clearly and completely described in conjunction with the embodiments and the accompanying drawings to fully understand the purpose, features and effects of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments of the present utility model, other embodiments obtained by those skilled in the art without creative efforts shall fall within the scope of protection of the present utility model. In addition, all the connection / connection relationships involved in the patent do not simply refer to the direct connection of components, but refer to the more optimal connection structure that can be formed by adding or reducing connection accessories according to the specific implementation situation. Each technical feature in the creation of the present utility model can be combined interactively without conflicting with each other.

[0027] Refer to Figure 1 As shown, the present utility model discloses a flash memory BGA package structure, and the flash memory BGA package structure includes:

[0028] A substrate 1, with pads provided on both sides of the top, and each pad is provided with a double channel;

[0029] Flash memory chips 2, stacked in a stepped manner, and installed on both sides of the top of the substrate 1, and close to the edge position of the pads;

[0030] Bonding wires 3, connected between the flash memory chips 2 and the pads on the same side;

[0031] A protective layer 4, covering the top of the substrate 1;

[0032] And a plastic encapsulant 5, filled in the gap between the protective layer 4 and the substrate 1.

[0033] It should be noted that in this embodiment, the substrate 1 serves as the basic structure of the BGA package and is usually composed of multiple insulating materials and conductive layers. It provides electrical connections and mechanical support to ensure that the flash memory chips 2 can be firmly installed and enables effective connection with external circuits. Each row of pads is dual-channel to form four-channel pads distributed on both sides of the substrate 1. This design facilitates pulling out all the pads to the edge of the substrate 1 without wire tails remaining, thereby optimizing the high-speed transmission performance of the substrate 1. The flash memory chips 2 are the core components for storing data, and the flash memory chips 2 are stacked in a stepped manner, that is, multiple flash memory chips 2 are stacked together in a layered manner. This helps save space and increase the storage capacity. Compared with the existing flash BGA package structure, no dummy chips are required, and the generation of air cavities and pores can be significantly reduced during the injection of the encapsulant 5, thereby simplifying the packaging difficulty and reducing the cost. The bonding wires 3 are metal wires used to connect the flash memory chips 2 and the pads on the substrate 1, usually made of materials such as gold and copper, and are fixed on the chips and pads by thermal pressing or soldering. The design of the bonding wires 3 provides an electrical connection path to transfer the electrical signals of the flash memory chips 2 to the pads on the substrate 1, realizing signal transmission between the chips and the substrate 1. The protective layer 4 covers the top of the substrate 1, usually made of a protective material such as epoxy resin, and can be applied by coating, spraying, etc. The design of the protective layer 4 can protect the circuits and pads on the substrate 1 from environmental influences such as moisture, dust, and mechanical damage, enhancing the durability and reliability of the package. The encapsulant 5 is a filling material, usually epoxy resin or other plastic materials, which is injected into the gap between the protective layer 4 and the substrate 1 during the packaging process. It can provide additional protection to prevent moisture and contaminants from entering the package interior, and at the same time increase the mechanical strength of the structure.

[0034] Both of the dual-channels are arranged with IO adjacent to each other.

[0035] It should be noted that in this embodiment, the IO adjacent layout makes the pin connections closer, reduces the length of the signal transmission path, helps improve the signal transmission speed and quality, and the adjacent IO pins can reduce signal interference and electromagnetic interference, improving the reliability of data transmission.

[0036] Referring to Figures 2 - 5 As shown, the substrate 1 includes a TOP layer, a GND layer, a POWER layer, and a BOTTOM layer. The TOP layer, GND layer, POWER layer, and BOTTOM layer are arranged in sequence from the top to the bottom of the substrate 1.

[0037] It should be noted that in this embodiment, the TOP layer is the uppermost layer of the substrate 1, mainly used for arranging input / output (I / O) pins and signal lines. It is the key interface connecting the chip to the external circuit, and the signal lines and pads arranged on the TOP layer need to be carefully designed to ensure the quality and stability of signal transmission; the GND layer is a key layer in the substrate 1, responsible for providing electrical grounding, and the design of the GND layer usually includes a large-area grounding plane to reduce electromagnetic interference and ground potential difference. The existence of the grounding layer helps to suppress noise and improve signal integrity; the POWER layer is used for power distribution, providing stable voltage to the chip and other circuits. As the distribution layer of multiple power rails, the POWER layer needs to be designed to have sufficient current-carrying capacity and usually has low resistance and inductance to reduce power noise and voltage fluctuations; the BOTTOM layer is the bottom layer of the substrate 1, usually used for the reverse side of arranging signal lines or power lines, or for encapsulating the pads for external connection.

[0038] Referring to Figures 2 - 5 As shown, the TOP layer and the BOTTOM layer are mesh laminates; the GND layer and the POWER layer are solid laminates.

[0039] It should be noted that in this embodiment, the mesh laminates of the TOP layer and the BOTTOM layer are usually used for the wiring layer. They are composed of multiple conductive lines and less covering material, forming a grid-like pattern. This design helps to flexibly arrange signal lines and pads while reducing the use of materials; the solid laminates of the GND layer and the POWER layer cover the entire layer, forming a uniform conductive plane. This design helps to provide a stable electrical reference point, reduce resistance and inductance, and improve the efficiency of power supply and grounding.

[0040] The BOTTOM layer is provided with a number of solder balls, and the solder balls are arranged in an array.

[0041] It should be noted that in this example, solder balls are provided on the BOTTOM layer of the substrate 1 and these solder balls are arranged in an array, providing a stable electrical connection to ensure good contact between layers; and the solder balls can provide additional mechanical support to enhance the stability of the component; in addition, the solder balls help to evenly distribute and dissipate heat, improving the thermal management performance.

[0042] Isolated pads are distributed on the BOTTOM layer, and the isolated pads are pulled to the edge of the substrate 1 for electroplating through the bonding wire 3, and a scribe lane is etched at the edge of the substrate 1.

[0043] It should be noted that in this embodiment, the isolated pad (or "isolated solder joint") refers to a pad or solder joint in a printed circuit board (PCB) design that is not connected to other circuit parts. They may exist on the circuit board but are not connected to any other part of the circuit. The design of the isolated pad, as a contact point for circuit testing and debugging, can reserve positions that may be used to add new functions or components in the future. It also provides physical support or fixes certain components without participating in electrical connections. Additionally, it can electrically isolate certain areas to reduce interference or signal crosstalk. Electroplating on the edge of the substrate 1 is to create a conductive layer at the edge part of the PCB to ensure good conductivity between the pad and the edge of the substrate 1, thereby improving the reliability of the connection. Cutting track etching on the edge of the substrate 1 refers to the cut or etching path created on the edge of the PCB, which is used to define the shape of the PCB or cut components, and removes the unnecessary materials through chemical etching, leaving the required electroplated connections and electrical circuits. Since the pads in this solution are located on both sides of the substrate 1, no residual wire tails will be left after etching during the lead electroplating etching of the substrate 1, thus not affecting high-speed transmission, and optimizing the high-speed transmission performance of the substrate 1.

[0044] The length of the protective layer 4 is adapted to the length of the substrate 1.

[0045] It should be noted that in this embodiment, the length of the protective layer 4 being adapted to the length of the substrate 1 can make the covered area of the protective layer 4 fully match the size of the substrate 1, ensuring that the entire substrate 1 is protected.

[0046] The height of the protective layer 4 is slightly higher than the stacking height of the flash memory chips 2.

[0047] It should be noted that in this embodiment, the protective layer 4 being slightly higher than the stacking height of the flash memory chips 2 can ensure full coverage of the entire surface and edges of the chips, providing better physical protection against external mechanical impacts or other environmental factors that may damage the chips.

[0048] The above is a specific description of the preferred embodiment of the present invention, but the present invention is not limited to the described embodiment. Those skilled in the art can make various equivalent deformations or substitutions without departing from the spirit of the present invention, and these equivalent deformations or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A flash memory BGA packaging structure, characterized in that: The flash memory BGA packaging structure comprises: A substrate, with pads on both sides of the top, and the pads are provided with dual channels; The flash memory chips are stacked in a stepped manner and mounted on both sides of the top of the substrate and close to the edge of the pad; A bonding wire is connected between the flash memory chip and the pad on the same side; A protective layer, covering the top of the substrate; And the plastic sealant is filled in the gap between the protective layer and the substrate.

2. A flash memory BGA packaging structure according to claim 1, characterized in that: The dual channels are arranged in an IO adjacent manner.

3. A flash memory BGA packaging structure according to claim 1, characterized in that: The substrate comprises a TOP layer, a GND layer, a POWER layer and a BOTTOM layer, and the TOP layer, the GND layer, the POWER layer and the BOTTOM layer are arranged in sequence from the top to the bottom of the substrate.

4. A flash memory BGA packaging structure according to claim 3, characterized in that: The TOP layer and the BOTTOM layer are mesh films; the GND layer and the POWER layer are solid films.

5. A flash memory BGA packaging structure according to claim 4, characterized in that: The BOTTOM layer is provided with a plurality of solder balls, and the solder balls are distributed in an array.

6. A flash memory BGA packaging structure according to claim 5, characterized in that: The BOTTOM layer is distributed with isolated pads, which are pulled to the edge of the substrate through bonding wires for electroplating, and are etched at the edge of the substrate.

7. A flash memory BGA packaging structure according to claim 1, characterized in that: The length of the protective layer is adapted to the length of the substrate.

8. The flash memory BGA packaging structure according to claim 1, characterized in that: The height of the protection layer is slightly higher than the stacking height of the flash memory chips.

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