2.5 D packaging method and structure

Abstract

The invention discloses a 2.5 D packaging method and structure, and the method comprises the following steps: providing a glass slide, and preparing a rewiring layer on the glass slide; and providing a silicon adapter plate wafer, performing multi-chip integration on the silicon adapter plate wafer, integrally mounting the silicon adapter plate wafer on the rewiring layer, and finally performing bottom filling, plastic packaging and cutting to form a single packaging body. The rewiring layer is used for replacing a traditional organic carrier plate or substrate, dependence on the organic carrier plate or substrate can be eliminated, the packaging cost is reduced, and the risk that the carrier plate is out of stock is avoided; the thickness of a traditional ABF carrier plate for 2.5 D packaging is as high as 0.3-0.5 mm, while the thickness of the rewiring layer adopted by the invention is 1t; the packaging thickness can be obviously reduced, and the packaging body can be lightened, thinned and miniaturized; a two-time plastic packaging process is adopted, and the second-time plastic packaging is performed after the rewiring layer is mounted on the silicon adapter plate wafer, so that the protection on the periphery of the packaging structure is enhanced, and the reliability of a packaging body is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a 2.5D packaging method and structure. Background Art

[0002] The most classic 2.5D package can be divided into three layers: the chip on the top, the silicon interposer in the middle, and the organic substrate at the bottom. In recent years, organic substrates have been in short supply and expensive, posing a significant challenge for 2.5D packages, which rely heavily on them. The thickness of an organic substrate is proportional to the number of layers. Substrates used in 2.5D packages typically have 10 to 20 layers and can be as thick as 0.3-0.5mm, significantly hindering the overall thinness of the package. Summary of the Invention

[0003] In order to solve the technical problems existing in the prior art, the purpose of the present invention is to provide a 2.5D packaging method and structure.

[0004] In order to achieve the above-mentioned purpose and the above-mentioned technical effect, the technical solution adopted by the present invention is:

[0005] A 2.5D packaging method comprises the following steps:

[0006] Providing a glass slide and preparing a redistribution layer on the glass slide;

[0007] A silicon transfer board wafer is provided, and multi-chip integration is performed on the silicon transfer board wafer to obtain a multi-chip integrated silicon transfer board wafer structure, which is then mounted as a whole on a redistribution layer. Finally, bottom filling, plastic sealing, and cutting are performed to form a single package body.

[0008] Furthermore, the step of preparing a redistribution layer on a glass slide includes:

[0009] 1) forming a release layer on the surface of the glass slide;

[0010] 2) forming a metal anti-reflection layer on the surface of the release layer obtained in step 1);

[0011] 3) Preparing a redistribution layer on the surface of the metal anti-reflection layer obtained in step 2).

[0012] Furthermore, the redistribution layer includes multiple passivation layers and multiple metal circuit layers, which are alternately distributed, and a first metal micro-bump structure is formed on the surface of the redistribution layer.

[0013] Furthermore, a plurality of TSV copper pillar structures and a plurality of damascene circuit layers are provided on the silicon adapter plate wafer, and a second metal micro-bump structure is formed on the surface of the silicon adapter plate wafer.

[0014] Furthermore, the steps of performing multi-chip integration on the silicon interposer wafer include:

[0015] First, the side of the silicon transfer plate wafer with the second metal micro-bump structure is bonded to the first glass slide;

[0016] Then, a conductive structure is fabricated on the opposite side of the silicon adapter wafer and then bonded to the second glass slide;

[0017] Then, the first glass slide is removed to expose the second metal micro-bump structure on the surface of the silicon adapter wafer;

[0018] Then, a plurality of chips are mounted on the side of the silicon transfer board wafer with the second metal micro-bump structure and bottom-filled and plastic-sealed;

[0019] Finally, the second glass slide is removed to expose the conductive structure, thereby obtaining a multi-chip integrated silicon adapter wafer structure.

[0020] Furthermore, the side of the silicon adapter plate wafer with the second metal micro-bump structure is bonded to the first glass slide through a first temporary bonding layer, and the thickness of the first temporary bonding layer is 1-3 times the height of the second metal micro-bump structure.

[0021] Furthermore, the other side of the silicon adapter plate wafer is bonded to the second glass slide through a second temporary bonding adhesive layer, and the thickness of the second temporary bonding adhesive layer is 1-3 times the height of the conductive structure.

[0022] Furthermore, the step of mounting the multi-chip integrated silicon interposer wafer structure as a whole onto the redistribution layer includes:

[0023] The multi-chip integrated silicon adapter board wafer structure is cut into single pieces, and then mounted on the surface of the redistribution layer through a flip-chip welding process, and physical connection and signal interconnection are achieved through the conductive structure and the first metal bump structure on the surface of the redistribution layer.

[0024] Furthermore, after the bottom filling and molding are completed, the glass slide and the release layer and the metal anti-reflection layer thereon are removed to expose the redistribution layer, and then solder balls are set at specific positions of the exposed surface of the redistribution layer.

[0025] The present invention also discloses a 2.5D packaging structure prepared by a 2.5D packaging method, comprising a redistribution layer, wherein the redistribution layer comprises multiple passivation layers and multiple metal circuit layers, and the two are alternately distributed; a first metal micro-bump structure is arranged on the front of the redistribution layer, and a solder ball is arranged on the back of the redistribution layer; a multi-chip integrated silicon adapter plate wafer structure is mounted on the front of the redistribution layer through the first metal micro-bump structure and the conductive structure; the multi-chip integrated silicon adapter plate wafer structure is enclosed in a plastic package; the multi-chip integrated silicon adapter plate wafer structure comprises a silicon adapter plate wafer and a plurality of chips mounted thereon; a plurality of TSV copper pillar structures and a plurality of damascene circuit layers are arranged on the silicon adapter plate wafer; a second metal micro-bump structure is arranged on the surface of the silicon adapter plate wafer; and a plurality of chips are physically connected and electrically interconnected with the second metal micro-bump structure through a third metal micro-bump structure.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The present invention discloses a 2.5D packaging method and structure, which no longer requires the use of an organic substrate or a carrier. A redistribution layer is used to replace the traditional organic carrier or substrate, so that the packaging and testing factory can get rid of the dependence on the organic carrier or substrate of the ABF carrier factory, reduce the packaging cost, and avoid the risk of carrier shortages; the thickness of the ABF carrier used in traditional 2.5D packaging is as high as 0.3-0.5mm, while the redistribution layer thickness adopted in the present invention is less than 0.1mm, which can significantly reduce the packaging thickness and is conducive to the lightweight and miniaturization of the package body; a two-time plastic sealing process is adopted, and the second plastic sealing is after the silicon adapter wafer is mounted with the redistribution layer, which enhances the protection of the surrounding of the packaging structure and is conducive to improving the reliability of the package body; the wafer-level flip-chip process is used to replace the substrate flip-chip process, which can greatly improve production efficiency. The overall packaging method is reasonable, convenient, low-cost, and suitable for industrial promotion and use. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic structural diagram of step 1) of the present invention;

[0029] Figure 2 This is a schematic structural diagram of step 2) of the present invention;

[0030] Figure 3 This is a schematic structural diagram of step 3) of the present invention;

[0031] Figure 4 This is a schematic structural diagram of step 4) of the present invention;

[0032] Figure 5 This is a schematic structural diagram of step 5) of the present invention;

[0033] Figure 6This is a schematic structural diagram of step 6) of the present invention;

[0034] Figure 7 This is a schematic structural diagram of step 7) of the present invention;

[0035] Figure 8 This is a schematic structural diagram of step 8) of the present invention;

[0036] Figure 9 This is a schematic structural diagram of step 9) of the present invention;

[0037] Figure 10 This is a schematic structural diagram of step 10) of the present invention;

[0038] Figure 11 This is a schematic structural diagram of step 11) of the present invention;

[0039] Figure 12 This is a schematic structural diagram of step 12) of the present invention;

[0040] Figure 13 This is a schematic structural diagram of step 13) of the present invention;

[0041] Figure 14 This is a schematic structural diagram of step 14) of the present invention;

[0042] Figure 15 Schematic diagram of the structure of step 15) of the present invention. DETAILED DESCRIPTION

[0043] The present invention is described in detail below so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more precise definition of the protection scope of the present invention.

[0044] The following is a brief summary of one or more aspects to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceivable aspects and is neither intended to identify key or critical elements of all aspects nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that will be provided later.

[0045] like Figure 1-15 As shown, the present invention discloses a 2.5D packaging method, comprising the following steps:

[0046] A glass slide 1 is provided, and a redistribution layer 4 is prepared on the glass slide 1;

[0047] A silicon transfer board wafer 5 is provided, and multi-chip integration is performed on the silicon transfer board wafer 5 to obtain a multi-chip integrated silicon transfer board wafer structure, which is then mounted as a whole on the redistribution layer 4, and finally bottom filling, plastic sealing, marking, cutting, etc. are performed to form a single package body.

[0048] The present invention discloses a 2.5D packaging method, which specifically includes the following steps:

[0049] 1) If Figure 1 As shown, a release layer 2 is formed on the surface of a glass slide 1. The glass slide 1 is usually a circular slide. The release layer 2 usually contains a laser-sensitive material that decomposes after laser irradiation.

[0050] 2) If Figure 2 As shown, a metal anti-reflection layer 3 is sputtered on the surface of the release layer 2. The metal anti-reflection layer 3 is usually made of aluminum or titanium copper, and its function is to block the laser in the subsequent laser debonding process to prevent the laser from damaging the redistribution layer 4;

[0051] 3) If Figure 3 As shown, a redistribution layer 4 is then prepared using processes such as metal sputtering, photolithography, and electroplating. The redistribution layer 4 comprises alternating layers of passivation layers 41 and metal circuit layers 42. Passivation layers 41 are typically made of a photolithographically etchable polyimide material, while metal circuit layers 42 are typically copper circuits. A first metal micro-bump structure 43 is then formed on the surface of the redistribution layer 4. The first metal bump structure 43 is typically made of copper-nickel-gold or copper-nickel-tin-silver.

[0052] 4) If Figure 4 As shown, a silicon interposer wafer 5 is provided, on which a plurality of TSV copper pillar structures 51 and a plurality of damascene circuit layers 52 are provided. A second metal micro-bump structure 53 is provided at a specific position on the front surface of the silicon interposer wafer 5 by metal sputtering, photolithography, and electroplating processes. The second metal bump structure 53 is typically copper-nickel-gold or copper-nickel-tin-silver.

[0053] 5) If Figure 5 As shown, the front surface of the silicon transfer plate wafer 5 on which the second metal micro-bump structure 53 is provided is bonded to the first glass carrier 6 through a temporary bonding process. The two are bonded together through a first temporary bonding adhesive layer 7. The thickness of the first temporary bonding adhesive layer 7 is generally 1-3 times the height of the second metal micro-bump structure 53, and the material of the first temporary bonding adhesive layer 7 is generally laser-sensitive material.

[0054] 6) If Figure 6As shown, the back side of the silicon transfer board wafer 5 is subjected to back side copper exposure processing, which generally includes grinding, first chemical mechanical polishing, silicon etching, chemical vapor deposition and second chemical mechanical polishing, thereby exposing the TSV copper pillar structure 51 on the back side of the silicon transfer board wafer 5, and forming a conductive structure 8 at the position where the TSV copper pillar structure 51 is exposed, preferably a C4 metal bump. The process of forming the C4 metal bump generally includes sputtering a metal layer, photolithography patterning and electroplating the C4 metal bump.

[0055] 7) If Figure 7 As shown, the back side of the silicon interposer wafer 5 provided with the conductive structure 8 is bonded to the second glass slide 10 again, and the two are bonded together by a second temporary bonding adhesive layer 9. The thickness of the second temporary bonding adhesive layer 9 is usually 1-3 times the height of the C4 metal bump, and the material of the second temporary bonding adhesive layer 9 is usually laser-sensitive material.

[0056] 8) If Figure 8 As shown, the first glass carrier 6 bonded to the front surface of the silicon transfer plate wafer 5 is removed by a laser debonding process, and the first temporary bonding adhesive layer 7 is removed by a wet cleaning process or a plasma cleaning process to expose the second metal micro-bump structure 53 on the front surface of the silicon transfer plate wafer 5;

[0057] 9) If Figure 9 As shown, several chips 11 that need to be integrated and packaged are welded to the front of the silicon adapter board wafer 5 through a wafer-level flip-chip process, and the two are physically connected and electrically interconnected through a third metal micro-bump structure 111 pre-set on the surface of the chip 11 and a second metal micro-bump structure 53 pre-set on the front of the silicon adapter board wafer 5. The third metal micro-bump structure 111 is usually copper-nickel-tin-silver or copper-nickel-copper-tin-silver. There are usually multiple chips 11, at least 2, which can be SoC chips, HBM chips, IO chips and other types. Then, the front of the silicon adapter board wafer 5 is bottom-filled with a first bottom filling glue 12 and then plastic-sealed with a first plastic sealing material 13 to form effective protection for the chip 11;

[0058] 10) If Figure 10 As shown, the second glass carrier 10 on the back of the silicon transfer plate wafer 5 is removed by a laser debonding process, and the second temporary bonding layer 9 is removed by a wet cleaning process or a plasma cleaning process to expose the conductive structure 8;

[0059] 11) If Figure 11 As shown, the semi-finished product obtained in step 10) is cut into individual pieces and attached to the surface of the redistribution layer 4 by a flip-chip bonding process. The two are physically connected and signal interconnected through the conductive structure 8 on the back of the silicon adapter wafer 5 and the first metal bump structure 43 on the surface of the redistribution layer 4;

[0060] 12) If Figure 12 As shown, the redistribution layer 4 is then underfilled with a second underfill glue 14 and then sealed with a second plastic sealing material 15 to form a plastic sealing body to protect the silicon transfer board wafer 5 integrated with multiple chips 11 to form a reconstructed wafer;

[0061] 13) If Figure 13 As shown, the glass slide 1 is removed by a laser debonding process, and the release layer 2 is removed by wet cleaning or plasma cleaning to expose the metal anti-reflection layer 3;

[0062] 14) If Figure 14 As shown, the metal anti-reflection layer 3 is removed by a wet etching process to expose the back surface of the redistribution layer 4, and solder balls 16 are arranged at specific positions on the exposed surface of the redistribution layer 4;

[0063] 15) If Figure 15 As shown, the plastic cover of the reconstructed wafer is ground and thinned to expose the back side of the chip 11, and finally marked and cut to form a single package.

[0064] The present invention also discloses a 2.5D packaging structure prepared by a 2.5D packaging method, including a redistribution layer 4, the redistribution layer 4 including a multi-layer passivation layer 41 and a multi-layer metal circuit layer 42, and the two are alternately distributed, a first metal micro-bump structure 43 is provided on the front of the redistribution layer 4, and a solder ball 16 is provided on the back of the redistribution layer 4. The front of the redistribution layer 4 is mounted with a multi-chip integrated silicon adapter board wafer structure through the first metal micro-bump structure 43 and the conductive structure 8. The multi-chip integrated silicon adapter board wafer structure is encapsulated in a plastic package. The multi-chip integrated silicon adapter board wafer structure includes a silicon adapter board wafer 5 and several chips 11 mounted thereon, several TSV copper pillar structures 51 and several layers of Damascus circuit layers 52 are provided on the silicon adapter board wafer 5, a second metal micro-bump structure 53 is provided on the surface of the silicon adapter board wafer 5, and the several chips 11 are physically connected and electrically interconnected with the second metal micro-bump structure 53 through a third metal micro-bump structure 111.

[0065] Example 1

[0066] like Figure 1-15 As shown, a 2.5D packaging method includes the following steps:

[0067] 1) If Figure 1 As shown, a release layer 2 is formed on the surface of a glass slide 1. The glass slide 1 is a circular slide. The release layer 2 generally contains a laser-sensitive material that decomposes after laser irradiation.

[0068] 2) If Figure 2As shown, a metal anti-reflection layer 3 is sputtered on the surface of the release layer 2. The metal anti-reflection layer 3 is made of aluminum and is used to block the laser in the subsequent laser debonding process to prevent the laser from damaging the redistribution layer 4.

[0069] 3) If Figure 3 As shown, a redistribution layer 4 is then prepared using processes such as metal sputtering, photolithography, and electroplating. The redistribution layer 4 includes multiple layers of passivation layers 41 and multiple layers of metal circuit layers 42, which are alternately arranged. The passivation layers 41 are made of a photolithographic polyimide material, and the metal circuit layers 42 are made of copper circuits. A first metal micro-bump structure 43 is then formed on the surface of the redistribution layer 4. The first metal bump structure 43 is made of copper-nickel-gold.

[0070] 4) If Figure 4 As shown, a silicon transfer board wafer 5 is provided, on which a plurality of TSV copper pillar structures 51 and a plurality of damascene circuit layers 52 are provided. A second metal micro-bump structure 53 is provided at a specific position on the front surface of the silicon transfer board wafer 5 by metal sputtering, photolithography, and electroplating processes. The second metal bump structure 53 is made of copper-nickel-gold.

[0071] 5) If Figure 5 As shown, the front surface of the silicon transfer plate wafer 5 on which the second metal micro-bump structure 53 is provided is bonded to the first glass carrier 6 through a temporary bonding process. The two are bonded together through a first temporary bonding adhesive layer 7. The thickness of the first temporary bonding adhesive layer 7 is generally 1.5 times the height of the second metal micro-bump structure 53, and the material of the first temporary bonding adhesive layer 7 is generally laser-sensitive material.

[0072] 6) If Figure 6 As shown, the back side of the silicon transfer board wafer 5 is subjected to back side copper exposure processing, which generally includes grinding, first chemical mechanical polishing, silicon etching, chemical vapor deposition and second chemical mechanical polishing, thereby exposing the TSV copper pillar structure 51 on the back side of the silicon transfer board wafer 5, and forming a conductive structure 8 at the position where the TSV copper pillar structure 51 is exposed, which is actually a C4 metal bump. The process of forming the C4 metal bump generally includes sputtering a metal layer, photolithography patterning and electroplating the C4 metal bump.

[0073] 7) If Figure 7 As shown, the back side of the silicon interposer wafer 5 provided with the conductive structure 8 is bonded to the second glass slide 10 again, and the two are bonded together by a second temporary bonding adhesive layer 9. The thickness of the second temporary bonding adhesive layer 9 is generally 1.5 times the height of the C4 metal bump, and the material of the second temporary bonding adhesive layer 9 is generally laser-sensitive material.

[0074] 8) If Figure 8As shown, the first glass carrier 6 bonded to the front surface of the silicon transfer plate wafer 5 is removed by a laser debonding process, and the first temporary bonding adhesive layer 7 is removed by a wet cleaning process or a plasma cleaning process to expose the second metal micro-bump structure 53 on the front surface of the silicon transfer plate wafer 5;

[0075] 9) If Figure 9 As shown, multiple chips 11 that need to be integrated and packaged are welded to the front of the silicon adapter board wafer 5 through a wafer-level flip-chip process. The two are physically connected and electrically interconnected through a third metal micro-bump structure 111 pre-set on the surface of the chip 11 and a second metal micro-bump structure 53 pre-set on the front of the silicon adapter board wafer 5. The third metal micro-bump structure 111 is made of copper-nickel-tin-silver. The chip 11 can be a SoC chip, an HBM chip, an IO chip, etc. The front of the silicon adapter board wafer 5 is then bottom-filled with a first bottom filling glue 12 and then plastic-sealed with a first plastic sealing material 13 to form effective protection for the chip 11;

[0076] 10) If Figure 10 As shown, the second glass carrier 10 on the back of the silicon transfer plate wafer 5 is removed by a laser debonding process, and the second temporary bonding layer 9 is removed by a wet cleaning process to expose the conductive structure 8;

[0077] 11) If Figure 11 As shown, the semi-finished product obtained in step 10) is cut into individual pieces and attached to the surface of the redistribution layer 4 by a flip-chip bonding process. The two are physically connected and signal interconnected through the conductive structure 8 on the back of the silicon adapter wafer 5 and the first metal bump structure 43 on the surface of the redistribution layer 4;

[0078] 12) If Figure 12 As shown, the redistribution layer 4 is then underfilled with a second underfill glue 14 and then sealed with a second plastic sealing material 15 to form a plastic sealing body to protect the silicon transfer board wafer 5 integrated with multiple chips 11 to form a reconstructed wafer;

[0079] 13) If Figure 13 As shown, the glass slide 1 is removed by a laser debonding process, and the release layer 2 is removed by a wet cleaning process to expose the metal anti-reflection layer 3;

[0080] 14) If Figure 14 As shown, the metal anti-reflection layer 3 is removed by a wet etching process to expose the back surface of the redistribution layer 4, and solder balls 16 are arranged at specific positions on the exposed surface of the redistribution layer 4;

[0081] 15) If Figure 15 As shown, the plastic cover of the reconstructed wafer is ground and thinned to expose the back side of the chip 11, and finally marked and cut to form a single package.

[0082] A 2.5D packaging structure prepared by a 2.5D packaging method includes a redistribution layer 4, wherein the redistribution layer 4 includes multiple passivation layers 41 and multiple metal circuit layers 42, which are alternately distributed. A first metal micro-bump structure 43 is provided on the front of the redistribution layer 4, and a solder ball 16 is provided on the back of the redistribution layer 4. A multi-chip integrated silicon adapter plate wafer structure is mounted on the front of the redistribution layer 4 through the first metal micro-bump structure 43 and the conductive structure 8. The multi-chip integrated silicon adapter plate wafer structure is enclosed in a plastic package. The multi-chip integrated silicon adapter plate wafer structure includes a silicon adapter plate wafer 5 and several chips 11 mounted thereon. Several TSV copper pillar structures 51 and several layers of Damascus circuit layers 52 are provided on the silicon adapter plate wafer 5. A second metal micro-bump structure 53 is provided on the surface of the silicon adapter plate wafer 5. Several chips 11 are physically connected and electrically interconnected with the second metal micro-bump structure 53 through a third metal micro-bump structure 111.

[0083] Parts or structures not specifically described in the present invention may adopt existing technologies or existing products and will not be described in detail here.

[0084] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A 2.5D packaging method, characterized in that: The following steps are involved: Providing a glass slide and preparing a redistribution layer on the glass slide; A silicon transfer board wafer is provided, and multi-chip integration is performed on the silicon transfer board wafer to obtain a multi-chip integrated silicon transfer board wafer structure, which is then mounted as a whole on a redistribution layer. Finally, bottom filling, plastic sealing, and cutting are performed to form a single package body.

2. A 2.5D packaging method according to claim 1, characterized in that: The steps of preparing a redistribution layer on a glass slide include: 1) forming a release layer on the surface of the glass slide; 2) forming a metal anti-reflection layer on the surface of the release layer obtained in step 1); 3) Preparing a redistribution layer on the surface of the metal anti-reflection layer obtained in step 2).

3. The 2.5D packaging method according to claim 2, wherein: The redistribution layer includes multiple passivation layers and multiple metal circuit layers, which are alternately distributed. A first metal micro-bump structure is formed on the surface of the redistribution layer.

4. The 2.5D packaging method according to claim 1, wherein: A plurality of TSV copper pillar structures and a plurality of damascene circuit layers are arranged on the silicon adapter plate wafer, and a second metal micro-bump structure is formed on the surface of the silicon adapter plate wafer.

5. The 2.5D packaging method according to claim 1, wherein: The steps for multi-chip integration on a silicon interposer wafer include: First, the side of the silicon transfer plate wafer with the second metal micro-bump structure is bonded to the first glass slide; Then, a conductive structure is fabricated on the opposite side of the silicon adapter wafer and then bonded to the second glass slide; Then, the first glass slide is removed to expose the second metal micro-bump structure on the surface of the silicon adapter wafer; Then, a plurality of chips are mounted on the side of the silicon transfer board wafer with the second metal micro-bump structure and bottom-filled and plastic-sealed; Finally, the second glass slide is removed to expose the conductive structure, thereby obtaining a multi-chip integrated silicon adapter wafer structure.

6. The 2.5D packaging method according to claim 5, characterized in that: The side of the silicon adapter plate wafer with the second metal micro-bump structure is bonded to the first glass slide through a first temporary bonding layer, and the thickness of the first temporary bonding layer is 1-3 times the height of the second metal micro-bump structure.

7. The 2.5D packaging method according to claim 5, characterized in that: The other side of the silicon transfer plate wafer is bonded to the second glass slide through a second temporary bonding adhesive layer, and the thickness of the second temporary bonding adhesive layer is 1-3 times the height of the conductive structure.

8. The 2.5D packaging method according to claim 1, wherein: The steps of mounting the multi-chip integrated silicon interposer wafer structure onto the redistribution layer include: The multi-chip integrated silicon adapter board wafer structure is cut into single pieces, and then mounted on the surface of the redistribution layer through a flip-chip welding process, and physical connection and signal interconnection are achieved through the conductive structure and the first metal bump structure on the surface of the redistribution layer.

9. The 2.5D packaging method according to claim 1, wherein: After the bottom filling and molding are completed, the glass slide and the release layer and metal anti-reflective layer thereon are removed to expose the redistribution layer, and then solder balls are set at specific positions on the exposed surface of the redistribution layer.

10. The 2.5D packaging structure prepared by the 2.5D packaging method according to any one of claims 1 to 9, characterized in that: It includes a redistribution layer, which includes multiple passivation layers and multiple metal circuit layers, and the two are alternately distributed. A first metal micro-bump structure is arranged on the front of the redistribution layer, and a solder ball is arranged on the back of the redistribution layer. The front of the redistribution layer is mounted with a multi-chip integrated silicon adapter board wafer structure through the first metal micro-bump structure and the conductive structure. The multi-chip integrated silicon adapter board wafer structure is enclosed in a plastic package. The multi-chip integrated silicon adapter board wafer structure includes a silicon adapter board wafer and several chips mounted thereon. Several TSV copper pillar structures and several layers of Damascus circuit layers are arranged on the silicon adapter board wafer. A second metal micro-bump structure is arranged on the surface of the silicon adapter board wafer. Several chips are physically connected and electrically interconnected with the second metal micro-bump structure through a third metal micro-bump structure.

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