Stacked photoelectric sealing structure and packaging process thereof

Abstract

The invention belongs to the technical field of chip packaging, and particularly relates to a stacked photoelectric sealing structure and a packaging technology thereof, and the structure comprises a lead frame which comprises a substrate adhesive tape and four independent bonding pads disposed on the substrate adhesive tape; the first glass-based chip is arranged on the two bonding pads and is electrically connected with the two bonding pads; the two first silicon-based electric chips are electrically connected and are respectively arranged on the other two bonding pads; the second glass-based chip is stacked on the first glass-based chip; the second silicon-based electric chip is stacked on the two first silicon-based electric chips and is electrically connected with the two first silicon-based electric chips and the second glass-based chip; according to the stacked photoelectric combined packaging structure and the packaging process thereof, through the stacking design of the lead frame and the chip, the occupation of a transverse space is greatly reduced; and meanwhile, the packaging step is simplified by the epoxy resin plastic packaging process, and the manufacturing cost is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip packaging, and in particular relates to a stacked optoelectronic packaging structure and a packaging process thereof. Background Art

[0002] With the rapid development of global electronics, the demand for high-performance, low-power chips is growing. Optoelectronics-on-package technology, due to its unique advantages such as excellent thermal management, superior signal integrity, high miniaturization, and outstanding electrical performance, is rapidly emerging as a core technology in the semiconductor packaging field. Among them, stacked packaging technology, with its ability to significantly increase integration, has become a key development direction in the integrated packaging field.

[0003] However, traditional packaging processes typically package photonic and electronic components separately, creating independent optical and electrical chips. Surface mount technology (SMT) is then used to connect and integrate these different chips onto a single substrate. This packaging approach has drawbacks, including relatively low integration density and long interconnect lengths between chips, resulting in inefficient signal transmission and making it difficult to meet current demands for high-performance, high-density chip integration.

[0004] Therefore, in order to solve the above problems, it is necessary to design a stacked optoelectronic packaging structure and its packaging process. Summary of the Invention

[0005] The purpose of the present invention is to provide a stacked optoelectronic package structure and a packaging process thereof to solve the technical problems mentioned in the background technology.

[0006] In order to solve the above technical problems, the present invention provides a stacked optoelectronic sealing structure, comprising: The lead frame comprises: a base tape, and four independent pads arranged on the base tape; wherein The intervals between the four pads are cross-shaped; A first glass substrate chip is disposed on the two pads and electrically connected to the two pads; Two electrically connected first silicon-based electrical chips are respectively arranged on the other two pads; wherein The two first silicon-based electrical chips are electrically connected to corresponding pads respectively; a second glass base chip, stacked on the first glass base chip; A second silicon-based electric chip is stacked on the two first silicon-based electric chips and is electrically connected to the two first silicon-based electric chips and the second glass-based chip; The plastic packaging material cooperates with the base tape to cover each pad, the first glass-based chip, the second glass-based chip, the first silicon-based electric chip and the second silicon-based electric chip to form a plastic packaging body.

[0007] Furthermore, solder paste is provided between the first glass-based chip and the two pads and between the two first silicon-based electrical chips and the other two pads.

[0008] Furthermore, an optical adhesive is provided between the first glass substrate chip and the second glass substrate chip; Conductive glue is provided between the second silicon-based electric chip and the two first silicon-based electric chips.

[0009] Furthermore, at least one first gold wire is provided between the two first silicon-based electrical chips; The two first silicon-based electrical chips are electrically connected via a first gold wire.

[0010] Furthermore, at least one second gold wire is provided between the second silicon-based electric chip and the two first silicon-based electric chips and the second glass-based chip; wherein The second silicon-based electric chip is electrically connected to the two first silicon-based electric chips and the second glass-based chip via a second gold wire.

[0011] On the other hand, the present invention also provides a packaging process for a stacked optoelectronic package structure, comprising the following steps: S1. Pre-processing frame: Use steel mesh to print solder paste on the surface of the pad to obtain a pre-processing frame; S2. Chip mounting: flip-chip mounting the first glass-based chip onto two pads of the lead frame; Mounting the two first silicon-based electronic chips on the other two pads of the lead frame respectively in a face-mounted manner; S3, reflow soldering: reflow soldering the pads after mounting the first glass-based chip and the two first silicon-based electric chips to obtain the first layer of products; S4, stacking the second layer of chips: stacking the second glass base chip on the first glass base chip using optical adhesive; stacking a second silicon-based electric chip on the two first silicon-based electric chips using conductive adhesive; S5, bonding connection: electrically connecting the two first silicon-based electrical chips through a first gold wire; Bonding the second silicon-based electric chip to the second glass-based chip and the two first silicon-based electric chips respectively through second gold wires; S6, plastic encapsulation: plastic encapsulation material is used to encapsulate the lead frame to form a plastic encapsulation body; S7. Subsequent processing: removing the base tape from the lead frame after plastic encapsulation.

[0012] Furthermore, the step S7 further includes: S71, electroplating the pads exposed at the bottom of the plastic package body; S72. Laser printing is performed on the front side of the plastic package; S73, cutting a plurality of integrally plastic-sealed products; S74. Perform performance test on the single product after cutting.

[0013] The beneficial effects of the present invention are: (1) The present invention significantly reduces the lateral space occupied by the stacked design of the lead frame and the chip; at the same time, the epoxy resin molding process simplifies the packaging steps and reduces the manufacturing cost.

[0014] (2) The present invention adopts a vertical stacking structure to stack the first layer of chips (a first glass-based chip and two first silicon-based electric chips) and the second layer of chips (a second glass-based chip and a second silicon-based electric chip) in layers, and achieves close connection between the corresponding chips through optical glue and conductive glue, thereby significantly improving the packaging density.

[0015] (3) The present invention directly connects the two first silicon-based electrical chips through a first gold wire and directly connects the second silicon-based electrical chip with the two first silicon-based electrical chips and the second glass-based chip through a second gold wire, thereby shortening the electrical signal transmission path. At the same time, the optical properties of the glass-based chip are combined with the low light loss characteristics of the optical adhesive to optimize the optical signal transmission efficiency.

[0016] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description and the drawings.

[0017] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 is an exploded view of a preferred embodiment of the present invention as a whole; Figure 2 It is a three-dimensional diagram of a preferred embodiment of the present invention. Figure 1 ; Figure 3 It is a three-dimensional diagram of a preferred embodiment of the present invention. Figure 2 ; Figure 4 is a cross-sectional view of a preferred embodiment of the molding compound of the present invention; Figure 5 is a flow chart of a preferred embodiment of the packaging process of the present invention.

[0020] In the picture: Lead frame 1, base tape 101, pad 102; A first glass-based chip 2 , a first silicon-based electric chip 3 , a second glass-based chip 4 , a second silicon-based electric chip 5 , a plastic encapsulation material 6 , solder paste 7 , optical adhesive 8 , conductive adhesive 9 , a first gold wire 10 , and a second gold wire 11 . DETAILED DESCRIPTION

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention. Example 1

[0022] like Figures 1 to 4 As shown, this embodiment provides a stacked optoelectronic package structure, including: The lead frame 1 comprises: a base tape 101, four independent pads 102 arranged on the base tape 101; wherein the intervals between the four pads 102 are cross-shaped; a first glass substrate chip 2, arranged on two pads 102, and electrically connected to the two pads 102; two electrically connected first silicon-based electric chips 3, respectively arranged on the other two pads 102; wherein the two first silicon-based electric chips 3 are electrically connected to the corresponding pads 102; a second glass substrate chip 4, stacked on the first glass substrate chip 2; a second silicon-based electric chip 5, stacked on the two first silicon-based electric chips 3, and electrically connected to the two first silicon-based electric chips 3 and the second The glass-based chip 4 is electrically connected; the plastic encapsulation material 6 cooperates with the base tape 101 to cover each soldering pad 102, the first glass-based chip 2, the second glass-based chip 4, the first silicon-based electric chip 3 and the second silicon-based electric chip 5 to form a plastic encapsulation body; wherein the base tape 101 adopts but is not limited to polyimide material, which is used to fix and support the four soldering pads 102 to ensure the stable position of each chip and component during the packaging process; wherein the soldering pad 102 adopts bare copper material, and silver plating is the most preferred to provide conductivity and welding reliability; wherein the plastic encapsulation material 6 adopts but is not limited to epoxy resin, after forming the plastic encapsulation body, to protect the internal components from the influence of the external environment.

[0023] In this embodiment, the stacking design of the lead frame 1 and the chip is provided to greatly reduce the lateral space occupied; at the same time, the epoxy resin molding process simplifies the packaging steps and reduces the manufacturing cost.

[0024] Solder paste 7 is provided between the first glass-based chip 2 and the two solder pads 102, and between the two first silicon-based electric chips 3 and the other two solder pads 102. By providing the solder paste 7, the tin powder in the solder paste 7 will melt during the heating and reflow process, and form a reliable metal connection after cooling, so that the first glass-based chip 2 and the two first silicon-based electric chips 3 can achieve good electrical conduction with the corresponding solder pads 102, ensuring the stable transmission of electrical signals between the first glass-based chip 2 and the two first silicon-based electric chips 3 and the external circuit.

[0025] An optical glue 8 is provided between the first glass-based chip 2 and the second glass-based chip 4; a conductive glue 9 is provided between the second silicon-based electric chip 5 and the two first silicon-based electric chips 3; wherein the optical glue 8 is provided for stacking connection between the first glass-based chip 2 and the second glass-based chip 4, thereby ensuring optical performance while providing mechanical support; wherein the conductive glue 9 is provided for stacking connection between the first-layer first silicon-based electric chip 3 and the second-layer second silicon-based electric chip 5, thereby achieving electrical conductivity.

[0026] In this embodiment, by adopting a vertical stacking structure, the first layer of chips (first glass-based chip 2, two first silicon-based electric chips 3) and the second layer of chips (second glass-based chip 4, second silicon-based electric chip 5) are stacked in layers, and the corresponding chips are tightly connected through optical glue 8 and conductive glue 9, thereby significantly improving the packaging density.

[0027] At least one first gold wire 10 is provided between the two first silicon-based electric chips 3 ; wherein the two first silicon-based electric chips 3 are electrically connected via the first gold wire 10 .

[0028] At least one second gold wire 11 is provided between the second silicon-based electric chip 5 and the two first silicon-based electric chips 3 and the second glass-based chip 4; wherein the second silicon-based electric chip 5 is electrically connected to the two first silicon-based electric chips 3 and the second glass-based chip 4 through the second gold wire 11.

[0029] In this embodiment, the two first silicon-based electric chips 3 are directly connected by the first gold wire 10, and the second silicon-based electric chip 5 is directly connected to the two first silicon-based electric chips 3 and the second glass-based chip 4 by the second gold wire 11, thereby shortening the electric signal transmission path. At the same time, the optical properties of the glass-based chip are combined with the low light loss characteristics of the optical glue 8 to optimize the optical signal transmission efficiency. Example 2

[0030] like Figures 1 to 5 As shown, this embodiment also provides a packaging process for a stacked optoelectronic package structure, including the following steps: S1, pre-processing the frame: using a steel mesh to print solder paste 7 on the surface of the pad 102 to obtain a pre-processed frame; Select an appropriate steel mesh, design and customize it according to the size and layout of the pads 102, accurately cover the steel mesh on the surface of the pads 102 of the lead frame, use professional steel mesh printing equipment to evenly print solder paste 7 on the pads 102, and after printing is completed, use optical inspection equipment to check the printing quality to ensure that each pad is evenly covered with an appropriate amount of solder paste 7, and obtain a pre-treated qualified frame.

[0031] S2, chip mounting: flip-chip mounting the first glass-based chip 2 onto the two pads 102 of the lead frame 1; For the first glass substrate chip 2, a flip chip technology is adopted. A high-precision flip chip placement machine is used to precisely align the first glass substrate chip 2 with the two target pads 102 of the lead frame 1, ensuring that the electrodes on the chip are accurately aligned with the solder paste 7 on the pads 102, and then the chip is placed on the pads 102; Mount the two first silicon-based electric chips 3 on the other two pads 102 of the lead frame 1 in a face-mounted manner; For the two first silicon-based electric chips 3, a face-up mounting method is adopted. Using a face-up mounting machine, the two first silicon-based electric chips 3 are accurately placed on the other two pads 102 of the lead frame 1 to ensure good contact between the chip pins and the pads 102. During the entire mounting process, the chip position is monitored in real time by a machine vision system to ensure that the mounting accuracy is controlled within the allowable error range.

[0032] S3, reflow soldering: reflow soldering is performed on the solder pads 102 after the first glass-based chip 2 and the two first silicon-based electric chips 3 are mounted to obtain a first layer product; The lead frame 1 mounted with the first glass-based chip 2 and the two first silicon-based electric chips 3 is placed in the reflow soldering equipment. According to the characteristics of the solder paste 7 used, a suitable reflow soldering temperature curve is set to achieve good soldering between the chip and the solder pad 102. After the reflow soldering is completed, the soldering quality is checked to see if there are defects such as cold soldering and short circuits to obtain a qualified first-layer product.

[0033] S4, stacking the second layer of chips: using optical adhesive 8 to stack the second glass-based chip 4 on the first glass-based chip 2; using conductive adhesive 9 to stack the second silicon-based electric chip 5 on the two first silicon-based electric chips 3; Apply an appropriate amount of optical glue 8 evenly on the first glass-based chip 2, use high-precision dispensing equipment to control the amount of glue and the coating position, accurately align the second glass-based chip 4 with the first glass-based chip 2, and mount it on the optical glue 8 through a placement machine to ensure that the chips are tightly fitted and free of bubbles, and apply conductive glue 9 on the two first silicon-based electric chips 3 respectively. Use dispensing equipment to ensure a uniform amount of glue, and accurately place the second silicon-based electric chip 5 on the conductive glue 9 to achieve good electrical and physical connection with the two first silicon-based electric chips 3, completing the stacking of the second layer of chips.

[0034] S5, bonding connection: electrically connecting the two first silicon-based electrical chips 3 through the first gold wire 10; bonding the second silicon-based electrical chip 5 to the second glass-based chip 4 and the two first silicon-based electrical chips 3 through the second gold wire 11; A gold wire bonding machine is used for bonding operations. First, the two first silicon-based electrical chips 3 are electrically connected through the first gold wire 10. Then, the second silicon-based electrical chip 5 is bonded to the second glass-based chip 4 and the two first silicon-based electrical chips 3 through the second gold wire 11 to ensure the stability and reliability of signal transmission. After bonding is completed, the bonding quality of the gold wire is checked under a microscope to ensure that the gold wire has no problems such as cold solder joints and breakage.

[0035] S6, plastic encapsulation: plastic encapsulating the lead frame 1 with a plastic encapsulating material 6 to form a plastic encapsulating body; The transfer molding process is used for plastic encapsulation. Several lead frames 1 are placed in a plastic encapsulation mold. The design of the mold must ensure that the plastic encapsulation material 6 can evenly cover components such as chips, gold wires and pads. The plastic encapsulation material 6 is heated to a molten state and injected into the mold cavity by pressure to fill the entire area that needs to be plastic encapsulated. The plastic encapsulation material 6 is fully filled and solidified to form a complete and dense plastic encapsulation body to protect the internal chips and connection structures from the influence of the external environment.

[0036] S7 , subsequent processing: removing the base tape 101 from the plastic-sealed lead frame 1 .

[0037] The S7 further includes: S71, electroplating the pad 102 exposed at the bottom of the plastic package body; The base tape 101 in the plastic-encapsulated lead frame 1 is removed to expose the pad 102 exposed at the bottom of the plastic-encapsulated body. A layer of metal (such as tin, silver, etc.) is plated on the surface of the pad 102 using an electroplating process to enhance the conductivity and solderability of the pad 102 and improve the reliability of the connection with the external circuit.

[0038] S72. Laser printing is performed on the front side of the plastic package; Use laser equipment to print on the front of the plastic package to facilitate product identification, traceability and management.

[0039] S73, cutting a plurality of integrally plastic-sealed products; Using high-precision cutting equipment, several integrally plastic-sealed products are cut according to the preset cutting path and separated into individual products.

[0040] S74. Perform performance test on the single product after cutting; Comprehensive performance testing is performed on the cut single products, including electrical performance testing (such as conductivity, resistance, capacitance, etc.), optical performance testing (such as optical signal transmission efficiency, optical loss, etc.) and mechanical performance testing (such as impact resistance, vibration resistance, etc.). According to the product design specifications and quality standards, qualified products are screened out and unqualified products are eliminated to ensure that the quality and performance of the final product meet the requirements.

[0041] Regarding the specific structure and implementation process of the stacked optoelectronic sealing structure, please refer to the relevant discussion in Example 1 and will not be repeated here.

[0042] The various devices selected in this application (components whose specific structures are not described) are all universal standard parts or components known to those skilled in the art, and their structures and principles can be known to those skilled in the art through technical manuals or conventional experimental methods.

[0043] In the description of the embodiments of the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0044] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0045] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. There may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed may be through some communication interface, indirect coupling or communication connection of devices or units, which may be electrical, mechanical or other forms.

[0046] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0047] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0048] With the above-described preferred embodiments of the present invention as a guide, and with reference to the above description, relevant personnel are fully capable of making various changes and modifications without departing from the technical scope of this invention. The technical scope of this invention is not limited to the contents of the specification and must be determined according to the scope of the claims.

Claims

1. A stacked optoelectronic sealing structure, characterized in that: include: A lead frame (1) comprising: a base tape (101), four independent pads (102) arranged on the base tape (101); wherein The intervals between the four welding pads (102) are in the form of a cross; A first glass substrate chip (2) is disposed on the two pads (102) and is electrically connected to the two pads (102); Two electrically connected first silicon-based electric chips (3) are respectively arranged on the other two pads (102); wherein The two first silicon-based electrical chips (3) are electrically connected to corresponding pads (102) respectively; A second glass base chip (4) stacked on the first glass base chip (2); A second silicon-based electric chip (5) is stacked on the two first silicon-based electric chips (3) and is electrically connected to the two first silicon-based electric chips (3) and the second glass-based chip (4); The plastic encapsulation material (6) cooperates with the base tape (101) to cover each pad (102), the first glass-based chip (2), the second glass-based chip (4), the first silicon-based electric chip (3) and the second silicon-based electric chip (5) to form a plastic encapsulation body.

2. The stacked optoelectronic sealing structure according to claim 1, wherein: Solder paste (7) is provided between the first glass-based chip (2) and the two solder pads (102), and between the two first silicon-based electrical chips (3) and the other two solder pads (102).

3. The stacked optoelectronic sealing structure according to claim 2, wherein: An optical glue (8) is provided between the first glass substrate chip (2) and the second glass substrate chip (4); Conductive glue (9) is provided between the second silicon-based electric chip (5) and the two first silicon-based electric chips (3).

4. The stacked optoelectronic sealing structure according to claim 3, wherein: At least one first gold wire (10) is provided between the two first silicon-based electric chips (3); wherein The two first silicon-based electrical chips (3) are electrically connected via a first gold wire (10).

5. The stacked optoelectronic sealing structure according to claim 4, wherein: At least one second gold wire (11) is provided between the second silicon-based electric chip (5) and the two first silicon-based electric chips (3) and the second glass-based chip (4); wherein The second silicon-based electric chip (5) is electrically connected to the two first silicon-based electric chips (3) and the second glass-based chip (4) via a second gold wire (11).

6. A packaging process based on the stacked optoelectronic package structure according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1, pre-processing frame: using a steel mesh to print solder paste (7) on the surface of the pad (102) to obtain a pre-processed frame; S2, chip mounting: flip-chip mounting the first glass-based chip (2) onto two pads (102) of the lead frame (1); Mounting the two first silicon-based electric chips (3) on the other two pads (102) of the lead frame (1) respectively in a face-on manner; S3, reflow soldering: reflow soldering the soldering pad (102) after mounting the first glass-based chip (2) and the two first silicon-based electric chips (3) to obtain a first layer product; S4, stacking the second layer of chips: stacking the second glass base chip (4) on the first glass base chip (2) using optical glue (8); stacking a second silicon-based electric chip (5) on the two first silicon-based electric chips (3) using a conductive adhesive (9); S5, bonding connection: electrically connecting the two first silicon-based electrical chips (3) via a first gold wire (10); The second silicon-based electric chip (5) is bonded to the second glass-based chip (4) and the two first silicon-based electric chips (3) respectively via second gold wires (11); S6, plastic encapsulation: plastic encapsulating the lead frame (1) with a plastic encapsulating material (6) to form a plastic encapsulating body; S7, subsequent processing: removing the base tape (101) from the lead frame (1) after plastic packaging.

7. The packaging process of the stacked optoelectronic package structure according to claim 6, characterized in that: The step S7 further includes: S71, electroplating the solder pad (102) exposed at the bottom of the plastic package body; S72. Laser printing is performed on the front side of the plastic package; S73, cutting a plurality of integrally plastic-sealed products; S74. Perform performance test on the single product after cutting.

Images