Safety response trigger circuit and safety response system

Abstract

The utility model relates to the technical field of electric driving, and provides a safety response trigger circuit and a safety response system. The safety response trigger circuit is used for a multi-drive system, and comprises a pulse conversion circuit which is configured to convert a rotating speed signal into a pulse signal; the pulse width comparison circuit is configured to generate a corresponding trigger signal according to the relationship between the frequency of the pulse signal and a frequency threshold; wherein the rotating speed signal is a rotating speed signal of a fault driving system of the multi-driving system, and the trigger signal is used for triggering the fault driving system to enter a corresponding safety state; and the signal latch circuit is configured to latch the received trigger signal and periodically output the latest trigger signal. According to the rotating speed signal of the fault driving system, the fault driving system is triggered to accurately enter a corresponding safety state, reverse torque and back electromotive force are avoided, the requirement that other driving work is not affected by faults of part of the driving systems is met, and the maximum driving advantage of the multi-driving system is achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of electric drive, and specifically, to a safety response trigger circuit and a safety response system. Background Art

[0002] For an electric vehicle configured with a multi-drive system, it has become an increasingly important requirement that the damage of some drive systems does not affect the operation of other drive systems.

[0003] In traditional electric drive technology, when some drive systems fail, the response of the whole vehicle is to decelerate and stop. Taking a dual-drive system as an example, when one drive system fails, the inverter of this drive system disconnects the relay connected to the high-voltage battery, and the relay connects the high-voltage battery to the inverters of the two drive systems. When the relay disconnects, the operation of the other drive system is affected, and the whole vehicle decelerates and stops. During this process, since the relay disconnects, the voltage on the high-voltage bus connected to the inverter and the high-voltage battery changes, and then the faulty drive system switches to different safety states according to the voltage on the high-voltage bus. Specifically, when the voltage on the high-voltage bus is relatively high, the faulty drive system enters the first safety state that can avoid back electromotive force; when the voltage on the high-voltage bus is relatively low, the faulty drive system enters the second safety state that can avoid reverse torque.

[0004] However, based on the requirement that the damage of some drive systems does not affect the operation of other drive systems, when a drive system fails, the relay does not disconnect, so that the drive system without faults can continue to work; at this time, the voltage on the high-voltage bus does not change, and then the faulty drive system cannot accurately switch to different safety states.

[0005] It should be noted that the information disclosed in the above background art part is only used to strengthen the understanding of the background of the utility model, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Utility Model

[0006] In view of this, the utility model provides a safety response trigger circuit and a safety response system, which can trigger the faulty drive system to accurately enter the corresponding safety state according to the rotational speed signal of the faulty drive system, avoid reverse torque and back electromotive force, meet the requirement that the failure of some drive systems does not affect the work of others, and enable the multi-drive system to exert the maximum driving advantage.

[0007] According to one aspect of the present utility model, a safety response trigger circuit for a multi-drive system is provided, including: a pulse conversion circuit configured to convert a rotational speed signal into a pulse signal; a pulse width comparison circuit connected to the pulse conversion circuit, the pulse width comparison circuit being configured to generate a corresponding trigger signal according to the relationship between the frequency of the pulse signal and a frequency threshold; wherein, the rotational speed signal is the rotational speed signal of a faulty drive system of the multi-drive system, and the trigger signal is used to trigger the faulty drive system to enter a corresponding safety state; a signal latch circuit connected to the pulse width comparison circuit, the signal latch circuit being configured to latch the received trigger signal and periodically output the latest trigger signal.

[0008] In some embodiments, the pulse conversion circuit includes: a first comparator, two input terminals of the first comparator respectively receiving the rotational speed signal and a first threshold signal, and an output terminal of the first comparator outputting the pulse signal.

[0009] In some embodiments, the first threshold signal is generated by a series connection node of two voltage dividing resistors connected in series to a power supply.

[0010] In some embodiments, the pulse width comparison circuit includes: a first integrated circuit chip connected between an output terminal of the pulse conversion circuit and an input terminal of the signal latch circuit; when the frequency of the pulse signal is respectively greater than and less than the frequency threshold, the first integrated circuit chip respectively outputs a first trigger signal for triggering the faulty drive system to enter a first safety state and a second trigger signal for triggering the faulty drive system to enter a second safety state.

[0011] In some embodiments, the pulse width comparison circuit further includes: a first charge and discharge circuit connected between an output terminal of the pulse conversion circuit and a threshold terminal of the first integrated circuit chip; when the frequency of the pulse signal is respectively greater than and less than the frequency threshold, the first charge and discharge circuit respectively charges and discharges, so that the voltage of the threshold terminal of the first integrated circuit chip is respectively greater than and less than a first control voltage, so that the first integrated circuit chip respectively outputs the first trigger signal and the second trigger signal.

[0012] In some embodiments, the first charge and discharge circuit includes: a first triode, the control end of the first triode is connected to the output end of the pulse conversion circuit; a first capacitor, which is connected in parallel between the input end and the output end of the first triode, the positive pole of the first capacitor is connected to the threshold end of the first integrated circuit chip and is connected to the power supply through at least one voltage dividing resistor, and the negative pole of the first capacitor is grounded; when the frequency of the pulse signal is greater than the frequency threshold, the first triode is cut off, and the first capacitor is charged, so that the voltage of the threshold end of the first integrated circuit chip is greater than the first control voltage; when the frequency of the pulse signal is less than the frequency threshold, the first triode is turned on, and the first capacitor is discharged, so that the voltage of the threshold end of the first integrated circuit chip is less than the first control voltage.

[0013] In some embodiments, the first integrated circuit chip is an NE555 time base integrated circuit, the trigger end of the NE555 time base integrated circuit is connected to the output end of the pulse conversion circuit, the output end of the NE555 time base integrated circuit is connected to the input end of the signal latching circuit, and the first control voltage is the voltage of the control end of the NE555 time base integrated circuit; when the voltage of the threshold end of the first integrated circuit chip is greater than the first control voltage, the first integrated circuit chip outputs the first trigger signal, and the first trigger signal is a constant voltage; when the voltage of the threshold end of the first integrated circuit chip is less than the first control voltage, the first integrated circuit chip outputs the second trigger signal, and the second trigger signal is the voltage of the trigger end of the NE555 time base integrated circuit.

[0014] In some embodiments, the first trigger signal is a constant voltage, and the second trigger signal is the pulse signal received by the first integrated circuit chip; the pulse width comparison circuit further includes: a constant voltage conversion circuit, which is connected between the output end of the first integrated circuit chip and the input end of the signal latching circuit, and the constant voltage conversion circuit is configured to convert the received constant voltage into a first trigger signal in a first constant voltage form and convert the received pulse signal into a second trigger signal in a second constant voltage form.

[0015] In some embodiments, the constant voltage conversion circuit includes: a second charge and discharge circuit, which is connected to the output end of the first integrated circuit chip; a second comparator, and two input ends of the second comparator are respectively connected to the second charge and discharge circuit and receive a second threshold signal; when the second charge and discharge circuit receives the constant voltage and the pulse signal respectively, the voltages output by the second charge and discharge circuit to the second comparator are greater than and less than the second threshold signal respectively, so that the second comparator outputs the first trigger signal in the first constant voltage form and the second trigger signal in the second constant voltage form respectively.

[0016] In some embodiments, the second charge and discharge circuit includes: a second triode, the control end of the second triode being connected to the output end of the first integrated circuit chip; a second capacitor, connected in parallel between the input end and the output end of the second triode, the positive electrode of the second capacitor being connected to the positive extreme end of the second comparator and connected to the power supply via a fifth voltage dividing resistor, and the negative electrode of the second capacitor being grounded; when the second charge and discharge circuit receives the constant voltage, the second triode remains cut-off, and the second capacitor remains charged, such that the voltage at the positive extreme end of the second comparator is greater than the second threshold signal, and the second comparator outputs the first trigger signal in the form of a first constant voltage; when the second charge and discharge circuit receives the pulse signal, the second triode conducts and cuts off, and the second capacitor discharges and charges, such that the voltage at the positive extreme end of the second comparator is less than the second threshold signal, and the second comparator outputs the second trigger signal in the form of a second constant voltage; wherein, the second constant voltage is less than the first constant voltage.

[0017] In some embodiments, a sixth voltage dividing resistor is connected in series between the control end of the second triode and the output end of the first integrated circuit chip, and / or, a seventh voltage dividing resistor is connected in parallel between the second capacitor and the second triode.

[0018] In some embodiments, the signal latching circuit includes: a second integrated circuit chip, connected to the output end of the pulse width comparison circuit, the second integrated circuit chip being configured to latch the received trigger signal and output the latest trigger signal based on the periodically generated activation signal.

[0019] In some embodiments, the second integrated circuit chip is a rising edge triggered D flip-flop, the set end of the rising edge triggered D flip-flop being connected to the output end of the pulse width comparison circuit, and the clock signal input end of the rising edge triggered D flip-flop receiving the activation signal, the activation signal being a rising edge signal.

[0020] In some embodiments, the activation signal is generated by a timing reset circuit, the timing reset circuit including: a third integrated circuit chip, connected to the second integrated circuit chip; a charge and discharge interlock circuit, connected to the threshold end of the third integrated circuit chip; as the charge and discharge interlock circuit operates, the voltage at the threshold end of the third integrated circuit chip and the second control voltage periodically satisfy a preset relationship, such that the third integrated circuit chip periodically outputs the activation signal.

[0021] In some embodiments, the charge-discharge interlock circuit includes: a third triode, the control end of the third triode is connected to the discharge end of the third integrated circuit chip, the input end of the third triode is connected to the power supply through an eighth voltage-dividing resistor, and the output end of the third triode is grounded; a fourth triode, the control end of the fourth triode is connected to the input end of the third triode, and the input end of the fourth triode is connected to the power supply; a third capacitor, the positive electrode of the third capacitor is connected to the threshold end of the third integrated circuit chip and the output end of the fourth triode, and is connected to the discharge end of the third integrated circuit chip through an eleventh voltage-dividing resistor, and the negative electrode of the third capacitor is grounded; wherein, the third triode and the fourth triode are alternately turned on, so that the voltage at the threshold end of the third integrated circuit chip and the second control voltage periodically satisfy the preset relationship.

[0022] In some embodiments, the third integrated circuit chip is an NE555 time-base integrated circuit, and the second control voltage is the voltage at the control end of the NE555 time-base integrated circuit; when the voltage at the threshold end of the third integrated circuit chip is greater than the second control voltage, the third integrated circuit chip outputs the activation signal.

[0023] In some embodiments, the discharge end of the third integrated circuit chip is connected to the power supply through a tenth voltage-dividing resistor, and / or, the positive electrode of the third capacitor is connected to the output end of the fourth triode through an eleventh voltage-dividing resistor.

[0024] According to another aspect of the present invention, there is provided a safety response system applied to a multi-drive system, including: a fault response module configured to obtain a rotational speed signal of a faulty drive system in response to a fault signal of the multi-drive system; a safety response trigger circuit as described in any of the above embodiments, the pulse conversion circuit of the safety response trigger circuit is connected to the fault response module, and the trigger signals output by the signal latch circuit of the safety response trigger circuit include a first trigger signal and a second trigger signal; a safety policy module configured to trigger the faulty drive system to enter a first safety state according to the first trigger signal, and trigger the faulty drive system to enter a second safety state according to the second trigger signal.

[0025] The beneficial effects of the present invention compared with the prior art at least include:

[0026] Through a pulse conversion circuit, the rotational speed signal of the fault drive system is converted into a pulse signal for subsequent quantization and comparison. To a certain extent, the rotational speed signal is determined by the voltage on the high-voltage bus connecting the inverter of the fault drive system to the high-voltage battery. Through a pulse width comparison circuit, the frequency of the pulse signal is compared with a frequency threshold. The frequency of the pulse signal reflects the voltage on the high-voltage bus to a certain extent, so that the generated trigger signal can trigger the fault drive system to accurately enter the corresponding safety state, avoiding reverse torque and back electromotive force. Through a signal latching circuit, the latest trigger signal is output periodically, preventing the safety response system that the trigger signal fluctuates frequently and causes the fault drive system / triggers the fault drive system to enter different safety states from getting stuck, and keeping the trigger signal stable within a reasonable period.

[0027] Thus, the safety response trigger circuit of the present utility model, through the cooperation of the pulse conversion circuit, the pulse width comparison circuit, and the signal latching circuit, realizes triggering the fault drive system to accurately enter the corresponding safety state according to the rotational speed signal of the fault drive system, avoiding reverse torque and back electromotive force, meeting the requirement that the failure of some drive systems does not affect the operation of other drives, and enabling the multi-drive system to exert the maximum driving advantage.

[0028] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present utility model. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present utility model, and are used together with the specification to explain the principles of the present utility model. Obviously, the following described drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0030] Figure 1 Showing a schematic diagram of the modules of the safety response trigger circuit in an embodiment of the present utility model;

[0031] Figure 2 Showing a schematic diagram of the pulse conversion circuit converting the rotational speed signal into a pulse signal in an embodiment of the present utility model;

[0032] Figure 3 Showing a schematic diagram of the signal latching circuit latching and outputting the trigger signal in an embodiment of the present utility model;

[0033] Figure 4 Showing a schematic diagram of the circuit structure of the pulse conversion circuit in an embodiment of the present utility model;

[0034] Figure 5 Showing a schematic diagram of the circuit structure of the generation circuit of the first threshold signal in an embodiment of the present utility model;

[0035] Figure 6 Schematic diagram showing the circuit structure of the pulse width comparison circuit in an embodiment of the present utility model;

[0036] Figure 7 Schematic diagram showing the circuit structure of the signal latching circuit in an embodiment of the present utility model;

[0037] Figure 8 Schematic diagram showing the module of the safety response system in an embodiment of the present utility model. Detailed implementation manners

[0038] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments described herein. On the contrary, these embodiments are provided to make the present utility model more complete and comprehensive, and to fully convey the concept of the example embodiments to those skilled in the art.

[0039] The accompanying drawings are only schematic illustrations of the present utility model and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repeated description will be omitted.

[0040] The terms "first", "second" and similar terms used in the detailed description do not denote any order, quantity or importance, but are only used to distinguish different components. In the description of the present utility model, it should be noted that when it is said that a device is "connected" to another device, this includes not only the case of direct connection, but also the case of indirect connection through other elements.

[0041] It should be noted that, without conflict, the features in the embodiments of the present utility model and those in different embodiments can be combined with each other.

[0042] Figure 1 Schematically shows the main circuit modules of the safety response trigger circuit, referring to Figure 1 As shown, the safety response trigger circuit provided in an embodiment of the present utility model for a multi-drive system includes a pulse conversion circuit 100, a pulse width comparison circuit 200, and a signal latching circuit 300.

[0043] The multi-drive system can be an automotive drive system including two or more drive systems such as a dual-drive system or a four-drive system.

[0044] The pulse conversion circuit 100 is configured to convert a rotational speed signal into a pulse signal. Among them, the rotational speed signal is the rotational speed signal of the faulty drive system of the multi-drive system. The rotational speed signal is an analog signal, and converting the rotational speed signal into a pulse signal facilitates subsequent quantization and comparison. To a certain extent, the rotational speed signal is determined by the voltage on the high-voltage bus connecting the inverter of the faulty drive system to the high-voltage battery.

[0045] Figure 2 It shows that the pulse conversion circuit converts the rotational speed signal into a pulse signal; combined with Figure 1 and Figure 2 as shown, through the pulse conversion circuit 100, the rotational speed signal 100a in the form of a sine wave is converted into a pulse signal 100b in the form of a square wave. Figure 2 In, the horizontal axis represents time and the vertical axis represents voltage.

[0046] The pulse width comparison circuit 200 is connected to the pulse conversion circuit 100 and is configured to generate a corresponding trigger signal according to the relationship between the frequency of the pulse signal and the frequency threshold. Among them, the trigger signal is used to trigger the fault drive system to enter the corresponding safe state. Through the pulse width comparison circuit 200, the frequency of the pulse signal is compared with the frequency threshold. To a certain extent, the frequency of the pulse signal reflects the voltage on the high-voltage bus, so that the generated trigger signal can trigger the fault drive system to accurately enter the corresponding safe state, avoiding reverse torque and back electromotive force.

[0047] Specifically, by setting the frequency threshold, when the frequency of the pulse signal is relatively large (indicating that the voltage on the high-voltage bus is relatively large), the trigger signal generated by the pulse width comparison circuit 200 is used to trigger the fault drive system to enter the first safe state that can avoid back electromotive force, and when the frequency of the pulse signal is relatively small (indicating that the voltage on the high-voltage bus is relatively small), the trigger signal generated by the pulse width comparison circuit 200 is used to trigger the fault drive system to enter the second safe state that can avoid reverse torque. For example, when the frequency of the pulse signal is greater than the frequency threshold, the pulse width comparison circuit 200 generates a high-level trigger signal; when the frequency of the pulse signal is less than the frequency threshold, the pulse width comparison circuit 200 generates a low-level trigger signal. Among them, in the description of the present invention, descriptions such as high level and low level, low voltage and high voltage are relative.

[0048] The signal latch circuit 300 is connected to the pulse width comparison circuit 200 and is configured to latch the received trigger signal and periodically output the latest trigger signal. Through the signal latch circuit 300, the latest trigger signal is periodically output, avoiding the safety response system that the trigger signal fluctuates frequently and causes the fault drive system / triggers the fault drive system to enter different safe states to get stuck, and making the trigger signal stable within a reasonable period.

[0049] Figure 3 It shows that the signal latch circuit latches and outputs the trigger signal, where the horizontal axis represents time and the vertical axis represents voltage. Combined with Figures 1 to 3As shown, the trigger signal 300a is continuously output to the signal latching circuit 300; in the first cycle T1, the signal latching circuit 300 outputs the latest received trigger signal 300a1 with a low level, in the second cycle T2, the signal latching circuit 300 outputs the latest received trigger signal 300a2 with a high level, in the third cycle T3, the signal latching circuit 300 outputs the latest received trigger signal 300a3 with a high level, and so on. Between two cycles, regardless of whether the received trigger signal 300a changes, the output of the signal latching circuit 300 remains the same as the trigger signal output in the previous cycle until a new trigger signal is output in the next cycle.

[0050] The safety response trigger circuit of the present utility model realizes triggering the faulty drive system to accurately enter the corresponding safety state according to the rotational speed signal of the faulty drive system through the cooperation of the pulse conversion circuit 100, the pulse width comparison circuit 200, and the signal latching circuit 300, avoids reverse torque and back electromotive force, meets the requirement that some drive system faults do not affect the operation of other drives, and enables the multi-drive system to exert the maximum driving advantage.

[0051] Figure 4 Schematically shows the circuit structure of the pulse conversion circuit; in combination with Figure 1 and Figure 4 As shown, in some embodiments, the pulse conversion circuit 100 includes: a first comparator U1, two input terminals of the first comparator U1 respectively receive the rotational speed signal VRPS and the first threshold signal Vth1, and the output terminal OUT1 of the first comparator U1 outputs a pulse signal.

[0052] Specifically, the first comparator U1 can receive the rotational speed signal VRPS through the positive input terminal and receive the first threshold signal Vth1 through the negative input terminal. When the voltage value of the rotational speed signal VRPS is greater than or equal to the voltage value of the first threshold signal Vth1, the output terminal OUT1 of the first comparator U1 outputs an effective pulse width. The schematic diagram of converting the rotational speed signal into a pulse signal can be referred to Figure 2 As shown; but not limited thereto, the first comparator U1 can also receive the rotational speed signal VRPS through the negative input terminal and receive the first threshold signal Vth1 through the positive input terminal.

[0053] The first comparator U1 can be an LT1716 comparator, but not limited thereto. The first comparator U1 is also connected to a power supply, and the power supply is, for example, 5V, but not limited thereto. Each circuit module of the safety response trigger circuit can be powered by this power supply.

[0054] In other embodiments, the pulse conversion circuit 100 can also be implemented by other circuit structures, for example, it can be implemented by circuit structures such as a Schmitt trigger, a single-chip microcomputer, etc.

[0055] In some embodiments, the first threshold signal Vth1 is determined according to the critical speed. The relationship between the rotational speed signal VRPS and the critical speed determines that the fault drive system enters the corresponding safe state. When the motor speed of the fault drive system characterized by the rotational speed signal VRPS is greater than or equal to the critical speed, the fault drive system needs to enter the first safe state that can avoid back electromotive force; when the motor speed of the fault drive system characterized by the rotational speed signal VRPS is less than or equal to the critical speed, the fault drive system needs to enter the second safe state that can avoid reverse torque. The critical speed can be determined according to the motor configuration of the fault drive system or obtained through measurement; for example, the critical speed can be 6000 revolutions per second, but not limited thereto. When determining the first threshold signal Vth1, the pulse signals converted from the rotational speed signals greater than and less than the critical speed need to have frequencies greater than and less than the frequency threshold respectively, so as to trigger the fault drive system to enter the first safe state and the second safe state respectively. When determining the first threshold signal Vth1, the corresponding frequency threshold can be determined first according to the critical speed, and then the first threshold signal Vth1 can be determined according to the frequency threshold.

[0056] When designing the circuit, the following formula can be used to simulate the rotational speed signal in the form of a sine wave: V = 2.4 + 1.5 * sin(6.283 * (Fs + (Fe - Fs) / te * time / 2) * time). Wherein, Fs = 0, Fe = 100, te = 10.

[0057] Figure 5 Schematically shows the circuit structure of the circuit for generating the first threshold signal; combined with Figure 4 and Figure 5 As shown, in some embodiments, the first threshold signal Vth1 is generated at the series node of two voltage-dividing resistors (including the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2) connected in series to the power supply. Among them, the resistance value of the first voltage-dividing resistor R1 can be 13 kΩ, and the resistance value of the second voltage-dividing resistor R2 can be 12 kΩ. The power supply is, for example, 5V as described above, but not limited thereto. By adjusting the resistance values of the first voltage-dividing resistor R1 and / or the second voltage-dividing resistor R2, the first threshold signal Vth1 can be adjusted.

[0058] Figure 6 Schematically shows the circuit structure of the pulse width comparison circuit; combined with Figure 1 、 Figure 4 and Figure 6As shown, in some embodiments, the pulse width comparison circuit 200 includes: a first integrated circuit chip U2 connected between the output terminal OUT1 of the pulse conversion circuit 100 and the input terminal of the signal latching circuit 300; when the frequency of the pulse signal PWM output from the output terminal OUT1 is greater than and less than the frequency threshold respectively, the first integrated circuit chip U2 outputs a first trigger signal for triggering the fault drive system to enter the first safety state and a second trigger signal for triggering the fault drive system to enter the second safety state respectively.

[0059] For example, when the frequency of the pulse signal PWM is greater than the frequency threshold, the first integrated circuit chip U2 outputs a first trigger signal; when the frequency of the pulse signal PWM is less than the frequency threshold, the first integrated circuit chip U2 outputs a second trigger signal; when the frequency of the pulse signal PWM is equal to the frequency threshold, according to the design requirements, the first integrated circuit chip U2 can output a first trigger signal or a second trigger signal.

[0060] The first integrated circuit chip U2 can adopt a suitable circuit structure such as a single-chip microcomputer to generate corresponding trigger signals according to the relationship between the frequency of the pulse signal PWM and the frequency threshold.

[0061] In some embodiments, the pulse width comparison circuit 200 further includes: a first charge and discharge circuit 210 connected between the output terminal OUT1 of the pulse conversion circuit 100 and the threshold terminal THRS of the first integrated circuit chip U2; when the frequency of the pulse signal PWM is greater than and less than the frequency threshold respectively, the first charge and discharge circuit 210 charges and discharges respectively, so that the voltage of the threshold terminal THRS of the first integrated circuit chip U2 is greater than and less than the first control voltage respectively, so that the first integrated circuit chip U2 outputs a first trigger signal and a second trigger signal respectively.

[0062] The first integrated circuit chip U2 is configured to output a first trigger signal or a second trigger signal according to the relationship between the voltage of its threshold terminal THRS and the first control voltage; for example, when the voltage of the threshold terminal THRS is greater than the first control voltage, the first integrated circuit chip U2 outputs a first trigger signal, when the voltage of the threshold terminal THRS is less than the first control voltage, the first integrated circuit chip U2 outputs a second trigger signal, when the voltage of the threshold terminal THRS is equal to the first control voltage, the first integrated circuit chip U2 can output a first trigger signal or a second trigger signal. Through the first charge and discharge circuit 210, charging and discharging are realized with the change of the relationship between the frequency of the pulse signal PWM and the frequency threshold, so as to change the voltage of the threshold terminal THRS of the first integrated circuit chip U2, and further change the trigger signal output by the first integrated circuit chip U2.

[0063] The specific circuit structure of the first charge and discharge circuit 210 and the internal structure of the first integrated circuit chip U2 can be designed as needed, as long as the first charge and discharge circuit 210 can switch the charge and discharge state according to the relationship between the frequency of the pulse signal PWM and the frequency threshold, so that the relationship between the voltage at the threshold terminal THRS of the first integrated circuit chip U2 and the first control voltage changes, and then the first integrated circuit chip U2 outputs a corresponding trigger signal.

[0064] In some embodiments, the first charge and discharge circuit 210 includes: a first triode Q1, the control end of the first triode Q1 is connected to the output end OUT1 of the pulse conversion circuit 100; a first capacitor C1, which is connected in parallel between the input end and the output end of the first triode Q1, the positive electrode of the first capacitor C1 is connected to the threshold terminal THRS of the first integrated circuit chip U2 and is connected to the power supply through at least one voltage dividing resistor, and the negative electrode of the first capacitor C1 is grounded; when the frequency of the pulse signal PWM is greater than the frequency threshold, the first triode Q1 is turned off, and the first capacitor C1 is charged, so that the voltage at the threshold terminal THRS of the first integrated circuit chip U2 is greater than the first control voltage; when the frequency of the pulse signal PWM is less than the frequency threshold, the first triode Q1 is turned on, and the first capacitor C1 is discharged, so that the voltage at the threshold terminal THRS of the first integrated circuit chip U2 is less than the first control voltage.

[0065] The first triode Q1 can be a suitable transistor such as a bipolar junction transistor (BJT) or a field effect transistor (FET); for example, the first triode Q1 can be a PNP type transistor, specifically a BC856B type transistor, but not limited thereto. The capacitance of the first capacitor C1 can be 100 nF, but not limited thereto. The positive electrode of the first capacitor C1 can be connected to the power supply through a third voltage dividing resistor R3 and a fourth voltage dividing resistor R4, and the resistance value of the third voltage dividing resistor R3 can be 100 kΩ, but not limited thereto.

[0066] In some embodiments, the first integrated circuit chip U2 is an NE555 timer integrated circuit. The trigger terminal TRIG of the NE555 timer integrated circuit is connected to the output end OUT1 of the pulse conversion circuit 100, the output end OUT of the NE555 timer integrated circuit is connected to the input end of the signal latch circuit 300, and the first control voltage is the voltage at the control terminal CV of the NE555 timer integrated circuit; when the voltage at the threshold terminal THRS of the first integrated circuit chip U2 is greater than or greater than or equal to the first control voltage, the first integrated circuit chip U2 outputs a first trigger signal, and the first trigger signal is a constant voltage signal Vcons; when the voltage at the threshold terminal THRS of the first integrated circuit chip U2 is less than or equal to or less than the first control voltage, the first integrated circuit chip U2 outputs a second trigger signal, and the second trigger signal is the voltage at the trigger terminal TRIG of the NE555 timer integrated circuit, that is, the pulse signal PWM output by the output end OUT1 of the pulse conversion circuit 100.

[0067] Referring to Figure 6 as shown, according to the configuration of the NE555 timer integrated circuit: when the voltage at the threshold terminal THRS is greater than / greater than or equal to the voltage at the control terminal CV, the output terminal OUT outputs a constant voltage signal Vcons, and the constant voltage signal Vcons is usually a constant high voltage; when the voltage at the threshold terminal THRS is less than or equal to / less than the voltage at the control terminal CV, the output terminal OUT outputs the voltage of the trigger terminal TRIG. Among them, the control terminal CV can be grounded through the fourth capacitor C4, and the capacitance of the fourth capacitor C4 can be 10 nF, but not limited thereto. In addition, the power supply terminal Vcc and the reset terminal RST of the NE555 timer integrated circuit are both connected to the power supply, the discharge terminal DIS is connected to the threshold terminal THRS, and the ground terminal GND is grounded.

[0068] In some embodiments, the first trigger signal is the constant voltage signal Vcons, and the second trigger signal is the pulse signal PWM received by the first integrated circuit chip U2; the pulse width comparison circuit 200 further includes: a constant voltage conversion circuit 220, connected between the output terminal OUT of the first integrated circuit chip U2 and the input terminal of the signal latch circuit 300, and the constant voltage conversion circuit 220 is configured to convert the received constant voltage signal Vcons into a first trigger signal Vtrig1 in a first constant voltage form, and convert the received pulse signal PWM into a second trigger signal Vtrig2 in a second constant voltage form.

[0069] The constant voltage conversion circuit 220 converts the constant voltage signal Vcons and the pulse signal PWM output by the first integrated circuit chip U2 into a first trigger signal Vtrig1 in a first constant voltage form and a second trigger signal Vtrig2 in a second constant voltage form respectively, where the first trigger signal Vtrig1 in the first constant voltage form is, for example, a constant high voltage, and the second trigger signal Vtrig2 in the second constant voltage form is, for example, a constant low voltage, so as to facilitate triggering the fault drive system into a first safe state that can avoid back electromotive force and a second safe state that can avoid reverse torque respectively.

[0070] The constant voltage conversion circuit 220 can achieve level conversion through capacitor filtering, a switching tube circuit, etc.

[0071] In some embodiments, the constant voltage conversion circuit 220 includes: a second charge-discharge circuit 220a connected to the output terminal OUT of the first integrated circuit chip U2; a second comparator U3, with two input terminals of the second comparator U3 respectively connected to the second charge-discharge circuit 220a and receiving a second threshold signal Vth2; when the second charge-discharge circuit 220a receives a constant voltage signal Vcons and a pulse signal PWM respectively, the voltages output by the second charge-discharge circuit 220a to the second comparator U3 are respectively greater than and less than the second threshold signal Vth2, so that the second comparator U3 outputs a first trigger signal Vtrig1 in a first constant voltage form and a second trigger signal Vtrig2 in a second constant voltage form.

[0072] The specific circuit structure of the second charge-discharge circuit 220a can be designed according to needs, as long as it can switch the charge-discharge state according to the constant voltage signal Vcons and the pulse signal PWM, so that the voltages output to the second comparator U3 are respectively greater than and less than the second threshold signal Vth2. The second comparator U3 can be connected to the second charge-discharge circuit 220a through the positive input terminal and receive the second threshold signal Vth2 through the negative input terminal, but not limited thereto. By adjusting the parameters of the second charge-discharge circuit 220a, the second comparator U3, and the second threshold signal Vth2, it is ensured that when the second charge-discharge circuit 220a receives the constant voltage signal Vcons, the voltage output to the second comparator U3 is greater than / greater than or equal to the second threshold signal Vth2, so that the second comparator U3 outputs a first trigger signal Vtrig1 in a first constant voltage form, and it is ensured that when the second charge-discharge circuit 220a receives the pulse signal PWM, the voltage output to the second comparator U3 is less than or equal to / less than the second threshold signal Vth2, so that the second comparator U3 outputs a second trigger signal Vtrig2 in a second constant voltage form.

[0073] The second comparator U3 can be an LT1716 comparator, but not limited thereto.

[0074] In some embodiments, the second charge and discharge circuit 220a includes: a second triode Q2, the control end of the second triode Q2 is connected to the output end OUT of the first integrated circuit chip U2; a second capacitor C2, which is connected in parallel between the input end and the output end of the second triode Q2, the positive pole of the second capacitor C2 is connected to the positive terminal of the second comparator U3 and is connected to the power supply through a fifth voltage dividing resistor R5, and the negative pole of the second capacitor C2 is grounded; when the second charge and discharge circuit 220a receives a constant voltage signal Vcons, the second triode Q2 remains cut-off, and the second capacitor C2 remains charged, so that the voltage at the positive terminal of the second comparator U3 is greater than the second threshold signal Vth2, and the second comparator U3 outputs a first trigger signal Vtrig1 in the form of a first constant voltage; when the second charge and discharge circuit 220a receives a pulse signal PWM, the second triode Q2 conducts and cuts off, and the second capacitor C2 discharges and charges, so that the voltage at the positive terminal of the second comparator U3 is less than the second threshold signal Vth2, and the second comparator U3 outputs a second trigger signal Vtrig2 in the form of a second constant voltage; wherein, the second constant voltage is less than the first constant voltage, the first trigger signal Vtrig1 in the form of the first constant voltage is a constant high voltage, and the second trigger signal Vtrig2 in the form of the second constant voltage is a constant low voltage.

[0075] The second triode Q2 can be a PNP type transistor, specifically, a 2N2907 type transistor, but not limited thereto. The capacitance of the second capacitor C2 can be 10 μF, and the resistance value of the fifth voltage dividing resistor R5 can be 100 kΩ, but not limited thereto.

[0076] Wherein, when the second charge and discharge circuit 220a receives the pulse signal PWM: when the pulse signal PWM is high, the second triode Q2 is cut off and the second capacitor C2 is charged; when the pulse signal PWM is low, the second triode Q2 conducts and the second capacitor C2 discharges; through the design of parameters such as the second triode Q2, the second capacitor C2, and the fifth voltage dividing resistor R5, the charging voltage of the second capacitor C2 under the action of the pulse signal PWM is always less than the second threshold signal Vth2, so the second comparator U3 outputs the second trigger signal Vtrig2 in the form of the second constant voltage.

[0077] In some embodiments, a sixth voltage dividing resistor R6 is connected in series between the control end of the second triode Q2 and the output end OUT of the first integrated circuit chip U2, and / or, a seventh voltage dividing resistor R7 is connected in parallel between the second capacitor C2 and the second triode Q2. The resistance value of the sixth voltage dividing resistor R6 can be 100 kΩ, and the resistance value of the seventh voltage dividing resistor R7 can be 110 kΩ, but not limited thereto.

[0078] Figure 7 Schematically shows the circuit structure of the signal latching circuit; in combination with Figure 1 、 Figure 6 and Figure 7As shown, in some embodiments, the signal latch circuit 300 includes: a second integrated circuit chip U4 connected to the output end of the pulse width comparison circuit 200. The second integrated circuit chip U4 is configured to latch the received trigger signals (including a first trigger signal Vtrig1 in a first constant voltage form and a second trigger signal Vtrig2 in a second constant voltage form), and output the latest trigger signal based on the periodically generated activation signal VCLK.

[0079] For the schematic of the second integrated circuit chip U4 latching and outputting the trigger signal, reference can be made to Figure 3 As shown, among them, the low-level trigger signal 300a1 output by the second integrated circuit chip U4 in the first cycle T1 and the third cycle T3 is the second trigger signal Vtrig2 in the second constant voltage form, and the high-level trigger signal 300a2 output in the second cycle T2 is the first trigger signal Vtrig1 in the first constant voltage form.

[0080] In some embodiments, the second integrated circuit chip U4 is a rising-edge triggered D flip-flop. The set terminal PRE of the rising-edge triggered D flip-flop is connected to the output end of the pulse width comparison circuit 200, and the clock signal input terminal CLK of the rising-edge triggered D flip-flop receives the activation signal VCLK, and the activation signal VCLK is a rising-edge signal.

[0081] In this way, the second integrated circuit chip U4 is enabled to latch the received trigger signals, and periodically output the latest received first trigger signal Vtrig1 in the first constant voltage form or the second trigger signal Vtrig2 in the second constant voltage form based on the activation signal VCLK, preventing the trigger signals from fluctuating frequently and causing the safety response system that drives the system / triggers the failure drive system to enter different safety states to get stuck, and keeping the trigger signals stable within a reasonable period.

[0082] Specifically, the second integrated circuit chip U4 can adopt a SN74HCS74D type flip-flop. Its power supply terminal VCC and clear terminal CLR are connected to the power supply, the data terminal Data and the ground terminal GND are grounded, and one of the two output terminals Q_N and Q can be selected to output the first trigger signal Vtrig1 in the first constant voltage form / the second trigger signal Vtrig2 in the second constant voltage form.

[0083] The activation signal VCLK can be periodically input externally. In some embodiments, the activation signal VCLK is generated by a timing reset circuit. Refer to Figure 7As shown, the timing reset circuit includes: a third integrated circuit chip U5 connected to the second integrated circuit chip U4; a charge-discharge interlock circuit 300b connected to the threshold terminal THRS of the third integrated circuit chip U5. As the charge-discharge interlock circuit 300b operates, the voltage of the threshold terminal THRS of the third integrated circuit chip U5 periodically satisfies a preset relationship with the second control voltage, causing the third integrated circuit chip U5 to periodically output an activation signal VCLK.

[0084] The charge-discharge interlock circuit 300b mainly consists of a switching transistor and a capacitor. After the charge-discharge interlock circuit 300b is powered on, it can alternately charge and discharge the capacitor through the conduction and cutoff of the switching transistor to periodically change the voltage of the threshold terminal THRS of the third integrated circuit chip U5, so that the voltage of the threshold terminal THRS of the third integrated circuit chip U5 periodically satisfies a preset relationship with the second control voltage. The third integrated circuit chip U5 can adopt a suitable circuit structure such as a single-chip microcomputer to output the activation signal VCLK at a set timing according to the relationship between the voltage of the threshold terminal THRS and the second control voltage.

[0085] In some embodiments, the charge-discharge interlock circuit 300b includes: a third triode Q3, the control terminal of the third triode Q3 is connected to the discharge terminal DIS of the third integrated circuit chip U5, the input terminal of the third triode Q3 is connected to the power supply through an eighth voltage-dividing resistor R8, and the output terminal of the third triode Q3 is grounded; a fourth triode M4, the control terminal of the fourth triode M4 is connected to the input terminal of the third triode Q3, and the input terminal of the fourth triode M4 is connected to the power supply; a third capacitor C3, the positive electrode of the third capacitor C3 is connected to the threshold terminal THRS of the third integrated circuit chip U5 and the output terminal of the fourth triode M4, and is connected to the discharge terminal DIS of the third integrated circuit chip U5 through a ninth voltage-dividing resistor R9, and the negative electrode of the third capacitor C3 is grounded. Among them, the third triode Q3 and the fourth triode M4 conduct alternately, so that the voltage of the threshold terminal THRS of the third integrated circuit chip U5 periodically satisfies a preset relationship with the second control voltage.

[0086] The third triode Q3 and the fourth triode M4 can adopt suitable transistors such as bipolar junction transistors (BJTs) and field-effect transistors (FETs). For example, the third triode Q3 can adopt an NPN triode, and the fourth triode M4 can adopt a PMOS transistor, specifically, an FDS4435A type transistor, but not limited thereto. The resistance value of the eighth voltage-dividing resistor R8 can be 1 kΩ, the resistance value of the ninth voltage-dividing resistor R9 can be 200 kΩ, and the capacitance of the third capacitor C3 can be 10 μF, but not limited thereto. The preset relationship can mean that the voltage of the threshold terminal THRS of the third integrated circuit chip U5 is greater than or greater than or equal to the second control voltage, but not limited thereto.

[0087] In a specific implementation: The initial voltage of the discharge terminal DIS of the third integrated circuit chip U5 is low; when the signal latch circuit 300 is powered on, the third triode Q3 is cut off, the fourth triode M4 is turned on, and the third capacitor C3 is charged, causing the voltages of the threshold terminal THRS and the discharge terminal DIS of the third integrated circuit chip U5 to rise; when the voltage of the discharge terminal DIS of the third integrated circuit chip U5 rises to cause the third triode Q3 to conduct, the fourth triode M4 is cut off, and the third capacitor C3 discharges, causing the voltage of the threshold terminal THRS of the third integrated circuit chip U5 to be greater than or greater than or equal to the second control voltage, so that the third integrated circuit chip U5 outputs an activation signal VCLK. The third capacitor C3 can achieve instantaneous discharge, causing the activation signal VCLK to appear in the form of a rising edge. Then, the voltage of the discharge terminal DIS of the third integrated circuit chip U5 is pulled low, and it returns to the state where the third triode Q3 is cut off and the fourth triode M4 is turned on. In this way, by cycling, the charge-discharge interlock circuit 300b controls the third integrated circuit chip U5 to periodically output the activation signal VCLK.

[0088] In some embodiments, the third integrated circuit chip U5 is an NE555 time-base integrated circuit, and the second control voltage is the voltage of the control terminal CV of the NE555 time-base integrated circuit; when the voltage of the threshold terminal THRS of the third integrated circuit chip U5 is greater than the second control voltage, the third integrated circuit chip U5 outputs an activation signal VCLK.

[0089] Refer to Figure 7 As shown, according to the configuration of the NE555 time-base integrated circuit: when the voltage of the threshold terminal THRS is greater than / greater than or equal to the voltage of the control terminal CV, the output terminal OUT outputs a rising-edge signal, that is, the activation signal VCLK; when the voltage of the threshold terminal THRS is less than or equal to / less than the voltage of the control terminal CV, the output terminal OUT outputs the voltage of the trigger terminal TRIG, and the voltage of the trigger terminal TRIG can be equal to the voltage of the threshold terminal THRS. Among them, the control terminal CV can be grounded through the fifth capacitor C5, and the capacitance of the fifth capacitor C5 can be 10 nF, but it is not limited thereto. In addition, the power supply terminal Vcc and the reset terminal RST of the NE555 time-base integrated circuit are both connected to the power supply, and the ground terminal GND is grounded.

[0090] In some embodiments, the discharge terminal DIS of the third integrated circuit chip U5 is connected to the power supply through the tenth voltage-dividing resistor R10, and / or, the positive electrode of the third capacitor C3 is connected to the output terminal of the fourth triode M4 through the eleventh voltage-dividing resistor R11. The resistance value of the tenth voltage-dividing resistor R10 can be 1 kΩ, and the resistance value of the eleventh voltage-dividing resistor R11 can be 10 Ω, but it is not limited thereto.

[0091] The embodiment of the present invention also provides a safety response system applied to a multi-drive system. Figure 8Schematically shows the main circuit modules of the safety response system, in combination with Figure 1 and Figure 8 As shown, the safety response system provided by the embodiment of the present invention includes:

[0092] A fault response module 810, configured to respond to a fault signal of a multi-drive system and obtain a rotational speed signal of the faulty drive system;

[0093] The safety response trigger circuit as described in any of the above embodiments, wherein the trigger signals output by the pulse conversion circuit 100 connected to the fault response module 810 and the signal latch circuit 300 include a first trigger signal (for example, a first trigger signal in the form of a first constant voltage) and a second trigger signal (for example, a second trigger signal in the form of a second constant voltage);

[0094] A safety policy module 830, configured to trigger the faulty drive system 860 to enter a first safety state according to the first trigger signal, and trigger the faulty drive system 860 to enter a second safety state according to the second trigger signal.

[0095] Wherein, the safety policy module 830 can directly control the faulty drive system 860 to enter the corresponding safety state; or, the safety policy module 830 can output corresponding safety policy signals according to the trigger signals, and then the subsequent safety logic circuit controls the faulty drive system 860 to enter the corresponding safety state according to the safety policy signals.

[0096] The safety response system of the present invention can automatically trigger the faulty drive system to accurately enter the corresponding safety state according to the rotational speed signal of the faulty drive system, avoid reverse torque and back electromotive force, meet the requirement that the failure of some drive systems does not affect the operation of other drives, and enable the multi-drive system to exert the maximum driving advantage.

[0097] The safety response system of the present invention is particularly applicable to a dual-drive system, and can realize that the failure of one drive system does not affect the normal operation of the other drive system, greatly improving the performance of the dual-drive system.

[0098] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A safety response trigger circuit for a multi-drive system, characterized in that, Comprising: A pulse conversion circuit configured to convert a rotational speed signal into a pulse signal; A pulse width comparison circuit connected to the pulse conversion circuit, the pulse width comparison circuit being configured to generate a corresponding trigger signal according to the relationship between the frequency of the pulse signal and a frequency threshold; Wherein, the rotational speed signal is the rotational speed signal of a faulty drive system of the multi-drive system, and the trigger signal is used to trigger the faulty drive system to enter a corresponding safe state; A signal latching circuit connected to the pulse width comparison circuit, the signal latching circuit being configured to latch the received trigger signal and periodically output the latest trigger signal.

2. The safety response trigger circuit according to claim 1, wherein The pulse conversion circuit includes: A first comparator, two input terminals of the first comparator respectively receive the rotational speed signal and a first threshold signal, and an output terminal of the first comparator outputs the pulse signal.

3. The safety response trigger circuit according to claim 2, wherein The first threshold signal is generated by a series connection node of two voltage dividing resistors connected in series to a power supply.

4. The safety response trigger circuit according to claim 1, characterized in that, The pulse width comparison circuit includes: A first integrated circuit chip connected between an output terminal of the pulse conversion circuit and an input terminal of the signal latching circuit; When the frequency of the pulse signal is respectively greater than and less than the frequency threshold, the first integrated circuit chip respectively outputs a first trigger signal for triggering the faulty drive system to enter a first safe state and a second trigger signal for triggering the faulty drive system to enter a second safe state.

5. The safety response trigger circuit according to claim 4, characterized in that, The pulse width comparison circuit further includes: A first charge and discharge circuit connected between an output terminal of the pulse conversion circuit and a threshold terminal of the first integrated circuit chip; When the frequency of the pulse signal is respectively greater than and less than the frequency threshold, the first charge and discharge circuit respectively charges and discharges, so that the voltage of the threshold terminal of the first integrated circuit chip is respectively greater than and less than a first control voltage, so that the first integrated circuit chip respectively outputs the first trigger signal and the second trigger signal.

6. The safety response trigger circuit according to claim 5, wherein The first charge and discharge circuit includes: A first triode, a control terminal of the first triode is connected to an output terminal of the pulse conversion circuit; A first capacitor, connected in parallel between an input terminal and an output terminal of the first triode, a positive electrode of the first capacitor is connected to the threshold terminal of the first integrated circuit chip and connected to a power supply through at least one voltage dividing resistor, and a negative electrode of the first capacitor is grounded; When the frequency of the pulse signal is greater than the frequency threshold, the first triode is cut off, and the first capacitor is charged, so that the voltage of the threshold terminal of the first integrated circuit chip is greater than the first control voltage; When the frequency of the pulse signal is less than the frequency threshold, the first triode is turned on, and the first capacitor is discharged, so that the voltage of the threshold terminal of the first integrated circuit chip is less than the first control voltage.

7. The safety response trigger circuit according to claim 5, characterized in that, The first integrated circuit chip is an NE555 time base integrated circuit, a trigger terminal of the NE555 time base integrated circuit is connected to an output terminal of the pulse conversion circuit, an output terminal of the NE555 time base integrated circuit is connected to an input terminal of the signal latching circuit, and the first control voltage is the voltage of a control terminal of the NE555 time base integrated circuit; When the voltage at the threshold terminal of the first integrated circuit chip is greater than the first control voltage, the first integrated circuit chip outputs the first trigger signal, and the first trigger signal is a constant voltage; When the voltage at the threshold terminal of the first integrated circuit chip is less than the first control voltage, the first integrated circuit chip outputs the second trigger signal, and the second trigger signal is the voltage at the trigger terminal of the NE555 timer integrated circuit.

8. The safety response trigger circuit according to claim 5, wherein The first trigger signal is a constant voltage, and the second trigger signal is a pulse signal received by the first integrated circuit chip; The pulse width comparison circuit further includes: A constant voltage conversion circuit connected between the output terminal of the first integrated circuit chip and the input terminal of the signal latch circuit. The constant voltage conversion circuit is configured to convert the received constant voltage into a first trigger signal in a first constant voltage form, and convert the received pulse signal into a second trigger signal in a second constant voltage form.

9. The safety response trigger circuit according to claim 8, wherein The constant voltage conversion circuit includes: A second charge and discharge circuit connected to the output terminal of the first integrated circuit chip; A second comparator, with two input terminals of the second comparator connected to the second charge and discharge circuit and receiving a second threshold signal respectively; When the second charge and discharge circuit receives the constant voltage and the pulse signal respectively, the voltages output by the second charge and discharge circuit to the second comparator are greater than and less than the second threshold signal respectively, so that the second comparator outputs the first trigger signal in the first constant voltage form and the second trigger signal in the second constant voltage form respectively.

10. The safety response trigger circuit according to claim 9, characterized in that, The second charge and discharge circuit includes: A second triode, with the control terminal of the second triode connected to the output terminal of the first integrated circuit chip; A second capacitor, connected in parallel between the input terminal and the output terminal of the second triode. The positive electrode of the second capacitor is connected to the positive terminal of the second comparator and connected to the power supply through a fifth voltage dividing resistor, and the negative electrode of the second capacitor is grounded; When the second charge and discharge circuit receives the constant voltage, the second triode remains cut off, and the second capacitor remains charged, so that the voltage at the positive terminal of the second comparator is greater than the second threshold signal, and the second comparator outputs the first trigger signal in the first constant voltage form; When the second charge and discharge circuit receives the pulse signal, the second triode conducts and cuts off, and the second capacitor discharges and charges, so that the voltage at the positive terminal of the second comparator is less than the second threshold signal, and the second comparator outputs the second trigger signal in the second constant voltage form; Wherein, the second constant voltage is less than the first constant voltage.

11. The safety response trigger circuit according to claim 10, wherein, A sixth voltage dividing resistor is connected in series between the control terminal of the second triode and the output terminal of the first integrated circuit chip, and / or a seventh voltage dividing resistor is connected in parallel between the second capacitor and the second triode.

12. The safety response trigger circuit according to claim 1, wherein The signal latch circuit includes: A second integrated circuit chip, connected to the output terminal of the pulse width comparison circuit. The second integrated circuit chip is configured to latch the received trigger signal and output the latest trigger signal based on the periodically generated activation signal.

13. The safety response trigger circuit according to claim 12, characterized in that, The second integrated circuit chip is a rising-edge triggered D flip-flop. The set terminal of the rising-edge triggered D flip-flop is connected to the output terminal of the pulse width comparison circuit. The clock signal input terminal of the rising-edge triggered D flip-flop receives the activation signal, and the activation signal is a rising-edge signal.

14. The safety response trigger circuit according to claim 12, wherein, The activation signal is generated by a timing reset circuit, and the timing reset circuit includes: A third integrated circuit chip, connected to the second integrated circuit chip; A charge-discharge interlock circuit, connected to the threshold terminal of the third integrated circuit chip; As the charge-discharge interlock circuit operates, the voltage of the threshold terminal of the third integrated circuit chip and the second control voltage periodically satisfy a preset relationship, so that the third integrated circuit chip periodically outputs the activation signal.

15. The safety response trigger circuit according to claim 14, wherein The charge-discharge interlock circuit includes: A third triode, the control terminal of the third triode is connected to the discharge terminal of the third integrated circuit chip, the input terminal of the third triode is connected to the power supply through an eighth voltage dividing resistor, and the output terminal of the third triode is grounded; A fourth triode, the control terminal of the fourth triode is connected to the input terminal of the third triode, and the input terminal of the fourth triode is connected to the power supply; A third capacitor, the positive electrode of the third capacitor is connected to the threshold terminal of the third integrated circuit chip and the output terminal of the fourth triode, and is connected to the discharge terminal of the third integrated circuit chip through a ninth voltage dividing resistor, and the negative electrode of the third capacitor is grounded; Wherein, the third triode and the fourth triode are alternately turned on, so that the voltage of the threshold terminal of the third integrated circuit chip and the second control voltage periodically satisfy the preset relationship.

16. The safety response trigger circuit according to claim 15, wherein The third integrated circuit chip is an NE555 timer integrated circuit, and the second control voltage is the voltage of the control terminal of the NE555 timer integrated circuit; When the voltage of the threshold terminal of the third integrated circuit chip is greater than the second control voltage, the third integrated circuit chip outputs the activation signal.

17. The safety response trigger circuit according to claim 15, wherein The discharge terminal of the third integrated circuit chip is connected to the power supply through a tenth voltage dividing resistor, and / or, the positive electrode of the third capacitor is connected to the output terminal of the fourth triode through an eleventh voltage dividing resistor.

18. A security response system is applied to a multi-drive system, characterized in that, Including: A fault response module, configured to obtain the rotational speed signal of the faulty drive system in response to the fault signal of the multi-drive system ； The safety response trigger circuit according to any one of claims 1-17, the pulse conversion circuit of the safety response trigger circuit is connected to the fault response module, and the trigger signals output by the signal latch circuit of the safety response trigger circuit include a first trigger signal and a second trigger signal; A safety policy module, configured to trigger the faulty drive system to enter a first safety state according to the first trigger signal, and trigger the faulty drive system to enter a second safety state according to the second trigger signal.

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