FM radio management circuit

Abstract

The utility model provides an FM radio management circuit comprising an SOC chip, an AMP chip, a DSP chip and an FM socket. The radio frequency signal output end of the FM socket is connected with the radio frequency signal input end of the DSP chip through a frequency screening circuit, and the frequency screening circuit comprises a frequency modulation circuit and / or an amplitude modulation circuit; the communication data transmission end of the DSP chip is connected with the communication data transmission end of the SOC chip, and the audio signal output end of the DSP chip is connected with the audio signal input end of the AMP chip. According to the utility model, the output power of the radio is enhanced, audio signals can be ensured to fully drive the loudspeaker, and clear and powerful playing of sound is realized. Not only is the signal receiving capability of the FM radio improved, but also the tone quality and the sound output effect are improved.

Description

Technical Field

[0001] The utility model relates to a radio management circuit, in particular to an FM radio management circuit. Background Art

[0002] Due to the existence of various electronic devices inside an automobile, such as an engine control system, a car audio, etc., these devices may generate electromagnetic interference, affecting the reception performance of the radio. In addition, there are also various interference sources in the external environment, such as lightning, radio waves, etc., and these interference signals may reduce the signal-to-noise ratio and sensitivity of the radio. Therefore, it is necessary to consider how to design a radio circuit to have sufficient frequency stability and selectivity to accurately receive and extract useful radio signals. Content of the Utility Model

[0003] The utility model aims to at least solve the technical problems existing in the prior art, and particularly innovatively provides an FM radio management circuit.

[0004] To achieve the above object of the utility model, the utility model provides an FM radio management circuit, including: an SOC chip, an AMP chip, a DSP chip, and an FM socket;

[0005] A frequency screening circuit is connected between the radio frequency signal output end of the FM socket and the radio frequency signal input end of the DSP chip, and the frequency screening circuit includes a frequency modulation circuit and / or an amplitude modulation circuit; the communication data transmission end of the DSP chip is connected to the communication data transmission end of the SOC chip, and the audio signal output end of the DSP chip is connected to the audio signal input end of the AMP chip;

[0006] A frequency screening circuit is arranged between the DSP chip and the FM socket, allowing signals within a specific frequency range to pass through while blocking other frequency signals. Thus, it is ensured that only useful signals are transmitted to subsequent processing units, improving the overall performance and stability of the system.

[0007] Further, the frequency modulation circuit includes:

[0008] The frequency modulation input end FMI of the DSP chip UR1 is connected to the first ends of a capacitor CR5, an inductor LR1, and an inductor LR2. The second ends of the inductor LR2 and the capacitor CR5 are respectively connected to the power ground; the second end of the inductor LR1 is connected to the first end of a capacitor CR4, and the second end of the capacitor CR4 is connected to the radio frequency signal output end of the FM socket.

[0009] Further, the amplitude modulation circuit includes:

[0010] The RF signal output terminal of the FM socket is connected to the first terminal of capacitor CR3. The second terminal of capacitor CR3 is connected to the first terminal of inductor LR6 and the first terminal of capacitor CR38. The second terminal of inductor LR6 and the second terminal of capacitor CR38 are connected to the first terminal of capacitor CR39, the first terminal of transient diode LTVS18, and the input terminal of the band-pass filter circuit. The output terminal of the band-pass filter circuit is connected to the first terminal of capacitor CR41. The band-pass filter circuit includes: resistor RR31, inductor LR8, and capacitor CR40 connected in parallel;

[0011] The second terminal of capacitor CR39 is connected to the first terminal of inductor LR7. The second terminal of inductor LR7 is connected to the power ground. The second terminal of transient diode LTVS18 is connected to the power ground;

[0012] The second terminal of capacitor CR41 is connected to the AM input terminal AMI of DSP chip UR1.

[0013] Furthermore, the circuit connection of the DSP chip includes:

[0014] The channel selection terminal ABYP of DSP chip UR1 is connected to the first terminal of capacitor CR42, the first terminal of capacitor CR43, the first terminal of capacitor CR44, the first terminal of capacitor CR45, the first terminal of capacitor CR46, and the first terminal of inductor LR9. The second terminal of inductor LR9 is connected to the power +3.3VSW;

[0015] The positive analog input terminal AIN0P of DSP chip UR1 is connected to the first terminal of capacitor CR47. The second terminal of capacitor CR47 is connected to the first terminal of resistor RR35,

[0016] The negative analog input terminal AIN0N of DSP chip UR1 and the first terminal of capacitor CR48 are connected. The second terminal of capacitor CR48 is connected to the first terminal of capacitor CR50, the first terminal of capacitor CR52, the first terminal of capacitor CR54, the first terminal of capacitor CR55, the first terminal of capacitor CR56, the first terminal of capacitor CR57, the first terminal of capacitor CR58, the first terminal of capacitor CR60, and the power ground;

[0017] The positive analog input terminal AIN1P of DSP chip UR1 is connected to the first terminal of capacitor CR49. The second terminal of capacitor CR49 is connected to the first terminal of resistor RR36;

[0018] The negative analog input terminal AIN1N of DSP chip UR1 is connected to the second terminal of capacitor CR50,

[0019] The positive analog input terminal AIN2P of the DSP chip UR1 is connected to the first terminal of the capacitor CR51. The second terminal of the capacitor CR51 is connected to the first terminal of the resistor RR32. The second terminal of the resistor RR32 is connected to the first terminal of the capacitor C140. The second terminal of the capacitor C140 is respectively connected to the signal transmission terminal of the AMP chip and the signal transmission terminal of the SOC chip;

[0020] The negative analog input terminal AIN2N of the DSP chip UR1 is connected to the second terminal of the capacitor CR52;

[0021] The positive analog input terminal AIN3P of the DSP chip UR1 is connected to the first terminal of the capacitor CR53. The second terminal of the capacitor CR53 is connected to the first terminal of the resistor RR33. The second terminal of the resistor RR33 is connected to the first terminal of the capacitor C141. The second terminal of the capacitor C141 is respectively connected to the signal transmission terminal of the AMP chip and the signal transmission terminal of the SOC chip;

[0022] The negative analog input terminal AIN3N of the DSP chip UR1 is connected to the second terminal of the capacitor CR54;

[0023] The positive analog input terminal AIN4P of the DSP chip UR1 is connected to the second terminal of the capacitor CR55;

[0024] The negative analog input terminal AIN4N of the DSP chip UR1 is connected to the second terminal of the capacitor CR56;

[0025] The positive analog input terminal AIN5P of the DSP chip UR1 is connected to the second terminal of the capacitor CR57;

[0026] The negative analog input terminal AIN5N of the DSP chip UR1 is connected to the second terminal of the capacitor CR58 and the first terminal of the resistor RR39;

[0027] The positive analog input terminal AIN6P of the DSP chip UR1 is connected to the second terminal of the resistor RR39 and the first terminal of the capacitor CR59. The second terminal of the capacitor CR59 is connected to the first terminal of the resistor RR34;

[0028] The negative analog input terminal AIN6N of the DSP chip UR1 is connected to the second terminal of the capacitor CR60;

[0029] The second terminals of the resistors RR35, RR36, RR37, RR38, and RR34 are connected to the power ground;

[0030] The reset signal terminal RSTB of the DSP chip UR1 is connected to the first terminal of the resistor RR42 and the reset control terminal of the SOC chip;

[0031] The mode selection terminal SMODE of the DSP chip UR1 is connected to the first ends of the resistor RR40 and the resistor RR43; the second end of the resistor RR40 is connected to the power ground;

[0032] The interrupt request terminal INTB of the DSP chip UR1 is connected to the first end of the resistor RR41 and the interrupt request data terminal of the SOC chip;

[0033] The second ends of the resistor RR41, the resistor RR42, and the resistor RR43 are connected to the power supply DSP_VIO1_3V3 / 1V8;

[0034] The data output terminal MISO / A0 of the DSP chip UR1 is connected to the first end of the resistor RB33, and the second end of the resistor RB33 is connected to the first end of the resistor RB29 and the data receiving terminal of the SOC chip;

[0035] The data receiving terminal MOSI / SDA of the DSP chip UR1 is connected to the first end of the resistor RB32, and the second end of the resistor RB32 is connected to the first end of the resistor RB28 and the data output terminal of the SOC chip;

[0036] The clock terminal SCLK / SCL of the DSP chip UR1 is connected to the first end of the resistor RB31, and the second end of the resistor RB31 is connected to the first end of the resistor RB27 and the clock control terminal of the SOC chip,

[0037] The chip select signal receiving terminal SSB / A1 of the DSP chip UR1 is connected to the first end of the resistor R0.1B30, and the second end of the resistor RB30 is connected to the first end of the resistor RB26 and the chip select control terminal of the SOC chip,

[0038] The second ends of the resistor RB26, the resistor RB27, the resistor RB28, and the resistor RB29 are connected to the power supply +3.3VSW;

[0039] The digital bypass terminal DBYP of the DSP chip UR1 is connected to the first ends of the capacitor CR18, the capacitor CR20, the capacitor CR22, the capacitor CR24, the capacitor CR26, the capacitor CR28, the first end of the capacitor CR19, the first end of the capacitor CR21, the first end of the capacitor CR23, the first end of the capacitor CR25, the first end of the capacitor CR27, the first end of the capacitor CR29; the first end of the capacitor CR30, the first end of the capacitor CR31, the first end of the capacitor CR32, the first end of the capacitor CR33, the first end of the capacitor CR34, the first end of the capacitor CR35, the first end of the capacitor CR36, the first end of the capacitor CR37;

[0040] The second terminal of capacitor CR19, the second terminal of capacitor CR21, the second terminal of capacitor CR23, the second terminal of capacitor CR25, the second terminal of capacitor CR27, the second terminal of capacitor CR29, the first terminal of inductor LR3 are connected to the power supply DSP_DVDD1V8_250MA; the second terminal of inductor LR3 is connected to the first terminal of capacitor CR29 and the power supply +1.8V; the second terminal of capacitor CR29 is connected to the power supply ground;

[0041] The second terminal of capacitor CR30, the second terminal of capacitor CR31, the second terminal of capacitor CR32, the second terminal of capacitor CR33, the second terminal of capacitor CR34, the second terminal of capacitor CR35, the second terminal of capacitor CR36, the second terminal of capacitor CR37, the first terminal of inductor LR5 are connected to the power supply DSP_VIO1_3V3 / 1V8; the second terminal of inductor LR5 is connected to the power supply +3.3VSW;

[0042] The second power input terminal VIO2 of DSP chip UR1 is connected to the second terminal of capacitor CR18, the second terminal of capacitor CR20, the second terminal of capacitor CR22, the second terminal of capacitor CR24, the second terminal of capacitor CR26, the second terminal of capacitor CR28, the first terminal of inductor LR4 and is connected to DSP_VIO2_3V3 / 1V8, and the second terminal of inductor LR4 is connected to the power supply +3.3VSW;

[0043] The data input terminal NC of DSP chip UR1 is connected to the first terminal of resistor RR29, the second terminal of resistor RR29 is connected to the first terminal of resistor RR50 and the data output terminal of the Bluetooth WIFI chip, and the second terminal of resistor RR50 is connected to the digital audio output terminal of the SOC chip,

[0044] The digital input frame synchronization terminal DIFS2 of DSP chip UR1 is connected to the first terminal of resistor RR28, the second terminal of resistor RR28 is connected to the first terminal of resistor RR51 and the frame synchronization clock signal output terminal of the Bluetooth WIFI chip, and the second terminal of resistor RR51 is connected to the clock signal output terminal of the SOC chip,

[0045] The digital input clock terminal DICLK2 of DSP chip UR1 is connected to the first terminal of resistor RR27, the second terminal of resistor RR27 is connected to the first terminal of resistor RR52 and the data clock signal output terminal of the Bluetooth WIFI chip, and the second terminal of resistor RR52 is connected to the clock signal control terminal of the SOC chip;

[0046] The first analog audio output terminal of DSP chip UR1 is connected to the first terminal of resistor RR23, the second terminal of resistor RR23 is connected to the first terminal of capacitor CR17 and the first terminal of capacitor CR8, and the second terminal of capacitor CR17 is connected to the audio left channel input terminal of the AMP chip;

[0047] The first analog audio output terminal of the DSP chip UR1 is connected to the first terminal of the resistor RR22. The second terminal of the resistor RR22 is connected to the first terminal of the capacitor CR16 and the first terminal of the capacitor CR9. The second terminal of the capacitor CR16 is connected to the audio right channel input terminal of the AMP chip;

[0048] The third analog audio output terminal of the DSP chip UR1 is connected to the first terminal of the resistor RR21. The second terminal of the resistor RR21 is connected to the first terminal of the capacitor CR10;

[0049] The fourth analog audio output terminal of the DSP chip UR1 is connected to the first terminal of the resistor RR20. The second terminal of the resistor RR20 is connected to the first terminal of the capacitor CR11;

[0050] The second terminals of the capacitor CR8, the capacitor CR9, the capacitor CR10, and the capacitor CR11 are connected to the power ground.

[0051] Among them, the inductor L11, the inductor L12, the capacitor C108, the capacitor C110, the capacitor C112, the capacitor C114, the resistor R47, the resistor R48, the capacitor C116, and the capacitor C119 form a filter circuit unique to the class-D power amplifier. The same is true for the three paths of the inductors L12, L9, and L10, all of which are filter circuits of the class-D power amplifier.

[0052] Furthermore, the RF signal output terminal of the FM socket, the second terminal of the capacitor CR2, and the first terminal of the transient diode LTVS17 are connected to the power supply TUNER_RF; the second terminal of the transient diode LTVS17 is connected to the power ground;

[0053] The power supply TUNER_RF is provided by the power supply chip U8:

[0054] The power input terminal IN of the power supply chip U8, the first terminal of the capacitor CD1, and the first terminal of the capacitor C91 are connected to the power supply +VBATT. The second terminal of the capacitor CD1 and the second terminal of the capacitor C91 are connected to the power ground;

[0055] The first enable terminal EN1 of the power supply chip U8 is connected to the first terminal of the resistor RO9. The second terminal of the resistor RO9 is connected to the FM enable control terminal of the MCU chip,

[0056] The second enable terminal EN2 of the power supply chip U8 is connected to the first terminal of the resistor RO18. The second terminal of the resistor RO18 is connected to the camera enable control terminal of the MCU chip;

[0057] The power supply terminal VCC of the power supply chip U8 is connected to the first terminal of the capacitor CO8,

[0058] The first current sensing output terminal SENSE1 of the power supply chip U8 is connected to the first terminal of the resistor RO7 and the first terminal of the capacitor CO6. The second terminal of the resistor RO7, the second terminal of the capacitor CO6, and the second terminal of the capacitor CO8 are connected to the power ground.

[0059] The first current sensing output terminal SENSE2 of the power supply chip U8 is connected to the first terminal of the resistor RO8 and the first terminal of the capacitor CO7. The second terminal of the resistor RO8 and the second terminal of the capacitor CO7 are connected to the power ground.

[0060] The enable control terminal SENSE_SEL of the power supply chip U8 is connected to the first terminal of the resistor RO10. The second terminal of the resistor RO10 is connected to the power ground.

[0061] The current sensing enable terminal SENSE_EN of the power supply chip U8 is connected to the first terminal of the resistor RO11. The second terminal of the resistor RO11 is connected to the power ground.

[0062] The first power output terminal OUT1 of the power supply chip U8 is connected to the first terminal of the inductor LD1 and the first terminal of the resistor RO13. The second terminal of the inductor LD1 is connected to the first terminal of the capacitor CD2, the first terminal of the capacitor CD3, and the first terminal of the inductor LD2. The second terminal of the inductor LD2 outputs the power supply TUNER_RF. The second terminals of the capacitor CD2 and the capacitor CD3 are connected to the power ground. Among them, the inductors LD1 and LD2 are used for EMC interference problems.

[0063] The first feedback terminal FB1 of the power supply chip U8 is connected to the second terminal of the resistor RO13 and the first terminal of the resistor RO15. The second terminal of the resistor RO15, the first terminal of the resistor RO17, the first terminal of the resistor RO16, and the first terminal of the resistor RO14 are connected to the power ground.

[0064] The first power output terminal OUT2 of the power supply chip U8 outputs the power supply CAMPOW + 8V and is connected to the first terminal of the resistor RO12, the first terminal of the capacitor CD6, and the first terminal of the capacitor CD5. The second terminals of the capacitor CD6 and the capacitor CD5 are connected to the power ground.

[0065] The first feedback terminal FB2 of the power supply chip U8 is connected to the second terminal of the resistor RO12 and the second terminal of the resistor RO17.

[0066] The ground terminal GND of the power supply chip U8 is connected to the power ground.

[0067] The first current limiting terminal LIM1 of the power supply chip U8 is connected to the second terminal of the resistor RO16.

[0068] The second current limiting terminal LIM2 of the power supply chip U8 is connected to the second terminal of the resistor RO14.

[0069] Furthermore, the audio signal output terminal of the DSP chip is connected to the audio signal input terminal of the AMP chip, including:

[0070] The mode selection terminal MODSEL of the AMP chip U9 is connected to the power ground;

[0071] The input terminal SDZ of the audio amplifier of the AMP chip U9 and the fault terminal FAULTZ of the AMP chip U9 are connected to the first terminal of the resistor R129 and the first terminal of the resistor R130; the second terminal of the resistor R129 is connected to the control terminal of the MCU chip; the second terminal of the resistor R130 is connected to the power ground;

[0072] The right-channel positive audio input terminal RINP of the AMP chip U9 is connected to the first terminal of the capacitor C94, the second terminal of the capacitor C94 is connected to the first terminal of the resistor R128 and the audio right-channel data output terminal of the DSP chip, and the second terminal of the resistor R128 is connected to the ADC right-channel output terminal of the SOC chip;

[0073] The right-channel negative audio input terminal RINN of the AMP chip U9 is connected to the first terminal of the capacitor C95;

[0074] The power limit terminal PLIMIT of the AMP chip U9 is connected to the first terminal of the resistor R126 and the first terminal of the resistor R127;

[0075] The internal power supply terminal GVDD of the AMP chip U9 is connected to the second terminal of the resistor R127, the first terminal of the resistor R42, and the first terminal of the capacitor C92;

[0076] The selectable gain terminal GAIN / SLV of the AMP chip U9 is connected to the second terminal of the resistor R42 and the first terminal of the resistor R43;

[0077] The ground terminal GND of the AMP chip U9, the second terminal of the capacitor C95, the second terminal of the resistor R126, the second terminal of the capacitor C92, and the second terminal of the resistor R43 are connected to the power ground;

[0078] The left-channel positive audio input terminal LINP of the AMP chip U9 is connected to the first terminal of the capacitor C93, the second terminal of the capacitor C93 is connected to the first terminal of the resistor R125 and the audio left-channel data output terminal of the DSP chip, and the second terminal of the resistor R125 is connected to the ADC right-channel output terminal of the SOC chip;

[0079] The left-channel negative audio input terminal LINN of the AMP chip U9 is connected to the first terminal of the capacitor C96, and the second terminal of the capacitor C96 is connected to the power ground;

[0080] The mute control terminal MUTE of the AMP chip U9 is connected to the mute control terminal of the MCU chip and the first terminal of the resistor R45, and the second terminal of the resistor R45 is connected to the power supply +5VCAN;

[0081] The AM frequency modulation terminal AM2 of the AMP chip U9 is connected to the power supply ground;

[0082] The AM frequency modulation terminal AM1 of the AMP chip U9 is connected to the power supply ground;

[0083] The AM frequency modulation output terminal AMO of the AMP chip U9 is connected to the AM frequency modulation output terminal of the MCU chip;

[0084] The power supply terminal AVCC of the AMP chip U9, the power supply terminal PVCC of the AMP chip U9, the power supply terminal PVCC of the AMP chip U9, the first terminal of the capacitor CR62, the first terminal of the capacitor C104, the first terminal of the capacitor C106, and the positive electrode of the polarized capacitor C106 are connected to the power supply +VBATT; the second terminal of the capacitor CR62, the second terminal of the capacitor C104, the second terminal of the capacitor C106, and the negative electrode of the polarized capacitor C106 are connected to the power supply ground;

[0085] The bootstrap terminal BSNL of the left - channel negative output of the AMP chip U9 is connected to the first terminal of the capacitor C103, the second terminal of the capacitor C103 is connected to the left - channel negative output terminal OUTNL of the AMP chip U9 and the first terminal of the inductor L10. The second terminal of the inductor L10 outputs the left - channel negative pole and is connected to the first terminal of the capacitor C111, the first terminal of the capacitor C115, and the first terminal of the resistor R50. The second terminal of the resistor R50 is connected to the first terminal of the capacitor C118, and the second terminal of the capacitor C118 is connected to the power supply ground; the second terminals of the capacitor C111 and the capacitor C115 are connected to the power supply ground;

[0086] The ground terminal GND of the AMP chip U9 is connected to the power supply ground;

[0087] The left - channel positive output terminal OUTPL of the AMP chip U9 is connected to the first terminal of the capacitor C102 and the first terminal of the inductor L9. The second terminal of the inductor L9 outputs the left - channel positive pole and is connected to the first terminal of the capacitor C109, the first terminal of the capacitor C113, and the first terminal of the resistor R49. The second terminal of the resistor R49 is connected to the first terminal of the capacitor C117, and the second terminal of the capacitor C117 is connected to the power supply ground; the second terminals of the capacitor C109 and the capacitor C113 are connected to the power supply ground;

[0088] The bootstrap terminal BSPL of the left - channel positive output of the AMP chip U9 is connected to the second terminal of the capacitor C102,

[0089] The bootstrap terminal BSNR of the negative right channel output of the AMP chip U9 is connected to the first terminal of the capacitor C101. The second terminal of the capacitor C101 is connected to the negative right channel output terminal OUTNR of the AMP chip U9 and the first terminal of the inductor L12. The second terminal of the inductor L12 outputs the negative pole of the right channel and is connected to the first terminal of the capacitor C110, the first terminal of the capacitor C114, and the first terminal of the resistor R48. The second terminal of the resistor R48 is connected to the first terminal of the capacitor C119, and the second terminal of the capacitor C119 is connected to the power ground. The second terminals of the capacitor C110 and the capacitor C114 are connected to the power ground.

[0090] The positive right channel output terminal OUTPR of the AMP chip U9 is connected to the first terminal of the capacitor C99 and the first terminal of the inductor L11. The second terminal of the inductor L11 outputs the positive pole of the right channel and is connected to the first terminal of the capacitor C108, the first terminal of the capacitor C112, and the first terminal of the resistor R47. The second terminal of the resistor R47 is connected to the first terminal of the capacitor C116, and the second terminal of the capacitor C116 is connected to the power ground. The second terminals of the capacitor C108 and the capacitor C112 are connected to the power ground.

[0091] The bootstrap terminal BSPR of the positive right channel output of the AMP chip U9 is connected to the second terminal of the capacitor C99.

[0092] The power supply terminal PVCC of the AMP chip U9, the first terminal of the resistor R46, the first terminal of the capacitor CR61, the first terminal of the capacitor C98, the first terminal of the capacitor C100, and the positive electrode of the polarized capacitor C105 are connected to the power supply +VBATT. The second terminal of the resistor R46 is connected to the first terminal of the capacitor C97, and the second terminal of the capacitor C97 is connected to the power ground. The second terminals of the capacitor CR61, the capacitor C98, the capacitor C100, and the negative electrode of the polarized capacitor C105 are connected to the power ground.

[0093] In summary, due to the adoption of the above technical solutions, the output power of the radio of the present utility model is enhanced, ensuring that the audio signal can fully drive the speaker and realizing clear and powerful sound playback. It not only improves the signal reception ability of the FM radio but also improves the sound quality and the sound output effect.

[0094] The additional aspects and advantages of the present utility model will be partially given in the following description, partially will become obvious from the following description, or will be understood through the practice of the present utility model. Description of the Drawings

[0095] The above and / or additional aspects and advantages of the present utility model will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, where:

[0096] Figure 1 is a schematic circuit connection diagram of the present utility model.

[0097] Figure 2 It is a schematic diagram of the circuit connection of the DSP chip of the present utility model.

[0098] Figure 3 It is a schematic diagram of the power supply circuit connection of the DSP chip of the present utility model.

[0099] Figure 4 It is a schematic diagram of the circuit connection of the AMP chip of the present utility model. Detailed implementation manners

[0100] The embodiments of the present utility model will be described in detail below. The examples of the embodiments are shown in the accompanying drawings, in which the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present utility model and should not be construed as a limitation to the present utility model.

[0101] The present utility model provides an FM radio management circuit, as Figure 1 shown, including: an MCU chip, an SOC chip, an AMP chip, a DSP chip, and an FM socket;

[0102] The RF signal output terminal of the FM socket is connected to the RF signal input terminal of the DSP chip, the communication data transmission terminal of the DSP chip is connected to the communication data transmission terminal of the SOC chip, and the audio signal output terminal of the DSP chip is connected to the audio signal input terminal of the AMP chip;

[0103] The communication data transmission terminal of the MCU chip is connected to the communication data transmission terminal of the SOC chip. The MCU plays multiple roles in the instrument communication transmission circuit, such as control and coordination, data processing and communication, function expansion and modularization, and system monitoring and protection.

[0104] When the FM socket receives an external RF signal RF, the signal is first transmitted to the DSP (Digital Signal Processor) chip for signal processing, including frequency modulation and possibly amplitude modulation operations. After processing the signal, the DSP chip communicates with the SOC (System-on-Chip) through the I2S interface and the SPI interface. The SPI interface is mainly used for the transmission of control signals for the FM frequency selection function in this specific scenario. Once the SOC completes the FM frequency selection operation, the DSP chip then outputs the processed AOUT audio signal to the AMP (Audio Power Amplifier) chip. After receiving this signal, the AMP chip amplifies it and drives audio output devices such as speakers, and finally the user can hear the audio content that has been processed by the DSP and selected by the SOC.

[0105] Briefly, when an external radio frequency signal RF is received, it is processed through a DSP chip, and the signal is transmitted to the SOC chip via SPI for FM frequency modulation and station selection; then the DSP chip outputs an AOUT signal to the AMP chip.

[0106] The circuit of the DSP chip is as Figure 2 shown:

[0107] The crystal oscillator input terminal XTALI of the DSP chip UR1 is connected to the first terminal of the capacitor CR7 and the third terminal of the crystal oscillator XR1.

[0108] The crystal oscillator output terminal XTALO of the DSP chip UR1 is connected to the first terminal of the resistor RR19. The second terminal of the resistor RR19 is connected to the first terminal of the capacitor CR6 and the first terminal of the crystal oscillator XR1. The second terminals of the capacitor CR6 and the capacitor CR7 are connected to the power ground; the second and fourth terminals of the crystal oscillator XR1 are both connected to the power ground.

[0109] A frequency screening circuit is required between the DSP chip and the FM socket to allow signals within a specific frequency range to pass through while blocking other frequency signals. This is used to ensure that only useful signals are transmitted to the subsequent processing unit, thereby improving the overall performance and stability of the system. Specifically: The frequency modulation input terminal FMI of the DSP chip UR1 is connected to the first terminal of the capacitor CR5, the first terminal of the inductor LR1, and the first terminal of the inductor LR2. The second terminal of the inductor LR2 and the second terminal of the capacitor CR5 are respectively connected to the power ground; the second terminal of the inductor LR1 is connected to the first terminal of the capacitor CR4. The second terminal of the capacitor CR4 is connected to the first terminal of the capacitor CR2 and the first terminal of the capacitor CR3; the second terminal of the capacitor CR3 is connected to the first terminal of the inductor LR6 and the first terminal of the capacitor CR38; the second terminal of the inductor LR6 and the second terminal of the capacitor CR38 are connected to the first terminal of the capacitor CR39, the first terminal of the transient diode LTVS18, and the input terminal of the band-pass filter circuit. The output terminal of the band-pass filter circuit is connected to the first terminal of the capacitor CR41; The band-pass filter circuit includes: the resistor RR31, the inductor LR8, and the capacitor CR40 connected in parallel.

[0110] The second terminal of the capacitor CR39 is connected to the first terminal of the inductor LR7, and the second terminal of the inductor LR7 is connected to the power ground; the second terminal of the transient diode LTVS18 is connected to the power ground.

[0111] The second terminal of the capacitor CR41 is connected to the amplitude modulation input terminal AMI of the DSP chip UR1.

[0112] The second terminal of the capacitor CR2, the first terminal of the transient diode LTVS17, the antenna socket are connected to the power supply TUNER_RF; the power supply TUNER_RF is provided by the power supply chip U8. The second terminal of the transient diode LTVS17 is connected to the power ground;

[0113] The channel selection terminal ABYP of the DSP chip UR1 is connected to the first terminal of the capacitor CR42, the first terminal of the capacitor CR43, the first terminal of the capacitor CR44, the first terminal of the capacitor CR45, the first terminal of the capacitor CR46 and the first terminal of the inductor LR9. The second terminal of the inductor LR9 is connected to the power supply +3.3VSW;

[0114] The positive analog input terminal AIN0P of the DSP chip UR1 is connected to the first terminal of the capacitor CR47. The second terminal of the capacitor CR47 is connected to the first terminal of the resistor RR35.

[0115] The negative analog input terminal AIN0N of the DSP chip UR1 is connected to the first terminal of the capacitor CR48. The second terminal of the capacitor CR48 is connected to the first terminal of the capacitor CR50, the first terminal of the capacitor CR52, the first terminal of the capacitor CR54, the first terminal of the capacitor CR55, the first terminal of the capacitor CR56, the first terminal of the capacitor CR57, the first terminal of the capacitor CR58, the first terminal of the capacitor CR60 and the power ground;

[0116] The positive analog input terminal AIN1P of the DSP chip UR1 is connected to the first terminal of the capacitor CR49. The second terminal of the capacitor CR49 is connected to the first terminal of the resistor RR36;

[0117] The negative analog input terminal AIN1N of the DSP chip UR1 is connected to the second terminal of the capacitor CR50;

[0118] The positive analog input terminal AIN2P of the DSP chip UR1 is connected to the first terminal of the capacitor CR51. The second terminal of the capacitor CR51 is connected to the first terminal of the resistor RR32. The second terminal of the resistor RR32 is connected to the first terminal of the capacitor C140. The second terminal of the capacitor C140 is respectively connected to the signal transmission terminal of the AMP chip and the signal transmission terminal of the SOC chip;

[0119] The negative analog input terminal AIN2N of the DSP chip UR1 is connected to the second terminal of the capacitor CR52;

[0120] The positive analog input terminal AIN3P of the DSP chip UR1 is connected to the first terminal of the capacitor CR53. The second terminal of the capacitor CR53 is connected to the first terminal of the resistor RR33. The second terminal of the resistor RR33 is connected to the first terminal of the capacitor C141. The second terminal of the capacitor C141 is respectively connected to the signal transmission terminal of the AMP chip and the signal transmission terminal of the SOC chip;

[0121] The negative analog input terminal AIN3N of the DSP chip UR1 is connected to the second terminal of the capacitor CR54;

[0122] The positive analog input terminal AIN4P of the DSP chip UR1 is connected to the second terminal of the capacitor CR55;

[0123] The negative analog input terminal AIN4N of the DSP chip UR1 is connected to the second terminal of the capacitor CR56;

[0124] The positive analog input terminal AIN5P of the DSP chip UR1 is connected to the second terminal of the capacitor CR57;

[0125] The negative analog input terminal AIN5N of the DSP chip UR1 is connected to the second terminal of the capacitor CR58 and the first terminal of the resistor RR39;

[0126] The positive analog input terminal AIN6P of the DSP chip UR1 is connected to the second terminal of the resistor RR39 and the first terminal of the capacitor CR59. The second terminal of the capacitor CR59 is connected to the first terminal of the resistor RR34;

[0127] The negative analog input terminal AIN6N of the DSP chip UR1 is connected to the second terminal of the capacitor CR60;

[0128] The second terminals of the resistors RR35, RR36, RR37, RR38, and RR34 are connected to the power ground;

[0129] The reset signal terminal RSTB of the DSP chip UR1 is connected to the first terminal of the resistor RR42 and the reset control terminal of the SOC chip;

[0130] The mode selection terminal SMODE of the DSP chip UR1 is connected to the first terminals of the resistors RR40 and RR43. The second terminal of the resistor RR40 is connected to the power ground;

[0131] The interrupt request terminal INTB of the DSP chip UR1 is connected to the first terminal of the resistor RR41 and the interrupt request data terminal of the SOC chip;

[0132] The second terminals of the resistors RR41, RR42, and RR43 are connected to the power DSP_VIO1_3V3 / 1V8;

[0133] The data output terminal MISO / A0 of the DSP chip UR1 is connected to the first terminal of the resistor RB33. The second terminal of the resistor RB33 is connected to the first terminal of the resistor RB29 and the data receiving terminal of the SOC chip;

[0134] The data receiving end MOSI / SDA of the DSP chip UR1 is connected to the first end of the resistor RB32, and the second end of the resistor RB32 is connected to the first end of the resistor RB28 and the data output end of the SOC chip;

[0135] The clock end SCLK / SCL of the DSP chip UR1 is connected to the first end of the resistor RB31, and the second end of the resistor RB31 is connected to the first end of the resistor RB27 and the clock control end of the SOC chip,

[0136] The chip select signal receiving end SSB / A1 of the DSP chip UR1 is connected to the first end of the resistor R0.1B30, and the second end of the resistor RB30 is connected to the first end of the resistor RB26 and the chip select control end of the SOC chip,

[0137] The second ends of the resistors RB26, RB27, RB28, and RB29 are connected to the power supply +3.3VSW;

[0138] The digital bypass end DBYP of the DSP chip UR1 is connected to the first ends of the capacitors CR18, CR20, CR22, CR24, CR26, CR28, the first ends of the capacitors CR19, CR21, CR23, CR25, CR27, CR29; the first end of the capacitor CR30, the first end of the capacitor CR31, the first end of the capacitor CR32, the first end of the capacitor CR33, the first end of the capacitor CR34, the first end of the capacitor CR35, the first end of the capacitor CR36, the first end of the capacitor CR37;

[0139] The second ends of the capacitors CR19, CR21, CR23, CR25, CR27, CR29, and the first end of the inductor LR3 are connected to the power supply DSP_DVDD1V8_250MA; the second end of the inductor LR3 is connected to the first end of the capacitor CR29 and the power supply +1.8V; the second end of the capacitor CR29 is connected to the power supply ground;

[0140] The second ends of the capacitors CR30, CR31, CR32, CR33, CR34, CR35, CR36, CR37, and the first end of the inductor LR5 are connected to the power supply DSP_VIO1_3V3 / 1V8; the second end of the inductor LR5 is connected to the power supply +3.3VSW;

[0141] The second power input terminal VIO2 of the DSP chip UR1 is connected to the second ends of the capacitors CR18, CR20, CR22, CR24, CR26, CR28, the first end of the inductor LR4, and is connected to DSP_VIO2_3V3 / 1V8. The second end of the inductor LR4 is connected to the power supply +3.3VSW;

[0142] The data input terminal NC of the DSP chip UR1 is connected to the first end of the resistor RR29. The second end of the resistor RR29 is connected to the first end of the resistor RR50 and the data output terminal of the Bluetooth WIFI chip. The second end of the resistor RR50 is connected to the digital audio output terminal of the SOC chip.

[0143] The digital input frame synchronization terminal DIFS2 of the DSP chip UR1 is connected to the first end of the resistor RR28. The second end of the resistor RR28 is connected to the first end of the resistor RR51 and the frame synchronization clock signal output terminal of the Bluetooth WIFI chip. The second end of the resistor RR51 is connected to the clock signal output terminal of the SOC chip.

[0144] The digital input clock terminal DICLK2 of the DSP chip UR1 is connected to the first end of the resistor RR27. The second end of the resistor RR27 is connected to the first end of the resistor RR52 and the data clock signal output terminal of the Bluetooth WIFI chip. The second end of the resistor RR52 is connected to the clock signal control terminal of the SOC chip;

[0145] The first analog audio output terminal of the DSP chip UR1 is connected to the first end of the resistor RR23. The second end of the resistor RR23 is connected to the first ends of the capacitors CR17 and CR8. The second end of the capacitor CR17 is connected to the audio left channel input terminal of the AMP chip;

[0146] The first analog audio output terminal of the DSP chip UR1 is connected to the first end of the resistor RR22. The second end of the resistor RR22 is connected to the first ends of the capacitors CR16 and CR9. The second end of the capacitor CR16 is connected to the audio right channel input terminal of the AMP chip;

[0147] The third analog audio output terminal of the DSP chip UR1 is connected to the first end of the resistor RR21. The second end of the resistor RR21 is connected to the first end of the capacitor CR10;

[0148] The fourth analog audio output terminal of the DSP chip UR1 is connected to the first end of the resistor RR20. The second end of the resistor RR20 is connected to the first end of the capacitor CR11;

[0149] The second terminal of capacitor CR8, the second terminal of capacitor CR9, the second terminal of capacitor CR10, and the second terminal of capacitor CR11 are connected to the power ground;

[0150] The model of DSP chip UR1 is Si47920.

[0151] The power supply circuit of the DSP chip is as Figure 3 shown. It outputs two power supplies, power supply TUNER_RF and power supply CAMPOW +8V, where power supply TUNER_RF is used to supply power to the DSP chip. Specifically as follows:

[0152] The power input terminal IN of power supply chip U8, the first terminal of capacitor CD1, and the first terminal of capacitor C91 are connected to power supply +VBATT, and the second terminal of capacitor CD1 and the second terminal of capacitor C91 are connected to the power ground;

[0153] The first enable terminal EN1 of power supply chip U8 is connected to the first terminal of resistor RO9, and the second terminal of resistor RO9 is connected to the FM enable control terminal of the MCU chip.

[0154] The second enable terminal EN2 of power supply chip U8 is connected to the first terminal of resistor RO18, and the second terminal of resistor RO18 is connected to the camera enable control terminal of the MCU chip;

[0155] The power supply terminal VCC of power supply chip U8 is connected to the first terminal of capacitor CO8.

[0156] The first current sensing output terminal SENSE1 of power supply chip U8 is connected to the first terminal of resistor RO7 and the first terminal of capacitor CO6. The second terminal of resistor RO7, the second terminal of capacitor CO6, and the second terminal of capacitor CO8 are connected to the power ground;

[0157] The second current sensing output terminal SENSE2 of power supply chip U8 is connected to the first terminal of resistor RO8 and the first terminal of capacitor CO7; the second terminal of resistor RO8 and the second terminal of capacitor CO7 are connected to the power ground;

[0158] The enable control terminal SENSE_SEL of power supply chip U8 is connected to the first terminal of resistor RO10, and the second terminal of resistor RO10 is connected to the power ground.

[0159] The current sensing enable terminal SENSE_EN of power supply chip U8 is connected to the first terminal of resistor RO11, and the second terminal of resistor RO11 is connected to the power ground.

[0160] The first power output terminal OUT1 of the power supply chip U8 is connected to the first terminal of the inductor LD1 and the first terminal of the resistor RO13. The second terminal of the inductor LD1 is connected to the first terminal of the capacitor CD2, the first terminal of the capacitor CD3, and the first terminal of the inductor LD2. The second terminal of the inductor LD2 outputs the power supply TUNER_RF. The second terminals of the capacitor CD2 and the capacitor CD3 are connected to the power ground.

[0161] The first feedback terminal FB1 of the power supply chip U8 is connected to the second terminal of the resistor RO13 and the first terminal of the resistor RO15. The second terminal of the resistor RO15, the first terminal of the resistor RO17, the first terminal of the resistor RO16, and the first terminal of the resistor RO14 are connected to the power ground.

[0162] The first power output terminal OUT2 of the power supply chip U8 outputs the power supply CAMPOW + 8V and is connected to the first terminal of the resistor RO12, the first terminal of the capacitor CD6, and the first terminal of the capacitor CD5. The second terminals of the capacitor CD6 and the capacitor CD5 are connected to the power ground.

[0163] The first feedback terminal FB2 of the power supply chip U8 is connected to the second terminal of the resistor RO12 and the second terminal of the resistor RO17.

[0164] The ground terminal GND of the power supply chip U8 is connected to the power ground.

[0165] The first current limiting terminal LIM1 of the power supply chip U8 is connected to the second terminal of the resistor RO16.

[0166] The second current limiting terminal LIM2 of the power supply chip U8 is connected to the second terminal of the resistor RO14.

[0167] The model of the power supply chip U8 is TPS7B7702.

[0168] The circuit connection of the AMP chip (audio power amplifier chip) is as Figure 4 shown.

[0169] The mode selection terminal MODSEL of the AMP chip U9 is connected to the power ground.

[0170] The input terminal SDZ of the audio amplifier of the AMP chip U9 and the fault terminal FAULTZ of the AMP chip U9 are connected to the first terminals of the resistor R129 and the resistor R130. The second terminal of the resistor R129 is connected to the control terminal of the MCU chip. The second terminal of the resistor R130 is connected to the power ground.

[0171] The positive audio input terminal RINP of the right channel of the AMP chip U9 is connected to the first terminal of the capacitor C94. The second terminal of the capacitor C94 is connected to the first terminal of the resistor R128 and the audio right channel data output terminal of the DSP chip. The second terminal of the resistor R128 is connected to the ADC signal right channel output terminal of the SOC chip;

[0172] The negative audio input terminal RINN of the right channel of the AMP chip U9 is connected to the first terminal of the capacitor C95;

[0173] The power limit terminal PLIMIT of the AMP chip U9 is connected to the first terminal of the resistor R126 and the first terminal of the resistor R127;

[0174] The internal power supply terminal GVDD of the AMP chip U9 is connected to the second terminal of the resistor R127, the first terminal of the resistor R42, and the first terminal of the capacitor C92;

[0175] The selectable gain terminal GAIN / SLV of the AMP chip U9 is connected to the second terminal of the resistor R42 and the first terminal of the resistor R43;

[0176] The ground terminal GND of the AMP chip U9, the second terminal of the capacitor C95, the second terminal of the resistor R126, the second terminal of the capacitor C92, and the second terminal of the resistor R43 are connected to the power ground;

[0177] The positive audio input terminal LINP of the left channel of the AMP chip U9 is connected to the first terminal of the capacitor C93. The second terminal of the capacitor C93 is connected to the first terminal of the resistor R125 and the audio left channel data output terminal of the DSP chip. The second terminal of the resistor R125 is connected to the ADC signal right channel output terminal of the SOC chip;

[0178] The negative audio input terminal LINN of the left channel of the AMP chip U9 is connected to the first terminal of the capacitor C96, and the second terminal of the capacitor C96 is connected to the power ground;

[0179] The mute control terminal MUTE of the AMP chip U9 is connected to the mute control terminal of the MCU chip and the first terminal of the resistor R45. The second terminal of the resistor R45 is connected to the power +5VCAN;

[0180] The AM modulation frequency terminal AM2 of the AMP chip U9 is connected to the power ground;

[0181] The AM modulation frequency terminal AM1 of the AMP chip U9 is connected to the power ground;

[0182] The AM modulation frequency terminal AMO of the AMP chip U9 is connected to the AM modulation frequency terminal of the MCU chip;

[0183] The power supply terminal AVCC of the AMP chip U9, the power supply terminal PVCC of the AMP chip U9, the power supply terminal PVCC of the AMP chip U9, the first terminal of the capacitor CR62, the first terminal of the capacitor C104, the first terminal of the capacitor C106, and the positive electrode of the polarized capacitor C106 are connected to the power supply +VBATT; the second terminal of the capacitor CR62, the second terminal of the capacitor C104, the second terminal of the capacitor C106, and the positive electrode of the polarized capacitor C106 are connected to the power supply ground;

[0184] The bootstrap terminal BSNL of the left-channel negative output of the AMP chip U9 is connected to the first terminal of the capacitor C103. The second terminal of the capacitor C103 is connected to the left-channel negative output terminal OUTNL of the AMP chip U9 and the first terminal of the inductor L10. The second terminal of the inductor L10 outputs the left-channel negative pole and is connected to the first terminal of the capacitor C111, the first terminal of the capacitor C115, and the first terminal of the resistor R50. The second terminal of the resistor R50 is connected to the first terminal of the capacitor C118. The second terminal of the capacitor C118 is connected to the power supply ground; the second terminals of the capacitor C111 and the capacitor C115 are connected to the power supply ground;

[0185] The ground terminal GND of the AMP chip U9 is connected to the power supply ground;

[0186] The left-channel positive output terminal OUTPL of the AMP chip U9 is connected to the first terminal of the capacitor C102 and the first terminal of the inductor L9. The second terminal of the inductor L9 outputs the left-channel positive pole and is connected to the first terminal of the capacitor C109, the first terminal of the capacitor C113, and the first terminal of the resistor R49. The second terminal of the resistor R49 is connected to the first terminal of the capacitor C117. The second terminal of the capacitor C117 is connected to the power supply ground; the second terminals of the capacitor C109 and the capacitor C113 are connected to the power supply ground;

[0187] The bootstrap terminal BSPL of the left-channel positive output of the AMP chip U9 is connected to the second terminal of the capacitor C102,

[0188] The bootstrap terminal BSNR of the negative right-channel output of the AMP chip U9 is connected to the first terminal of the capacitor C101. The second terminal of the capacitor C101 is connected to the negative right-channel output terminal OUTNR of the AMP chip U9 and the first terminal of the inductor L12. The second terminal of the inductor L12 outputs the right-channel negative pole and is connected to the first terminal of the capacitor C110, the first terminal of the capacitor C114, and the first terminal of the resistor R48. The second terminal of the resistor R48 is connected to the first terminal of the capacitor C119. The second terminal of the capacitor C119 is connected to the power supply ground; the second terminals of the capacitor C110 and the capacitor C114 are connected to the power supply ground;

[0189] The positive right-channel output terminal OUTPR of the AMP chip U9 is connected to the first terminal of the capacitor C99 and the first terminal of the inductor L11. The second terminal of the inductor L11 outputs the positive pole of the right channel and is connected to the first terminal of the capacitor C108, the first terminal of the capacitor C112, and the first terminal of the resistor R47. The second terminal of the resistor R47 is connected to the first terminal of the capacitor C116, and the second terminal of the capacitor C116 is connected to the power ground. The second terminals of the capacitor C108 and the capacitor C112 are connected to the power ground.

[0190] The bootstrap terminal BSPR of the positive right-channel output of the AMP chip U9 is connected to the second terminal of the capacitor C99.

[0191] The power supply terminal PVCC of the AMP chip U9, the first terminal of the resistor R46, the first terminal of the capacitor CR61, the first terminal of the capacitor C98, the first terminal of the capacitor C100, and the positive pole of the polarized capacitor C105 are connected to the power supply +VBATT. The second terminal of the resistor R46 is connected to the first terminal of the capacitor C97, and the second terminal of the capacitor C97 is connected to the power ground. The second terminals of the capacitor CR61, the capacitor C98, the capacitor C100, and the negative pole of the polarized capacitor C105 are connected to the power ground.

[0192] The model of the AMP chip U9 is TPA3116.

[0193] By applying a DSP (Digital Signal Processor) and an AMP (Audio Power Amplifier), the FM radio of the present utility model has achieved the following functional improvements: The DSP effectively filters out electromagnetic interference and noise in the environment, ensuring stable reception of radio signals. At the same time, it optimizes the spectrum of the audio signal, improving the accuracy and integrity of the sound signal. The AMP enhances the output power of the radio, ensuring that the audio signal can fully drive the speaker and achieve clear and powerful sound playback. The combination of these technologies not only improves the signal reception ability of the FM radio but also improves the sound quality and the effect of sound output.

[0194] Although the embodiments of the present utility model have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and purposes of the present utility model. The scope of the present utility model is defined by the claims and their equivalents.

Claims

1. An FM radio management circuit, characterized in that, Including: SOC chip, AMP chip, DSP chip, FM socket; The radio frequency signal output end of the FM socket is connected to the radio frequency signal input end of the DSP chip through a frequency selection circuit, and the frequency selection circuit includes a frequency modulation circuit and / or an amplitude modulation circuit; the communication data transmission end of the DSP chip is connected to the communication data transmission end of the SOC chip, and the audio signal output end of the DSP chip is connected to the audio signal input end of the AMP chip.

2. The FM radio management circuit according to claim 1, characterized in that The frequency modulation circuit includes: The frequency modulation input end FMI of the DSP chip UR1 is connected to the first end of the capacitor CR5, the first end of the inductor LR1, and the first end of the inductor LR2. The second end of the inductor LR2 and the second end of the capacitor CR5 are respectively connected to the power ground; the second end of the inductor LR1 is connected to the first end of the capacitor CR4, and the second end of the capacitor CR4 is connected to the radio frequency signal output end of the FM socket.

3. The FM radio management circuit according to claim 1, characterized in that The amplitude modulation circuit includes: The radio frequency signal output end of the FM socket is connected to the first end of the capacitor CR3. The second end of the capacitor CR3 is connected to the first end of the inductor LR6 and the first end of the capacitor CR38; the second end of the inductor LR6 and the second end of the capacitor CR38 are connected to the first end of the capacitor CR39, the first end of the transient diode LTVS18, and the input end of the band-pass filter circuit. The output end of the band-pass filter circuit is connected to the first end of the capacitor CR41; the band-pass filter circuit includes: a parallel connection of the resistor RR31, the inductor LR8, and the capacitor CR40; The second end of the capacitor CR39 is connected to the first end of the inductor LR7, and the second end of the inductor LR7 is connected to the power ground; the second end of the transient diode LTVS18 is connected to the power ground; The second end of the capacitor CR41 is connected to the amplitude modulation input end AMI of the DSP chip UR1.

4. The FM radio management circuit according to claim 1, wherein, The circuit connection of the DSP chip includes: The channel selection end ABYP of the DSP chip UR1 is connected to the first end of the capacitor CR42, the first end of the capacitor CR43, the first end of the capacitor CR44, the first end of the capacitor CR45, the first end of the capacitor CR46, and the first end of the inductor LR9. The second end of the inductor LR9 is connected to the power +3.3VSW; The positive analog input end AIN0P of the DSP chip UR1 is connected to the first end of the capacitor CR47, and the second end of the capacitor CR47 is connected to the first end of the resistor RR35. The negative analog input end AIN0N of the DSP chip UR1 and the first end of the capacitor CR48 are connected. The second end of the capacitor CR48 is connected to the first end of the capacitor CR50, the first end of the capacitor CR52, the first end of the capacitor CR54, the first end of the capacitor CR55, the first end of the capacitor CR56, the first end of the capacitor CR57, the first end of the capacitor CR58, and the first end of the capacitor CR60 and is connected to the power ground. The positive analog input end AIN1P of the DSP chip UR1 is connected to the first end of the capacitor CR49, and the second end of the capacitor CR49 is connected to the first end of the resistor RR36. The negative analog input end AIN1N of the DSP chip UR1 is connected to the second end of the capacitor CR50. The positive analog input terminal AIN2P of the DSP chip UR1 is connected to the first terminal of the capacitor CR51. The second terminal of the capacitor CR51 is connected to the first terminal of the resistor RR32. The second terminal of the resistor RR32 is connected to the first terminal of the capacitor C140. The second terminal of the capacitor C140 is respectively connected to the signal transmission terminal of the AMP chip and the signal transmission terminal of the SOC chip; The negative analog input terminal AIN2N of the DSP chip UR1 is connected to the second terminal of the capacitor CR52; The positive analog input terminal AIN3P of the DSP chip UR1 is connected to the first terminal of the capacitor CR53. The second terminal of the capacitor CR53 is connected to the first terminal of the resistor RR33. The second terminal of the resistor RR33 is connected to the first terminal of the capacitor C141. The second terminal of the capacitor C141 is respectively connected to the signal transmission terminal of the AMP chip and the signal transmission terminal of the SOC chip; The negative analog input terminal AIN3N of the DSP chip UR1 is connected to the second terminal of the capacitor CR54; The positive analog input terminal AIN4P of the DSP chip UR1 is connected to the second terminal of the capacitor CR55; The negative analog input terminal AIN4N of the DSP chip UR1 is connected to the second terminal of the capacitor CR56; The positive analog input terminal AIN5P of the DSP chip UR1 is connected to the second terminal of the capacitor CR57; The negative analog input terminal AIN5N of the DSP chip UR1 is connected to the second terminal of the capacitor CR58 and the first terminal of the resistor RR39; The positive analog input terminal AIN6P of the DSP chip UR1 is connected to the second terminal of the resistor RR39 and the first terminal of the capacitor CR59. The second terminal of the capacitor CR59 is connected to the first terminal of the resistor RR34; The negative analog input terminal AIN6N of the DSP chip UR1 is connected to the second terminal of the capacitor CR60; The second terminals of the resistors RR35, RR36, RR37, RR38, and RR34 are connected to the power ground; The reset signal terminal RSTB of the DSP chip UR1 is connected to the first terminal of the resistor RR42 and the reset control terminal of the SOC chip; The mode selection terminal SMODE of the DSP chip UR1 is connected to the first terminals of the resistors RR40 and RR43. The second terminal of the resistor RR40 is connected to the power ground; The interrupt request terminal INTB of the DSP chip UR1 is connected to the first terminal of the resistor RR41 and the interrupt request data terminal of the SOC chip; The second terminals of the resistors RR41, RR42, and RR43 are connected to the power DSP_VIO1_3V3 / 1V8; The data output terminal MISO / A0 of the DSP chip UR1 is connected to the first terminal of the resistor RB33. The second terminal of the resistor RB33 is connected to the first terminal of the resistor RB29 and the data receiving terminal of the SOC chip; The data receiving terminal MOSI / SDA of the DSP chip UR1 is connected to the first terminal of the resistor RB32. The second terminal of the resistor RB32 is connected to the first terminal of the resistor RB28 and the data output terminal of the SOC chip; The clock terminal SCLK / SCL of the DSP chip UR1 is connected to the first end of the resistor RB31, and the second end of the resistor RB31 is connected to the first end of the resistor RB27 and the clock control terminal of the SOC chip. The chip select signal receiving terminal SSB / A1 of the DSP chip UR1 is connected to the first end of the resistor R0.1B30, and the second end of the resistor RB30 is connected to the first end of the resistor RB26 and the chip select control terminal of the SOC chip. The second ends of the resistors RB26, RB27, RB28, and RB29 are connected to the power supply +3.3VSW. The digital bypass terminal DBYP of the DSP chip UR1 is connected to the first ends of the capacitors CR18, CR20, CR22, CR24, CR26, CR28, the first ends of the capacitors CR19, CR21, CR23, CR25, CR27, CR29; the first end of the capacitor CR30, the first end of the capacitor CR31, the first end of the capacitor CR32, the first end of the capacitor CR33, the first end of the capacitor CR34, the first end of the capacitor CR35, the first end of the capacitor CR36, the first end of the capacitor CR37. The second ends of the capacitors CR19, CR21, CR23, CR25, CR27, CR29, and the first end of the inductor LR3 are connected to the power supply DSP_DVDD1V8_250MA; the second end of the inductor LR3 is connected to the first end of the capacitor CR29 and the power supply +1.8V; the second end of the capacitor CR29 is connected to the power ground. The second ends of the capacitors CR30, CR31, CR32, CR33, CR34, CR35, CR36, CR37, and the first end of the inductor LR5 are connected to the power supply DSP_VIO1_3V3 / 1V8; the second end of the inductor LR5 is connected to the power supply +3.3VSW. The second power input terminal VIO2 of the DSP chip UR1 is connected to the second ends of the capacitors CR18, CR20, CR22, CR24, CR26, CR28, and the first end of the inductor LR4 is connected to DSP_VIO2_3V3 / 1V8, and the second end of the inductor LR4 is connected to the power supply +3.3VSW. The data input terminal NC of the DSP chip UR1 is connected to the first end of the resistor RR29, the second end of the resistor RR29 is connected to the first end of the resistor RR50 and the data output terminal of the Bluetooth WIFI chip, and the second end of the resistor RR50 is connected to the digital audio output terminal of the SOC chip. The digital input frame synchronization terminal DIFS2 of the DSP chip UR1 is connected to the first end of the resistor RR28. The second end of the resistor RR28 is connected to the first end of the resistor RR51 and the frame synchronization clock signal output terminal of the Bluetooth WIFI chip. The second end of the resistor RR51 is connected to the clock signal output terminal of the SOC chip. The digital input clock terminal DICLK2 of the DSP chip UR1 is connected to the first end of the resistor RR27. The second end of the resistor RR27 is connected to the first end of the resistor RR52 and the data clock signal output terminal of the Bluetooth WIFI chip. The second end of the resistor RR52 is connected to the clock signal control terminal of the SOC chip. The first analog audio output terminal of the DSP chip UR1 is connected to the first end of the resistor RR23. The second end of the resistor RR23 is connected to the first end of the capacitor CR17 and the first end of the capacitor CR8. The second end of the capacitor CR17 is connected to the audio left channel input terminal of the AMP chip. The first analog audio output terminal of the DSP chip UR1 is connected to the first end of the resistor RR22. The second end of the resistor RR22 is connected to the first end of the capacitor CR16 and the first end of the capacitor CR9. The second end of the capacitor CR16 is connected to the audio right channel input terminal of the AMP chip. The third analog audio output terminal of the DSP chip UR1 is connected to the first end of the resistor RR21. The second end of the resistor RR21 is connected to the first end of the capacitor CR10. The fourth analog audio output terminal of the DSP chip UR1 is connected to the first end of the resistor RR20. The second end of the resistor RR20 is connected to the first end of the capacitor CR11. The second ends of the capacitor CR8, the capacitor CR9, the capacitor CR10, and the capacitor CR11 are connected to the power ground.

5. The FM radio management circuit according to claim 1, wherein The radio frequency signal output terminal of the FM socket, the second end of the capacitor CR2, and the first end of the transient diode LTVS17 are connected to the power supply TUNER_RF. The second end of the transient diode LTVS17 is connected to the power ground. The power supply TUNER_RF is provided by the power supply chip U8. The power input terminal IN of the power supply chip U8, the first end of the capacitor CD1, and the first end of the capacitor C91 are connected to the power supply +VBATT. The second end of the capacitor CD1 and the second end of the capacitor C91 are connected to the power ground. The first enable terminal EN1 of the power supply chip U8 is connected to the first end of the resistor RO9. The second end of the resistor RO9 is connected to the FM enable control terminal of the MCU chip. The second enable terminal EN2 of the power supply chip U8 is connected to the first end of the resistor RO18. The second end of the resistor RO18 is connected to the camera enable control terminal of the MCU chip. The power supply terminal VCC of the power supply chip U8 is connected to the first end of the capacitor CO8. The first current sensing output terminal SENSE1 of the power supply chip U8 is connected to the first end of the resistor RO7 and the first end of the capacitor CO6. The second end of the resistor RO7, the second end of the capacitor CO6, and the second end of the capacitor CO8 are connected to the power ground. The first current sensing output terminal SENSE2 of the power supply chip U8 is connected to the first terminal of the resistor RO8 and the first terminal of the capacitor CO7; the second terminal of the resistor RO8 and the second terminal of the capacitor CO7 are connected to the power ground; The enable control terminal SENSE_SEL of the power supply chip U8 is connected to the first terminal of the resistor RO10, and the second terminal of the resistor RO10 is connected to the power ground. The current sensing enable terminal SENSE_EN of the power supply chip U8 is connected to the first terminal of the resistor RO11, and the second terminal of the resistor RO11 is connected to the power ground. The first power output terminal OUT1 of the power supply chip U8 is connected to the first terminal of the inductor LD1 and the first terminal of the resistor RO13. The second terminal of the inductor LD1 is connected to the first terminal of the capacitor CD2, the first terminal of the capacitor CD3, and the first terminal of the inductor LD2; the second terminal of the inductor LD2 outputs the power supply TUNER_RF; the second terminals of the capacitor CD2 and the capacitor CD3 are connected to the power ground; The first feedback terminal FB1 of the power supply chip U8 is connected to the second terminal of the resistor RO13 and the first terminal of the resistor RO15. The second terminal of the resistor RO15, the first terminal of the resistor RO17, the first terminal of the resistor RO16, and the first terminal of the resistor RO14 are connected to the power ground; The first power output terminal OUT2 of the power supply chip U8 outputs the power supply CAMPOW +8V and is connected to the first terminal of the resistor RO12, the first terminal of the capacitor CD6, and the first terminal of the capacitor CD5; the second terminals of the capacitor CD6 and the capacitor CD5 are connected to the power ground; The first feedback terminal FB2 of the power supply chip U8 is connected to the second terminal of the resistor RO12 and the second terminal of the resistor RO17; The ground terminal GND of the power supply chip U8 is connected to the power ground; The first current limiting terminal LIM1 of the power supply chip U8 is connected to the second terminal of the resistor RO16; The second current limiting terminal LIM2 of the power supply chip U8 is connected to the second terminal of the resistor RO14.

6. The FM radio management circuit according to claim 1, characterized in that, The audio signal output terminal of the DSP chip is connected to the audio signal input terminal of the AMP chip, including: The mode selection terminal MODSEL of the AMP chip U9 is connected to the power ground; The input terminal SDZ of the audio amplifier of the AMP chip U9 and the fault terminal FAULTZ of the AMP chip U9 are connected to the first terminal of the resistor R129 and the first terminal of the resistor R130; the second terminal of the resistor R129 is connected to the control terminal of the MCU chip; the second terminal of the resistor R130 is connected to the power ground; The right channel positive audio input terminal RINP of the AMP chip U9 is connected to the first terminal of the capacitor C94. The second terminal of the capacitor C94 is connected to the first terminal of the resistor R128 and the audio right channel data output terminal of the DSP chip. The second terminal of the resistor R128 is connected to the right channel output terminal of the SOC chip ADC signal; The right channel negative audio input terminal RINN of the AMP chip U9 is connected to the first terminal of the capacitor C95; The power limit terminal PLIMIT of the AMP chip U9 is connected to the first terminal of the resistor R126 and the first terminal of the resistor R127; The internal power supply terminal GVDD of the AMP chip U9 is connected to the second terminal of the resistor R127, the first terminal of the resistor R42, and the first terminal of the capacitor C92; The selectable gain terminal GAIN / SLV of the AMP chip U9 is connected to the second terminal of the resistor R42 and the first terminal of the resistor R43; The ground terminal GND of the AMP chip U9, the second terminal of the capacitor C95, the second terminal of the resistor R126, the second terminal of the capacitor C92, and the second terminal of the resistor R43 are connected to the power supply ground; The positive audio input terminal LINP of the left channel of the AMP chip U9 is connected to the first terminal of the capacitor C93. The second terminal of the capacitor C93 is connected to the first terminal of the resistor R125 and the audio left channel data output terminal of the DSP chip. The second terminal of the resistor R125 is connected to the right channel output terminal of the ADC of the SOC chip; The negative audio input terminal LINN of the left channel of the AMP chip U9 is connected to the first terminal of the capacitor C96. The second terminal of the capacitor C96 is connected to the power supply ground; The mute control terminal MUTE of the AMP chip U9 is connected to the mute control terminal of the MCU chip and the first terminal of the resistor R45. The second terminal of the resistor R45 is connected to the power supply +5VCAN; The AM2 terminal of the AM frequency of the AMP chip U9 is connected to the power supply ground; The AM1 terminal of the AM frequency of the AMP chip U9 is connected to the power supply ground; The AMO terminal of the AM frequency of the AMP chip U9 is connected to the AM frequency terminal of the MCU chip; The power supply terminal AVCC of the AMP chip U9, the power supply terminal PVCC of the AMP chip U9, the power supply terminal PVCC of the AMP chip U9, the first terminal of the capacitor CR62, the first terminal of the capacitor C104, the first terminal of the capacitor C106, and the positive electrode of the polarized capacitor C106 are connected to the power supply +VBATT; The second terminal of the capacitor CR62, the second terminal of the capacitor C104, the second terminal of the capacitor C106, and the negative electrode of the polarized capacitor C106 are connected to the power supply ground; The bootstrap terminal BSNL of the negative output of the left channel of the AMP chip U9 is connected to the first terminal of the capacitor C103. The second terminal of the capacitor C103 is connected to the negative output terminal OUTNL of the left channel of the AMP chip U9 and the first terminal of the inductor L10. The second terminal of the inductor L10 outputs the negative electrode of the left channel and is connected to the first terminal of the capacitor C111, the first terminal of the capacitor C115, and the first terminal of the resistor R50. The second terminal of the resistor R50 is connected to the first terminal of the capacitor C118. The second terminal of the capacitor C118 is connected to the power supply ground; The second terminal of the capacitor C111 and the second terminal of the capacitor C115 are connected to the power supply ground; The ground terminal GND of the AMP chip U9 is connected to the power supply ground; The positive output terminal OUTPL of the left channel of the AMP chip U9 is connected to the first terminal of the capacitor C102 and the first terminal of the inductor L9. The second terminal of the inductor L9 outputs the positive electrode of the left channel and is connected to the first terminal of the capacitor C109, the first terminal of the capacitor C113, and the first terminal of the resistor R49. The second terminal of the resistor R49 is connected to the first terminal of the capacitor C117. The second terminal of the capacitor C117 is connected to the power supply ground; The second terminal of the capacitor C109 and the second terminal of the capacitor C113 are connected to the power supply ground; The bootstrap terminal BSPL of the positive output of the left channel of the AMP chip U9 is connected to the second terminal of the capacitor C102. The bootstrap terminal BSNR of the negative right channel output of the AMP chip U9 is connected to the first terminal of the capacitor C101. The second terminal of the capacitor C101 is connected to the negative right channel output terminal OUTNR of the AMP chip U9 and the first terminal of the inductor L12. The second terminal of the inductor L12 outputs the negative pole of the right channel and is connected to the first terminal of the capacitor C110, the first terminal of the capacitor C114, and the first terminal of the resistor R48. The second terminal of the resistor R48 is connected to the first terminal of the capacitor C119. The second terminal of the capacitor C119 is connected to the power ground. The second terminals of the capacitor C110 and the capacitor C114 are connected to the power ground. The positive right channel output terminal OUTPR of the AMP chip U9 is connected to the first terminal of the capacitor C99 and the first terminal of the inductor L11. The second terminal of the inductor L11 outputs the positive pole of the right channel and is connected to the first terminal of the capacitor C108, the first terminal of the capacitor C112, and the first terminal of the resistor R47. The second terminal of the resistor R47 is connected to the first terminal of the capacitor C116. The second terminal of the capacitor C116 is connected to the power ground. The second terminals of the capacitor C108 and the capacitor C112 are connected to the power ground. The bootstrap terminal BSPR of the positive right channel output of the AMP chip U9 is connected to the second terminal of the capacitor C99. The power supply terminal PVCC of the AMP chip U9, the first terminal of the resistor R46, the first terminal of the capacitor CR61, the first terminal of the capacitor C98, the first terminal of the capacitor C100, and the positive pole of the polarized capacitor C105 are connected to the power supply +VBATT. The second terminal of the resistor R46 is connected to the first terminal of the capacitor C97. The second terminal of the capacitor C97 is connected to the power ground. The second terminals of the capacitor CR61, the capacitor C98, the capacitor C100, and the negative pole of the polarized capacitor C105 are connected to the power ground.

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