Loudspeaker test simulation device
Through the speaker test simulation device, the interface module, simulation module and data transmission module are used to simulate the test motherboard, which solves the problem of high price and large size of the speaker equipment, and achieves low-cost and efficient testing results.
Patent Information
- Application Number
- CN202421626308.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-10
- Publication Date
- 2025-07-04
- Estimated Expiration
- 2034-07-10
AI Technical Summary
In the existing speaker testing methods, speaker equipment is expensive and large in size, making it difficult to integrate into automated testing equipment, and some parameters cannot be measured, resulting in low applicability and testing efficiency.
The speaker test simulation device is adopted, including the test simulation motherboard, the motherboard to be tested and the upper computer. The analog sound signal of the motherboard to be tested is simulated through the interface module, the simulation module and the data transmission module, and the test data is obtained through the data transmission module, and the upper computer is used to perform automatic evaluation of the test data.
It reduces material costs, improves test applicability and efficiency, and realizes the testing of all parameters in the analog sound signal, which is suitable for integration in automated testing equipment.
Smart Images
Figure CN223067193U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of motherboard testing, and particularly relates to a loudspeaker test simulation device. Background Art
[0002] With the continuous development of science and technology, the functions of electronic products are becoming more and more abundant. As an essential functional device for electronic products such as computers and mobile phones, the performance of the loudspeaker can better reflect the quality of the electronic product and enhance the sensory experience. Therefore, how to ensure the normal function of the loudspeaker on the computer or mobile phone motherboard has put forward higher and higher requirements for the testing industry.
[0003] For the existing loudspeaker function testing, real loudspeaker devices are used for testing. The loudspeaker device is externally connected to the motherboard to drive the loudspeaker device to emit sound. However, under such testing conditions, many sound parameters cannot be tested. Therefore, the existing testing method has the problems of high cost of the loudspeaker device and high material cost, large volume of the loudspeaker device which is not conducive to integration in the automated testing equipment, and some parameters cannot be measured, resulting in lower applicability and testing efficiency. Content of the Utility Model
[0004] The utility model provides a loudspeaker test simulation device, aiming at solving the problems in the prior art that the loudspeaker device is expensive and the material cost is high, the loudspeaker device has a large volume and is not conducive to integration in the automated testing equipment, and some parameters cannot be measured, resulting in lower applicability and testing efficiency.
[0005] To solve the above problems, the utility model proposes a loudspeaker test simulation device for testing a motherboard to be tested, including: a test simulation motherboard, a motherboard to be tested, and a host computer; the test simulation motherboard includes an interface module, a simulation module, and a data transmission module; the simulation module and the data transmission module are connected to the motherboard to be tested through the interface module; the host computer is connected to the motherboard to be tested and the data transmission module; wherein, when the simulation module and the data transmission module are connected to the motherboard to be tested through the interface module, and the motherboard to be tested and the data transmission module receive the start test instruction sent by the host computer, the simulation module is used to perform loudspeaker simulation on the simulated sound signal sent by the motherboard to be tested; the data transmission module is used to obtain test data from the simulated sound signal and transmit it to the host computer; the host computer is used to test whether the test data is qualified.
[0006] Compared with the prior art, the present utility model provides a loudspeaker test simulation device for testing a main board to be tested, including: a test simulation main board, a main board to be tested, and a host computer; the test simulation main board includes an interface module, a simulation module, and a data transmission module; the simulation module and the data transmission module are connected to the main board to be tested through the interface module; the host computer is connected to the main board to be tested and the data transmission module; wherein, when the simulation module and the data transmission module are connected to the main board to be tested through the interface module, and the main board to be tested and the data transmission module receive a start test instruction sent by the host computer, the simulation module is used to perform loudspeaker simulation on the simulated sound signal sent by the main board to be tested; the data transmission module is used to obtain test data from the simulated sound signal and transmit it to the host computer; the host computer is used to test whether the test data is qualified. By implementing the embodiments of the present utility model, it is realized to test whether the test data obtained from the simulated sound signal of the main board to be tested is qualified, so as to reduce the material cost, test all parameters in the simulated sound signal, improve the applicability, and improve the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0008] Figure 1 It is a schematic block diagram of a loudspeaker test simulation device provided by an embodiment of the present utility model;
[0009] Figure 2 It is a schematic circuit diagram of a control signal circuit provided by an embodiment of the present utility model;
[0010] Figure 3 It is a schematic circuit diagram of an analog circuit provided by an embodiment of the present utility model;
[0011] Figure 4 It is a schematic circuit diagram of a first transmission circuit provided by an embodiment of the present utility model;
[0012] Figure 5 It is a schematic circuit diagram of a second transmission circuit provided by an embodiment of the present utility model;
[0013] Figure 6 It is a schematic circuit diagram of a third transmission circuit provided by an embodiment of the present utility model;
[0014] Figure 7The schematic circuit diagram of the interface module provided by an embodiment of the present utility model;
[0015] Figure 8 The schematic circuit diagram of the power conversion module provided by an embodiment of the present utility model.
[0016] Among them, the reference numerals in the figure are as follows:
[0017] 1. Speaker test simulation device; 10. Test simulation main board; 11. Interface module; 12. Simulation module; 13. Data transmission module; 20. Main board to be tested; 30. Host computer. Specific embodiments
[0018] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.
[0019] The directional terms mentioned in the present utility model, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., are only references to the directions in the attached drawings. Therefore, the directional terms used are for explaining and understanding the present utility model, rather than for limiting the present utility model. In addition, in the drawings, structures that are similar or the same are denoted by the same reference numerals.
[0020] It should be understood that when used in this specification and the appended claims, the terms "comprises" and "comprising" indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.
[0021] It should also be understood that the terms used in the specification of the present utility model are only for the purpose of describing specific embodiments and are not intended to limit the present utility model. As used in the specification of the present utility model and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms.
[0022] It should be further understood that the term " / and / " used in the specification of the present utility model and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.
[0023] Please refer to Figures 1 to 8, the present utility model provides a loudspeaker test simulation device 1 for testing a main board 20 to be tested, including: a test simulation main board 10, a main board 20 to be tested, and a host computer 30; the test simulation main board 10 includes an interface module 11, a simulation module 12, and a data transmission module 13; the simulation module 12 and the data transmission module 13 are connected to the main board 20 to be tested through the interface module 11; the host computer 30 is connected to the main board 20 to be tested and the data transmission module 13;
[0024] Wherein, when the simulation module 12 and the data transmission module 13 are connected to the main board 20 to be tested through the interface module 11, and the main board 20 to be tested and the data transmission module 13 receive a start test instruction sent by the host computer 30, the simulation module 12 is used to perform loudspeaker simulation on the analog sound signal sent by the main board 20 to be tested; the data transmission module 13 is used to obtain test data from the analog sound signal and transmit it to the host computer 30; the host computer 30 is used to test whether the test data is qualified.
[0025] In this embodiment, as Figure 1 shown, the main board 20 to be tested includes a system-on-chip (SOC for short, system-level chip) and a power amplifier chip.
[0026] After the simulation module 12 and the data transmission module 13 are connected to the main board 20 to be tested through the interface module 11, and the host computer 30 is connected to the main board 20 to be tested and the data transmission module 13, that is, when ensuring that the loudspeaker test simulation device 1 is connected normally and the communication runs normally; when the main board 20 to be tested receives a start test instruction sent by the host computer 30, the system chip starts to work and sends a digital sound signal to the power amplifier chip through an I2S (Inter-IC Sound, abbreviated as I2S) bus; after receiving the digital sound signal, the power amplifier chip converts the digital sound signal into an analog sound signal; the analog sound signal enters the test simulation main board 10 through the interface module 11, and after passing through the simulation module 12 (equivalent to a loudspeaker), it returns to the power amplifier chip, thereby forming a data loop to perform loudspeaker simulation on the main board 20 to be tested so that the data transmission module 13 obtains the test data from the obtained analog sound signal.
[0027] Specifically, the simulation module 12 performs speaker simulation on the analog sound signal sent by the main board 20 to be tested through the interface module 11, so that the data transmission module 13 obtains test data from the analog sound signal; the data transmission module 13 transmits the test data to the host computer 30; the host computer 30 tests whether the test data is qualified.
[0028] Through the above embodiments, it can be seen that the simulation module 12 performs speaker simulation on the analog sound signal sent by the main board 20 to be tested through the interface module 11, so that the data transmission module 13 obtains test data from the analog sound signal; the data transmission module 13 transmits the test data to the host computer 30; the host computer 30 tests whether the test data is qualified, which can realize the automatic test of whether the test data obtained from the analog sound signal is qualified; moreover, the material cost of the test simulation main board 10 is low and the volume is small. Therefore, the material cost is reduced, which is beneficial to integration into the automatic test equipment, and all parameters in the analog sound signal can be tested, thereby improving the applicability and test efficiency.
[0029] In one embodiment, as Figures 1 to 3 shown, the simulation module 12 includes a control signal circuit and an analog circuit; the control signal circuit is connected to the analog circuit; the control signal circuit is also connected to the data transmission module 13; the analog circuit is further connected to the main board 20 to be tested through the interface module 11; when the host computer 30 sends an instruction to the control signal circuit through the interface module 11 and the data transmission module 13, the control signal circuit outputs a driving signal to the analog circuit to perform speaker simulation on the main board 20 to be tested.
[0030] In this embodiment, as Figures 1 to 3 shown, when the host computer 30 sends an instruction to the control signal circuit through the interface module 11 and the data transmission module 13, the control signal circuit outputs a driving signal to the analog circuit to perform speaker simulation.
[0031] Specifically, the host computer 30 sends a start test instruction to the main board 20 to be tested through the interface module 11, and the system chip in the main board 20 to be tested sends a digital sound signal to the power amplifier chip through the I2S bus; after receiving the digital sound signal, the power amplifier chip converts the digital sound signal into the analog sound signal; the analog sound signal enters the test simulation main board 10 through the interface module 11.
[0032] Meanwhile, the host computer 30 sends a start test instruction to the analog module 12 through the data transmission module 13; after receiving the instruction, the control signal circuit outputs the drive signal with a low potential to the analog circuit; the analog circuit starts to work according to the drive signal, obtains the analog sound signal through the interface module 11 and enters the circuit, and returns the analog sound signal to the power amplifier chip through the interface module 11 to form a data loop, so as to perform speaker simulation on the analog sound signal in the analog circuit.
[0033] Through the above embodiments, it can be seen that when the host computer 30 sends an instruction to the control signal circuit through the interface module 11 and the data transmission module 13, the control signal circuit outputs a drive signal to the analog circuit to perform speaker simulation on the motherboard 20 to be tested, realizing speaker simulation on the analog sound signal sent by the motherboard 20 to be tested, and there is no need for a speaker device to perform the test. Therefore, the material cost is reduced, which is beneficial to integration into an automated test device and improves the test adaptability.
[0034] In one embodiment, as Figures 1 to 2 shown, the control signal circuit includes a control chip U1, a first capacitor C1, a first resistor R1, a second resistor R2, a third resistor R3, an amplifier chip U2 and a second capacitor C2 connected; the second pin of the control chip U1 is connected to the first end of the second resistor R2; the third pin of the control chip U1 is connected to the first end of the third resistor R3; the fourth pin, fifth pin, sixth pin and seventh pin of the control chip U1 are respectively connected to the first pin, second pin, third pin and fourth pin of the amplifier chip U2 correspondingly; the eighth pin, ninth pin and tenth pin of the control chip U1 are connected to the data transmission module 13; the twenty-first pin of the control chip U1 is connected to the first end of the first resistor R1; the twenty-second pin and twenty-third pin of the control chip U1 are connected to the data transmission module 13; the twenty-fourth pin of the control chip U1 is connected to the first end of the first capacitor C1; the tenth pin of the amplifier chip U2 is connected to the first end of the second capacitor C2; the ninth pin of the amplifier chip U2 is connected to the second end of the second capacitor C2; the fifteenth pin, sixteenth pin, seventeenth pin and eighteenth pin of the amplifier chip U2 are all connected to the analog circuit.
[0035] In this embodiment, as Figures 1 to 2As shown, the model of the control chip U1 can be CAT9555YI-T2; the specification of the first capacitor C1 can be 100 nF; the specification of the first resistor R1 can be 10 K; the specification of the second resistor R2 can be 10 K; the specification of the third resistor R3 can be 10 K; the model of the amplification chip U2 can be ULN2803ADM_TR; the specification of the second capacitor C2 can be 100 nF 50V.
[0036] Among them, the twelfth pin of the control chip U1, the second terminal of the first capacitor C1, the second terminal of the first resistor R1, the second terminal of the second resistor R2, the second terminal of the third resistor R3, the second terminal of the second capacitor C2, and the ninth pin of the amplification chip U2 are all grounded.
[0037] The control chip U1 receives the communication data (instructions) sent by the data transmission module 13 through its twenty-second pin and twenty-third pin, so as to control the high and low levels of the first drive signal sent by the fourth pin, fifth pin, sixth pin and seventh pin of the control chip U1, that is, the data transmission module 13 controls the pulling high or pulling low of the first drive signal in the control chip U1 according to the instructions of the host computer 30. At the same time, the control chip U1 divides the first drive signal into four paths through the fourth pin, fifth pin, sixth pin and seventh pin of the control chip U1, and sends them to the first pin, second pin, third pin and fourth pin of the amplification chip U2 one by one, so as to amplify the first drive signal through the amplification chip U2 to obtain an amplified drive signal; the amplification chip U2 transmits the amplified drive signal to the analog circuit through its eighteenth pin, seventeenth pin, sixteenth pin and fifteenth pin, so as to drive the analog circuit to work according to the drive signal, so as to realize the speaker simulation of the analog sound signal received by the interface module 11 from the motherboard 20 to be tested. Among them, the first drive signal refers to Figure 2 BIT1, BIT2, BIT3, BIT4, etc. in; the amplified drive signal refers to BIT1_CTRL, BIT2_CTRL, BIT3_CTRL, BIT4_CTRL.
[0038] Through the above embodiments, it can be seen that the control chip U1 receives the communication data sent by the data transmission module 13 to control the high and low levels of the first driving signal sent by the control chip U1, that is, the data transmission module 13 controls the pulling up or pulling down of the first driving signal in the control chip U1 according to the instructions of the host computer 30. At the same time, the control chip U1 divides the first driving signal into four paths through the control chip U1 and sends them to the amplifier chip U2 correspondingly, so as to amplify the first driving signal through the amplifier chip U2 to obtain an amplified driving signal; the amplifier chip U2 transmits the amplified driving signal to the analog circuit to drive the analog circuit to work according to the driving signal, thereby realizing the simulation of the analog sound signal through the interface module 11 receiving the analog sound signal sent by the motherboard 20 to be tested, and there is no need for a speaker device for testing. Therefore, the material cost is reduced and the test adaptability is improved.
[0039] In one embodiment, as Figures 1 to 3 shown, the analog circuit includes a first analog circuit and a second analog circuit; both the first analog circuit and the second analog circuit are connected to the control signal circuit and the interface module 11;
[0040] The first analog circuit includes a first inductor L1, a fourth resistor R4, a fifth resistor R5 and a first relay KA1; the first end of the first inductor L1 is connected to the interface module 11 and the data transmission module 13, and the second end of the first inductor L1 is connected to the first end of the fourth resistor R4 and the first end of the fifth resistor R5; the second ends of the fourth resistor R4 and the fifth resistor R5 are both connected to the third pin and the sixth pin of the first relay KA1; the fourth pin and the fifth pin of the first relay KA1 are connected to the interface module 11 and the data transmission module 13; the eighth pin of the first relay KA1 is connected to the eighteenth pin of the amplifier chip U2;
[0041] The second analog circuit includes a second inductor L2, a sixth resistor R6, a seventh resistor R7 and a second relay KA2; the first end of the second inductor L2 is connected to the interface module 11 and the data transmission module 13, and the second end of the second inductor L2 is connected to the first end of the sixth resistor R6 and the first end of the seventh resistor R7; the second ends of the sixth resistor R6 and the seventh resistor R7 are both connected to the third pin and the sixth pin of the second relay KA2; the fourth pin and the fifth pin of the second relay KA2 are connected to the interface module 11 and the data transmission module 13; the eighth pin of the second relay KA2 is connected to the seventeenth pin of the amplifier chip U2.
[0042] In this embodiment, as Figures 1 to 3As shown, the specification of the first inductor L1 can be 33 uH; the specification of the fourth resistor R4 can be 8R; the specification of the fifth resistor R5 can be 8R; the specification of the first relay KA1 can be AGQ200A4H; the specification of the second inductor L2 can be 33 uH; the specification of the sixth resistor R6 can be 8R; the specification of the seventh resistor R7 can be 8R; the specification of the second relay KA2 can be AGQ200A4H.
[0043] The analog circuit is divided into four paths, namely, including the first analog circuit, the second analog circuit, the third analog circuit, and the fourth analog circuit. Specifically, the first path obtains the analog audio signal SPK1_P of the motherboard 20 to be tested through the interface module 11. The analog audio signal SPK1_P is transmitted to the third pin and the sixth pin of the first relay KA1 through the first inductor L1, the fourth resistor R4, and the fifth resistor R5. At this time, if the amplified drive signal received by the first relay KA1 is at a high potential, the third pin of the first relay KA1 is connected to the second pin, and the sixth pin is connected to the seventh pin, and no data loop can be formed; if the amplified drive signal received by the first relay KA1 is at a low potential, the third pin of the first relay KA1 is connected to the fourth pin, and the sixth pin is connected to the fifth pin, and the analog audio signal SPK1_N is output to flow back to the interface module 11 and the power amplifier chip of the motherboard 20 to be tested to form a data loop, so that the data transmission module 13 can obtain test data from the analog audio signal for speaker simulation testing.
[0044] Similarly, the second path obtains the analog audio signal SPK2_P of the motherboard 20 to be tested through the interface module 11. The analog audio signal SPK2_P is transmitted to the third pin and the sixth pin of the second relay KA2 through the second inductor L2, the sixth resistor R6, and the seventh resistor R7. At this time, if the amplified drive signal received by the second relay KA2 is at a high potential, the third pin of the second relay KA2 is connected to the second pin, and the sixth pin is connected to the seventh pin, and no data loop can be formed; if the amplified drive signal received by the second relay KA2 is at a low potential, the third pin of the second relay KA2 is connected to the fourth pin, and the sixth pin is connected to the fifth pin, and the analog audio signal SPK2_N is output to flow back to the interface module 11 and the power amplifier chip of the motherboard 20 to be tested to form a data loop, so that the data transmission module 13 can obtain test data from the analog audio signal for speaker simulation testing.
[0045] From the above embodiments, it can be seen that when the driving signal of the control signal circuit is at a low potential, the first analog circuit and the second analog circuit form a data loop to simulate the actual scenario of testing the speaker device, so as to perform subsequent targeted processing. Therefore, the test applicability is improved, and the test efficiency is further improved.
[0046] In one embodiment, as Figures 1 to 3 shown, the analog circuit further includes a third analog circuit and a fourth analog circuit; both the third analog circuit and the fourth analog circuit are connected to the control signal circuit and the interface module 11;
[0047] The third analog circuit includes a third inductor L3, an eighth resistor R8, a ninth resistor R9, and a third relay KA3; the first end of the third inductor L3 is connected to the interface module 11 and the data transmission module 13, and the second end of the third inductor L3 is connected to the first ends of the eighth resistor R8 and the ninth resistor R9; the second ends of the eighth resistor R8 and the ninth resistor R9 are both connected to the third pin and the sixth pin of the third relay KA3; the fourth pin and the fifth pin of the third relay KA3 are connected to the interface module 11 and the data transmission module 13; the eighth pin of the third relay KA3 is connected to the sixteenth pin of the amplifier chip U2;
[0048] The fourth analog circuit includes a fourth inductor L4, a tenth resistor R10, an eleventh resistor R11, and a fourth relay KA4; the first end of the fourth inductor L4 is connected to the interface module 11 and the data transmission module 13, and the second end of the fourth inductor L4 is connected to the first ends of the tenth resistor R10 and the eleventh resistor R11; the second ends of the tenth resistor R10 and the eleventh resistor R11 are both connected to the third pin and the sixth pin of the fourth relay KA4; the fourth pin and the fifth pin of the fourth relay KA4 are connected to the interface module 11 and the data transmission module 13; the eighth pin of the fourth relay KA4 is connected to the fifteenth pin of the amplifier chip U2.
[0049] In this embodiment, as Figures 1 to 3 shown, the specification of the third inductor L3 can be 33 uH; the specification of the eighth resistor R8 can be 8R; the specification of the ninth resistor R9 can be 8R; the specification of the third relay KA3 can be AGQ200A4H; the specification of the fourth inductor L4 can be 33 uH; the specification of the tenth resistor R10 can be 8R; the specification of the eleventh resistor R11 can be 8R; the specification of the fourth relay KA4 can be AGQ200A4H.
[0050] The analog circuit is divided into four paths, namely, the first analog circuit, the second analog circuit, the third analog circuit, and the fourth analog circuit. Specifically, the third path obtains the analog audio signal SPK3_P of the main board 20 to be tested through the interface module 11. The analog audio signal SPK3_P is transmitted to the third pin and the sixth pin of the third relay KA3 through the third inductor L3, the eighth resistor R8, and the ninth resistor R9. At this time, if the amplified drive signal received by the third relay KA3 is at a high potential, the third pin of the third relay KA3 is connected to the second pin, and the sixth pin is connected to the seventh pin, and a data loop cannot be formed. If the amplified drive signal received by the third relay KA3 is at a low potential, the third pin of the third relay KA3 is connected to the fourth pin, and the sixth pin is connected to the fifth pin, and the analog audio signal SPK3_N is output and flows back to the interface module 11 and the power amplifier chip of the main board 20 to be tested to form a data loop, so that the data transmission module 13 can obtain the test data from the analog audio signal for the speaker simulation test.
[0051] Similarly, the fourth path obtains the analog audio signal SPK4_P of the main board 20 to be tested through the interface module 11. The analog audio signal SPK4_P is transmitted to the third pin and the sixth pin of the fourth relay KA4 through the fourth inductor L4, the tenth resistor R10, and the eleventh resistor R11. At this time, if the amplified drive signal received by the fourth relay KA4 is at a high potential, the third pin of the fourth relay KA4 is connected to the second pin, and the sixth pin is connected to the seventh pin, and a data loop cannot be formed. If the amplified drive signal received by the fourth relay KA4 is at a low potential, the third pin of the fourth relay KA4 is connected to the fourth pin, and the sixth pin is connected to the fifth pin, and the analog audio signal SPK4_N is output and flows back to the interface module 11 and the power amplifier chip of the main board 20 to be tested to form a data loop, so that the data transmission module 13 can obtain the test data from the analog audio signal for the speaker simulation test.
[0052] Through the above embodiments, it can be seen that when the drive signal of the control signal circuit is at a low potential, the actual scenario of forming a data loop through the third analog circuit and the fourth analog circuit for the analog use of the speaker device test is carried out for subsequent targeted processing. Therefore, the test applicability is improved, and the test efficiency is further improved.
[0053] In one embodiment, as Figures 1 to 6As shown, the data transmission module 13 includes a first transmission circuit, a second transmission circuit, and a third transmission circuit; the first transmission circuit is connected to the interface module 11, the control signal circuit, and the second transmission circuit; the second transmission circuit is further connected to the third transmission circuit; the third transmission circuit is further connected to the host computer 30.
[0054] In this embodiment, as Figures 1 to 6 shown, the first transmission circuit is used to receive the driving signal of the control signal circuit (the driving signal refers to Figure 2 BIT5, BIT6, and BIT7 in
[0055] ), and receive the analog sound signal sent by the motherboard 20 to be tested through the interface module 11, and transmit it to the second transmission circuit; the second transmission circuit is used to receive the driving signal sent by the third transmission circuit, receive the analog sound signal sent by the first transmission circuit, measure the analog sound signal to obtain the test data, and receive the instruction sent by the host computer 30 through the third transmission circuit and transmit it to the control signal circuit; the third transmission circuit is used to receive the command of the host computer 30, send a command to the second transmission circuit, and receive the test data transmitted by the second transmission circuit and transmit it to the host computer 30 for the host computer 30 to test whether the test data is qualified.
[0056] In an embodiment, as Figures 1 to 4As shown, the first transmission circuit includes a first transmission chip U3, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a twelfth resistor R12, a thirteenth resistor R13, and an operational amplifier U4; the second pin, third pin, fourth pin, fifth pin, tenth pin, ninth pin, eighth pin, and seventh pin of the first transmission chip U3 are all connected to the interface module 11 and the analog circuit; the sixth pin of the first transmission chip U3 is connected to the third pin of the operational amplifier U4; the first pin and the fourth pin of the operational amplifier U4 are both connected to the first end of the thirteenth resistor R13; the second end of the thirteenth resistor R13 is connected to the second transmission circuit; the fifth pin of the operational amplifier U4 is connected to the first end of the fourth capacitor C4 and the first end of the fifth capacitor C5; the eleventh pin of the first transmission chip U3 is connected to the first end of the third capacitor C3; the thirteenth pin of the first transmission chip U3 is connected to the tenth pin of the control chip U1; the fourteenth pin of the first transmission chip U3 is connected to the ninth pin of the control chip U1; the fifteenth pin of the first transmission chip U3 is connected to the eighth pin of the control chip U1; the sixteenth pin of the first transmission chip U3 is connected to the first end of the twelfth resistor R12.
[0057] In this embodiment, as Figures 1 to 4 shown, the specification of the first transmission chip U3 can be ADG1408YCPZ; the specification of the third capacitor C3 can be 100 nF; the specification of the fourth capacitor C4 can be 10 uF 35V; the specification of the fifth capacitor C5 can be 100 nF 50V; the specification of the twelfth resistor R12 can be 10K; the specification of the thirteenth resistor R13 can be 10R; the specification of the operational amplifier U4 can be LT6274IS5#TRPBF.
[0058] Among them, the first pin, twelfth pin, and P pin of the first transmission chip U3 are grounded; the second ends of the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, and the second pin of the operational amplifier U4 are all grounded.
[0059] The first transmission circuit obtains the analog sound signal of the motherboard 20 to be tested from the interface module 11, and transmits the analog sound signal to the operational amplifier U4 through the second pin, third pin, fourth pin, fifth pin, tenth pin, ninth pin, eighth pin, and seventh pin of the first transmission chip U3 respectively to increase the data transmission capacity; it should be noted that only one path of signal is transmitted by the first transmission circuit each time for the analog sound signal, that is, the analog sound signal needs to be transmitted eight times and is aggregated to the analog sound signal FREQ_INPUT for transmission to the second transmission circuit.
[0060] Through the above embodiments, it can be seen that the first transmission circuit realizes the transmission of the analog sound signal so that the subsequent second transmission circuit can perform targeted processing. Therefore, the automation of the test is realized, the test time is shortened, and the test efficiency is improved.
[0061] In one embodiment, as Figures 1 to 5As shown, the second transmission circuit includes a second transmission chip U5, a crystal oscillator X1, a first interface J2, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a fourteenth resistor R14, a first diode LED1, a tenth capacitor C10, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, an eleventh capacitor C11, a nineteenth resistor R19, a twentieth resistor R20, a twelfth capacitor C12, a thirteenth capacitor C13, a twenty-first resistor R21, a first switch K1, and a second switch K2; the first pin of the second transmission chip U5 is connected to the first end of the tenth capacitor C10; the fifth pin of the second transmission chip U5 is connected to the first pin of the crystal oscillator X1 and the first end of the thirteenth capacitor; the sixth pin of the second transmission chip U5 is connected to the third pin of the crystal oscillator X1 and the first end of the eleventh capacitor C11, and the second end of the eleventh capacitor C11 is connected to the second and fourth pins of the crystal oscillator X1; the seventh pin of the second transmission chip U5 is connected to the first end of the twelfth capacitor C12, the second end of the twentieth resistor R20, and the first end of the second switch K2; the eighth, twenty-third, thirty-fifth, and forty-seventh pins of the second transmission chip U5 are all connected to the second end of the sixth capacitor C6; the ninth pin of the second transmission chip U5 is connected to the first end of the sixth capacitor C6; the twenty-fourth, thirty-sixth, and forty-eighth pins of the second transmission chip U5 are all connected to the first end of the seventh capacitor C7, the first end of the eighth capacitor C8, and the first end of the ninth capacitor C9; the tenth pin of the second transmission chip U5 is connected to the negative electrode of the first diode LED1, and the positive electrode of the first diode LED1 is connected to the second end of the fourteenth resistor R14; the eleventh and twelfth pins of the second transmission chip U5 are connected to the second end of the thirteenth resistor R13; the twentieth pin of the second transmission chip U5 is connected to the first end of the twenty-first resistor R21; the thirty-second and thirty-third pins of the second transmission chip U5 are connected to the third transmission circuit; the thirty-fourth pin of the second transmission chip U5 is connected to the second end of the seventeenth resistor R17, and the first end of the seventeenth resistor R17 is connected to the second pin of the first interface J2; the thirty-seventh pin of the second transmission chip U5 is connected to the second end of the eighteenth resistor R18, and the first end of the eighteenth resistor R18 is connected to the third pin of the first interface J2; the forty-second pin of the second transmission chip U5 is connected to the twenty-second pin of the control chip U1; the forty-third pin of the second transmission chip U5 is connected to the twenty-third pin of the control chip U1; the forty-fourth pin of the second transmission chip U5 is connected to the first end of the sixteenth resistor R16;The second terminal of the sixteenth resistor R16 is connected to the second terminal of the first switch K1 and the first terminal of the nineteenth resistor R19.
[0062] In this embodiment, as Figures 1 to 5 shown, the model of the second transmission chip U5 can be STM32F103C8T6; the specification of the crystal oscillator X1 can be 8 MHz; the specification of the sixth capacitor C6 can be 100 nF 50V; the specification of the seventh capacitor C7 can be 100 nF 50V; the specification of the eighth capacitor C8 can be 100 nF 50V; the specification of the ninth capacitor C9 can be 100 nF 50V; the specification of the fourteenth can be 1K; the type of the first diode LED1 is a light-emitting diode; the specification of the tenth capacitor C10 can be 100 nF 50V; the specification of the fifteenth resistor R15 can be 0R; the specification of the sixteenth resistor R16 can be 1K; the specification of the seventeenth resistor R17 can be 1K; the specification of the eighteenth resistor R18 can be 1K; the specification of the eleventh capacitor C11 can be 18 pF; the specification of the nineteenth resistor R19 can be 10K; the specification of the twentieth resistor R20 can be 10K; the specification of the twelfth capacitor C12 can be 100 nF; the specification of the thirteenth capacitor C13 can be 18 pF; the specification of the twenty-first resistor R21 can be 10K; the model of the first switch K1 can be TSA36331; the model of the second switch K2 can be TSA36331.
[0063] Among them, the second terminals of the sixth capacitor C6, the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9, the tenth capacitor C10, the second terminal of the nineteenth resistor R19, the second terminal of the thirteenth capacitor C13, the second terminal of the twelfth capacitor C12, the second terminal of the second switch K2, the second terminal of the twenty-first resistor R21, the fourth pin of the first interface J2, the second and fourth pins of the crystal oscillator X1 are all grounded. The eleventh and twelfth pins of the second transmission chip U5 are also connected to an ADC (analog-to-digital converter) to convert the received analog sound signal FREQ_INPUT into a digital sound signal FREQ_INPUT for measurement. The first switch and the second switch are used to close when receiving the PP3V3 power supply, and the circuit is turned on.
[0064] The second transmission circuit receives the digital audio signal FREQ_INPUT sent by the second transmission signal through the ADC converter, the eleventh and twelfth pins of the second transmission chip U5, measures audio parameters such as the frequency, peak value, and effective value of the digital audio signal FREQ_INPUT, and records the parameter values corresponding to the audio parameters to form the test data; and sends the test data to the third transmission circuit through USB_P and USB_N.
[0065] Through the above embodiments, it can be seen that the second transmission circuit measures and processes various audio parameters of the analog audio signal to obtain test data, expands the test range, realizes the automation of the test, shortens the test time, and thus improves the test applicability and test efficiency.
[0066] In one embodiment, as Figures 1 to 6 shown, the third transmission circuit includes a second interface CON1, a twenty-second resistor R22, a fourteenth capacitor C14, and a surge protection chip U6; the first pin of the second interface CON1 is connected to the fifth pin of the surge protection chip U6; the second pin of the second interface CON1 is connected to the fourth pin of the surge protection chip U6 and the host computer 30; the third pin of the second interface CON1 is connected to the third pin of the surge protection chip U6 and the host computer 30; the fifth pin of the second interface CON1 is connected to the second end of the fourteenth capacitor C14 and the second end of the twenty-second resistor R22; the sixth and seventh pins of the second interface CON1 are connected to the first end of the fourteenth capacitor C14 and the first end of the twenty-second resistor R22.
[0067] In this embodiment, as Figures 1 to 6 shown, the second interface CON1 is a USB interface; the specification of the twenty-second resistor R22 can be 1M; the specification of the fourteenth capacitor C14 can be 100nF 50V; the model of the surge protection chip U6 can be NUP4202W1T2G.
[0068] Among them, the second end of the twenty-second resistor R22, the second end of the fourteenth capacitor C14, and the second pin of the surge protection chip U6 are all grounded. The surge protection chip U6 is used to protect the circuit from damage when the host computer 30 is inserted into the second interface CON1.
[0069] The host computer 30 sends a signal to the third transmission circuit through the second interface CON1; the third transmission circuit also sends a signal to the second transmission circuit through the second interface CON1. In this way, the second transmission circuit sends a signal to the control circuit to output a drive signal to control whether the analog circuit forms a data loop.
[0070] The third transmission circuit sends the test data to the host computer 30 through USB_P and USB_N; after receiving the test data, the host computer 30 tests whether the test data is qualified; specifically, the test data is displayed on the display of the host computer 30, and the test data is tested for qualification according to the qualification strategy, and the qualification strategy is to limit the parameter range in the test data. If it is within the allowed parameter range, the data is determined to be qualified; if it is not within the allowed parameter range, the data is determined to be unqualified.
[0071] Through the above embodiments, it can be seen that the third transmission circuit sends the test data to the host computer 30 so that the host computer 30 tests whether the test data is qualified, improving the test accuracy.
[0072] In one embodiment, as Figures 1 to 7 shown, the interface module 11 includes a third interface J1, and the third interface J1 is used to establish a data channel connection between the motherboard 20 to be tested and the analog module 12 and the data transmission module 13.
[0073] In this embodiment, as Figures 1 to 7 shown, the interface module 11 includes eight pins, which can be understood as eight data transmission channels for transmitting the analog sound signal of the motherboard 20 to be tested. The third interface J1 is connected to the motherboard 20 to be tested, the analog module 12, and the data transmission module 13.
[0074] When the motherboard 20 to be tested and the data transmission module 13 receive the start test command sent by the host computer 30, the second transmission circuit sends a signal to the control signal circuit to pull down the drive signal. The analog circuit receives the drive signal with a low potential and conducts the circuit; at the same time, the motherboard 20 to be tested sends an analog sound signal to the analog circuit through the third interface J1 to form a data loop, and the first transmission circuit obtains the analog sound signal through the third interface J1 and transmits it to the second transmission circuit; the second transmission circuit measures the sound parameters such as the frequency, peak value, and effective value of the analog sound signal and records the parameter values corresponding to the sound parameters to form the test data, and sends the test data to the third transmission circuit; the third transmission circuit receives the test data and sends the test data to the host computer 30; the host computer 30 tests whether the test data is qualified.
[0075] Through the above embodiments, it can be seen that the interface module 11 realizes the transmission of the analog sound signal, improves the data transmission rate, improves the test flexibility, and thus improves the test efficiency.
[0076] As Figures 1 to 8 shown, the speaker test simulation device 1 further includes a power conversion module, and the power conversion module is connected to the simulation module 12 and the data transmission module 13; the power conversion module is configured to convert the PP5V_USB power input by the third transmission circuit into PP3V3 power for the simulation module 12 and the data transmission module 13 to operate.
[0077] The power conversion module includes a conversion chip U7, a fifteenth capacitor C15, a sixteenth capacitor C16, a seventeenth capacitor C17, an eighteenth capacitor C18, a twenty-third resistor R23, and a second diode LED2; a first pin of the conversion chip U7 is connected to a second end of the fifteenth capacitor C15 and a second end of the sixteenth capacitor C16; a second pin and a fourth pin of the conversion chip U7 are all connected to a first end of the seventeenth capacitor C17, a first end of the eighteenth capacitor C18, and a first end of the twenty-third resistor R23; a second end of the twenty-third resistor R23 is connected to a positive electrode of the second diode LED2; a third pin of the conversion chip U7, a first end of the fifteenth capacitor C15, and a first end of the sixteenth capacitor C16 are all connected to a first pin of the second interface CON1; a second end of the fifteenth capacitor C15, a second end of the sixteenth capacitor C16, a second end of the seventeenth capacitor C17, a second end of the eighteenth capacitor C18, a first pin of the conversion chip U7, and a negative electrode of the second diode LED2 are all grounded.
[0078] The model of the conversion chip U7 may be LM1117IMP-3.3 / NOPB; the specification of the fifteenth capacitor C15 may be 10uF 25V; the specification of the sixteenth capacitor C16 may be 100nF 50V; the specification of the seventeenth capacitor C17 may be 10uF 25V; the specification of the eighteenth capacitor C18 may be 1uF 50V; the specification of the twenty-third resistor R23 may be 1K; the second diode LED2 is a light-emitting diode, and its specification may be LTST-C193KRKT-5A.
[0079] The PP5V_USB power supply input at the first pin of the third interface J1 in the third transmission circuit is input from the first pin and the third pin of the conversion chip U7, and after conversion processing, a PP3V3 power supply is obtained and the PP3V3 power supply is output from the first pin and the third pin of the conversion chip U7; the PP3V3 power supply is used for the twenty-fourth pin of the control chip U1; the PP3V3 power supply is used for the sixteenth pin of the first transmission chip U3; the PP3V3 power supply is used for the first pin, the seventh pin, the eighth pin, the ninth pin, the tenth pin, the twenty-fourth pin, the twenty-third pin, the thirty-fifth pin, the thirty-sixth pin, the forty-fourth pin, the forty-seventh pin and the forty-eighth pin of the second transmission chip U5; the PP3V3 power supply is used for the first pin of the first interface J2. The PP5V_USB power supply is used for the tenth pin of the amplification chip U2; the PP5V_USB power supply is used for the first pin of the first relay KA1, the first pin of the second relay KA2, the first pin of the third relay KA3, the first pin of the fourth relay KA4; the PP5V_USB power supply is used for the eleventh pin of the first transmission chip U3; the PP5V_USB power supply is used for the fifth pin of the crystal oscillator X1.
[0080] The above are only the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims
1. A speaker test simulation device for testing a motherboard to be tested, characterized in that, Including: A test simulation main board, a main board to be tested, and a host computer; the test simulation main board includes an interface module, a simulation module, and a data transmission module; The simulation module and the data transmission module are connected to the main board to be tested through the interface module; the host computer is connected to the main board to be tested and the data transmission module; Wherein, when the simulation module and the data transmission module are connected to the main board to be tested through the interface module, and the main board to be tested and the data transmission module receive a start test instruction sent by the host computer, the simulation module is used to perform speaker simulation on the analog sound signal sent by the main board to be tested; the data transmission module is used to obtain test data from the analog sound signal and transmit it to the host computer; the host computer is used to test whether the test data is qualified.
2. The device according to claim 1, characterized in that The simulation module includes a control signal circuit and an analog circuit; the control signal circuit is connected to the analog circuit; the control signal circuit is also connected to the data transmission module; the analog circuit is also connected to the main board to be tested through the interface module; when the host computer sends an instruction to the control signal circuit through the interface module and the data transmission module, the control signal circuit outputs a drive signal to the analog circuit to perform speaker simulation on the main board to be tested.
3. The device according to claim 2, characterized in that, The control signal circuit includes a control chip, a first capacitor, a first resistor, a second resistor, a third resistor, an amplifier chip, and a second capacitor connected; the second pin of the control chip is connected to the first end of the second resistor; the third pin of the control chip is connected to the first end of the third resistor; the fourth pin, fifth pin, sixth pin, and seventh pin of the control chip are respectively connected to the first pin, second pin, third pin, and fourth pin of the amplifier chip; the eighth pin, ninth pin, and tenth pin of the control chip are connected to the data transmission module; the twenty-first pin of the control chip is connected to the first end of the first resistor; the twenty-second pin and twenty-third pin of the control chip are connected to the data transmission module; the twenty-fourth pin of the control chip is connected to the first end of the first capacitor; the tenth pin of the amplifier chip is connected to the first end of the second capacitor; the ninth pin of the amplifier chip is connected to the second end of the second capacitor; the fifteenth pin, sixteenth pin, seventeenth pin, and eighteenth pin of the amplifier chip are all connected to the analog circuit.
4. The device according to claim 3, characterized in that, The analog circuit includes a first analog circuit and a second analog circuit; the first analog circuit and the second analog circuit are both connected to the control signal circuit and the interface module; The first analog circuit includes a first inductor, a fourth resistor, a fifth resistor, and a first relay; a first end of the first inductor is connected to the interface module and the data transmission module, and a second end of the first inductor is connected to a first end of the fourth resistor and a first end of the fifth resistor; a second end of the fourth resistor and a second end of the fifth resistor are both connected to a third pin and a sixth pin of the first relay; a fourth pin and a fifth pin of the first relay are connected to the interface module and the data transmission module; an eighth pin of the first relay is connected to an eighteenth pin of the amplifier chip; The second analog circuit includes a second inductor, a sixth resistor, a seventh resistor, and a second relay; a first end of the second inductor is connected to the interface module and the data transmission module, and a second end of the second inductor is connected to a first end of the sixth resistor and a first end of the seventh resistor; a second end of the sixth resistor and a second end of the seventh resistor are both connected to a third pin and a sixth pin of the second relay; a fourth pin and a fifth pin of the second relay are connected to the interface module and the data transmission module; an eighth pin of the second relay is connected to a seventeenth pin of the amplifier chip.
5. The device according to claim 4, characterized in that, The analog circuit further includes a third analog circuit and a fourth analog circuit; both the third analog circuit and the fourth analog circuit are connected to the control signal circuit and the interface module; The third analog circuit includes a third inductor, an eighth resistor, a ninth resistor, and a third relay; a first end of the third inductor is connected to the interface module and the data transmission module, and a second end of the third inductor is connected to a first end of the eighth resistor and a first end of the ninth resistor; a second end of the eighth resistor and a second end of the ninth resistor are both connected to a third pin and a sixth pin of the third relay; a fourth pin and a fifth pin of the third relay are connected to the interface module and the data transmission module; an eighth pin of the third relay is connected to a sixteenth pin of the amplifier chip; The fourth analog circuit includes a fourth inductor, a tenth resistor, an eleventh resistor, and a fourth relay; a first end of the fourth inductor is connected to the interface module and the data transmission module, and a second end of the fourth inductor is connected to a first end of the tenth resistor and a first end of the eleventh resistor; a second end of the tenth resistor and a second end of the eleventh resistor are both connected to a third pin and a sixth pin of the fourth relay; a fourth pin and a fifth pin of the fourth relay are connected to the interface module and the data transmission module; an eighth pin of the fourth relay is connected to a fifteenth pin of the amplifier chip.
6. The device according to claim 4, characterized in that, The data transmission module includes a first transmission circuit, a second transmission circuit, and a third transmission circuit; the first transmission circuit is connected to the interface module, the control signal circuit, and the second transmission circuit; the second transmission circuit is further connected to the third transmission circuit; the third transmission circuit is further connected to the host computer.
7. The device according to claim 6, wherein, The first transmission circuit includes a first transmission chip, a third capacitor, a fourth capacitor, a fifth capacitor, a twelfth resistor, a thirteenth resistor, and an operational amplifier; the second pin, third pin, fourth pin, fifth pin, tenth pin, ninth pin, eighth pin, and seventh pin of the first transmission chip are all connected to the interface module and the analog circuit; the sixth pin of the first transmission chip is connected to the third pin of the operational amplifier; the first pin and the fourth pin of the operational amplifier are both connected to the first end of the thirteenth resistor; the second end of the thirteenth resistor is connected to the second transmission circuit; the fifth pin of the operational amplifier is connected to the first end of the fourth capacitor and the first end of the fifth capacitor; the eleventh pin of the first transmission chip is connected to the first end of the third capacitor; the thirteenth pin of the first transmission chip is connected to the tenth pin of the control chip; the fourteenth pin of the first transmission chip is connected to the ninth pin of the control chip; the fifteenth pin of the first transmission chip is connected to the eighth pin of the control chip; the sixteenth pin of the first transmission chip is connected to the first end of the twelfth resistor.
8. The device according to claim 7, characterized in that The second transmission circuit includes a second transmission chip, a crystal oscillator, a first interface, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a fourteenth resistor, a first diode, a tenth capacitor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, an eleventh capacitor, a nineteenth resistor, a twentieth resistor, a twelfth capacitor, a thirteenth capacitor, a twenty-first resistor, a first switch, and a second switch; a first pin of the second transmission chip is connected to a first end of the tenth capacitor; a fifth pin of the second transmission chip is connected to a first pin of the crystal oscillator and a first end of the thirteenth capacitor; a sixth pin of the second transmission chip is connected to a third pin of the crystal oscillator and a first end of the eleventh capacitor, and a second end of the eleventh capacitor is connected to a second pin and a fourth pin of the crystal oscillator; a seventh pin of the second transmission chip is connected to a first end of the twelfth capacitor, a second end of the twentieth resistor, and a first end of the second switch; an eighth pin, a twenty-third pin, a thirty-fifth pin, and a forty-seventh pin of the second transmission chip are all connected to a second end of the sixth capacitor; a ninth pin of the second transmission chip is connected to a first end of the sixth capacitor; a twenty-fourth pin, a thirty-sixth pin, and a forty-eighth pin of the second transmission chip are all connected to a first end of the seventh capacitor, a first end of the eighth capacitor, and a first end of the ninth capacitor; a tenth pin of the second transmission chip is connected to a negative electrode of the first diode, and a positive electrode of the first diode is connected to a second end of the fourteenth resistor; an eleventh pin and a twelfth pin of the second transmission chip are connected to a second end of the thirteenth resistor; a twentieth pin of the second transmission chip is connected to a first end of the twenty-first resistor; a thirty-second pin and a thirty-third pin of the second transmission chip are connected to the third transmission circuit; a thirty-fourth pin of the second transmission chip is connected to a second end of the seventeenth resistor, and a first end of the seventeenth resistor is connected to a second pin of the first interface; a thirty-seventh pin of the second transmission chip is connected to a second end of the eighteenth resistor, and a first end of the eighteenth resistor is connected to a third pin of the first interface; a forty-second pin of the second transmission chip is connected to a twenty-second pin of the control chip; a forty-third pin of the second transmission chip is connected to a twenty-third pin of the control chip; a forty-fourth pin of the second transmission chip is connected to a first end of the sixteenth resistor; a second end of the sixteenth resistor is connected to a second end of the first switch and a first end of the nineteenth resistor.
9. The device according to claim 6, characterized in that, The third transmission circuit includes a second interface, a twenty-second resistor, a fourteenth capacitor, and a surge protection chip; a first pin of the second interface is connected to a fifth pin of the surge protection chip; a second pin of the second interface is connected to a fourth pin of the surge protection chip and the host computer; a third pin of the second interface is connected to a third pin of the surge protection chip and the host computer; a fifth pin of the second interface is connected to a second end of the fourteenth capacitor and a second end of the twenty-second resistor; a sixth pin and a seventh pin of the second interface are connected to a first end of the fourteenth capacitor and a first end of the twenty-second resistor.
10. The device according to claim 1, characterized in that, The interface module includes a third interface, and the third interface is used to establish a data channel connection between the motherboard to be tested, the analog module, and the data transmission module.