Low dropout regulator based on step-down transient protection

Abstract

The utility model discloses a low dropout regulator based on step-down transient protection, which comprises an LDO unit, the LDO unit comprises an amplifier, a first power tube and a voltage dividing unit, the first end of the first power tube is connected with power supply voltage, the second end of the first power tube is connected with an output node, the voltage dividing unit comprises a voltage dividing node, and the voltage dividing node is connected with the first input end of the amplifier; the voltage clamping unit is used for generating a clamping voltage at a clamping node; the buffer unit is connected between the power supply voltage and the reference potential, and is connected with the control end of the first power tube, the output end of the amplifier and the power supply port; and the transient protection unit is connected between the clamping node and the output node and is used for clamping the clamping voltage based on the output voltage. According to the low dropout linear regulator, the clamping voltage is clamped through the diode, when the power supply voltage is rapidly and greatly reduced, the LDO unit is prevented from collapsing, the transient response performance of the low dropout linear regulator is remarkably improved, and the reliability of the low dropout linear regulator is improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of integrated circuits, and particularly relates to a low dropout linear regulator based on buck transient protection. Background Art

[0002] Low Dropout regulators (LDOs) have the advantages of low output noise, simple circuit structure, small chip area occupation, and small voltage ripple, and have become an important type of circuit in power management chips. The low dropout linear regulator can provide a power supply with low output ripple for noise-sensitive circuits such as analog circuits and radio frequency circuits. Moreover, due to the relatively simple structure and few peripheral components, it is widely used in system-on-chip (SoC) chips.

[0003] For a low dropout linear regulator operating at a high input voltage V IN , usually many high-voltage MOS transistors are required, which will reduce the transient response speed of the low dropout linear regulator and increase power consumption. In the field of MOS transistor design and production applications, high-voltage MOS transistors refer to MOS transistor devices with V GS <5V, but V DS greater than 5V.

[0004] The prior art usually uses high-resistance resistor devices to generate a low-voltage clamped voltage rail, and connects the gate of the high-voltage NMOS in the low dropout linear regulator to this clamped voltage rail to provide a lower operating voltage for the low-voltage devices in the low dropout linear regulator, thereby improving the transient response of the low dropout linear regulator and reducing the current power consumption of the regulator.

[0005] However, the disadvantages of the prior art are that when the input voltage VIN changes rapidly from high voltage to low voltage, due to the coupling effect of the parasitic capacitance of the resistor device, the clamped voltage rail may collapse, resulting in the inability of the low-voltage devices in the low dropout linear regulator to operate stably.

[0006] Therefore, in view of the above technical problems, it is necessary to provide a low dropout linear regulator based on buck transient protection. Summary of the Utility Model

[0007] The purpose of the utility model is to provide a low dropout linear regulator based on buck transient protection to solve the problem of transient reduction of the output voltage when the power supply voltage drops rapidly.

[0008] To achieve the above purpose, the technical solution provided by a specific embodiment of the utility model is as follows:

[0009] A low dropout linear regulator based on buck transient protection, the low dropout linear regulator comprising:

[0010] The LDO unit includes an amplifier, a first power transistor, and a voltage dividing unit. The first end of the first power transistor is connected to the power supply voltage, the second end is connected to the output node, the voltage dividing unit is connected between the output node and the reference potential, the voltage dividing unit includes a voltage dividing node, and the voltage dividing node is connected to the first input end of the amplifier;

[0011] The voltage clamping unit is connected between the power supply voltage and the reference potential and is used to generate a clamping voltage at the clamping node;

[0012] The buffer unit is connected between the power supply voltage and the reference potential and is connected to the control end of the first power transistor, the output end, and the power supply port of the amplifier;

[0013] The transient protection unit is connected between the clamping node and the output node and is used to clamp the clamping voltage based on the output voltage on the output node when the power supply voltage decreases.

[0014] In one or more embodiments of the present invention, the transient protection unit includes a first diode. The anode of the first diode is directly or indirectly connected to the output node, and the cathode of the first diode is directly or indirectly connected to the clamping node.

[0015] In one or more embodiments of the present invention, the transient protection unit further includes a filter capacitor and a filter resistor. The first end of the filter capacitor is connected to the reference potential, the second end of the filter capacitor is connected to the first end of the filter resistor and the clamping node, and the second end of the filter resistor is connected to the cathode of the first diode.

[0016] In one or more embodiments of the present invention, the voltage clamping unit includes a first resistor and a second diode; wherein,

[0017] The first end of the first resistor is connected to the power supply voltage, the second end is connected to the clamping node and generates a clamping voltage;

[0018] The first end of the second diode is connected to the reference potential, the second end is connected to the clamping node, and the clamping voltage is less than the power supply voltage.

[0019] In one or more embodiments of the present invention, the buffer unit includes a first MOS transistor, a second MOS transistor, and a second power transistor; wherein,

[0020] The first end of the first MOS transistor is connected to the power supply port of the amplifier, the second end is indirectly connected to the power supply voltage, and the control end is connected to the clamping node;

[0021] The first end of the second MOS transistor is connected to the second end of the second power transistor, the second end is indirectly connected to the power supply voltage, and the control end is connected to the clamping node;

[0022] The control terminal of the second power transistor is connected to the output terminal of the amplifier, and the first terminal is connected to the reference potential;

[0023] The voltage at the output terminal of the amplifier is less than the voltage at the control terminal of the first power transistor, and the voltage at the power supply port is less than the clamping voltage.

[0024] In one or more embodiments of the present invention, the first MOS transistor and the second MOS transistor are NMOS transistors; and / or,

[0025] The second power transistor is an NMOS transistor.

[0026] In one or more embodiments of the present invention, the buffer unit further includes a second resistor and a third resistor;

[0027] The first terminal of the second resistor is connected to the power supply voltage, and the second terminal is connected to the second terminal of the first MOS transistor;

[0028] The first terminal of the third resistor is connected to the power supply voltage, and the second terminal is connected to the second terminal of the second MOS transistor.

[0029] In one or more embodiments of the present invention, the voltage dividing unit includes a fourth resistor and a fifth resistor; wherein,

[0030] The first terminal of the fourth resistor is connected to the output node, and the second terminal is connected to the voltage dividing node;

[0031] The first terminal of the fifth resistor is connected to the voltage dividing node, and the second terminal is connected to the reference potential.

[0032] In one or more embodiments of the present invention, the first power transistor is a PMOS transistor.

[0033] In one or more embodiments of the present invention, the LDO unit further includes a load capacitor, the first terminal of the load capacitor is connected to the output node, and the second terminal of the load capacitor is connected to the reference potential.

[0034] Compared with the prior art, for the low dropout linear regulator based on buck transient protection of the present invention, when the power supply voltage V IN rapidly and significantly drops, the clamping voltage is clamped based on the transient protection unit to prevent the LDO unit from collapsing, significantly improving the transient response of the low dropout linear regulator and enhancing the reliability of the low dropout linear regulator;

[0035] The utility model utilizes a resistance device and a diode to generate a clamping voltage, reduces the power consumption of a low dropout linear regulator, and some devices in the LDO unit can adopt low-voltage devices, improving the working efficiency of the low dropout linear regulator, and accelerating the transient response of the regulator without increasing current consumption. Description of the Drawings

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings described below are only some embodiments recorded in the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0037] Figure 1 It is a circuit diagram of a low dropout linear regulator based on buck transient protection in a specific embodiment of the present utility model. Detailed Embodiments

[0038] In order to enable those skilled in the art to better understand the technical solutions in the present utility model, the following will clearly and completely describe the technical solutions in the embodiments of the present utility model with reference to the drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0039] "Coupled" or "connected" or "linked" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conduction medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include a connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as a connection through a circuit or component such as a switch or a follower circuit. In addition, in the present utility model, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0040] As Figure 1 shown, a low dropout linear regulator based on buck transient protection in a specific embodiment of the present utility model includes an LDO unit 10, a buffer unit 20, a voltage clamping unit 30, and a transient protection unit 40.

[0041] The LDO unit 10 includes an amplifier U1, a first power transistor M3, and a voltage dividing unit 11. The control terminal of the first power transistor M3 is indirectly connected to the output terminal of the amplifier U1. The first terminal of the first power transistor M3 is connected to the power supply voltage V IN and the second terminal of the first power transistor M3 is connected to the output node, and an output voltage V OUT is generated through the output node.

[0042] The voltage dividing unit 11 includes a voltage dividing node. The voltage dividing unit 11 is connected to the output node and is configured to divide the output voltage V OUT and generate a feedback voltage V FB at the voltage dividing node. The first input terminal of the amplifier U1 is connected to the voltage dividing node to receive the feedback voltage V FB , and the second input terminal of the amplifier U1 is configured to receive a reference voltage V REF . It can be understood that in this embodiment, the reference voltage V REF is generated by a voltage source V1, and the voltage source V1 can be a low-voltage device.

[0043] As Figure 1 shown, the voltage dividing unit 11 in this embodiment includes a fourth resistor R4 and a fifth resistor R5.

[0044] The first terminal of the fourth resistor R4 is connected to the output node (i.e., the second terminal of the first power transistor M3), and the second terminal of the fourth resistor R4 is connected to the voltage dividing node and generates a feedback voltage V FB . The first terminal of the fifth resistor R5 is connected to the voltage dividing node, and the second terminal of the fifth resistor R5 is connected to the reference potential GND. The first terminal of the first power transistor M3 is the source, the second terminal is the drain, and the control terminal is the gate.

[0045] In the LDO unit 10 of this embodiment, the amplifier U1, the first power transistor M3, the fourth resistor R4, and the fifth resistor R5 form a basic LDO circuit. The control terminal of the first power transistor M3 is connected to the buffer unit 20, and the output terminal of the amplifier U1 is connected to the buffer unit 20. The working principle of the LDO will not be elaborated here.

[0046] In this embodiment, the first power transistor M3 is a PMOS transistor. Further, the LDO unit 10 in this embodiment is applicable to a high-voltage circuit, that is, the LDO unit 10 is a high-voltage LDO, and the first MOS transistor M3 is a high-voltage PMOS. It can be understood that in the field of MOS transistor design and production applications, a high-voltage PMOS transistor refers to a device with V GS <5V, but V DS is greater than 5V. This embodiment provides a buffer unit 20, which enables low-voltage devices such as the amplifier U1 in the LDO unit 10 to work when the power supply voltage V IN is high voltage (for example, greater than 5V).

[0047] As shown Figure 1 in the figure, the voltage clamping unit 30 in this embodiment is connected between the power supply voltage V IN and the reference potential GND, and is connected to the buffer unit 20. The voltage clamping unit 30 includes a clamping node for generating a clamping voltage V CLAMP , and the clamping voltage V CLAMP is less than the power supply voltage VIN.

[0048] The voltage clamping unit 30 includes a first resistor R1 and a second diode Z1.

[0049] The first end of the first resistor R1 is connected to the power supply voltage VIN, the second end of the first resistor R1 is connected to the clamping node, and the second end of the second diode Z1 is connected to the clamping node and generates the clamping voltage V CLAMP , and the first end of the second diode Z1 is connected to the reference potential GND.

[0050] The second diode Z1 in this embodiment can be a zener diode. Since the reverse breakdown voltage of the zener diode is about 6V, the clamping voltage V CLAMP is about 6V under normal working conditions.

[0051] As shown Figure 1 in the figure, the buffer unit 20 is connected between the power supply voltage VIN and the reference potential GND, and is connected to the control end of the first power transistor M3 and the output end of the amplifier U1.

[0052] Specifically, the buffer unit 20 includes a first MOS transistor M1, a second MOS transistor M2, and a second power transistor M4.

[0053] The first end of the first MOS transistor M1 is connected to the power supply port of the amplifier U1, the second end of the first MOS transistor M1 is indirectly connected to the power supply voltage V IN , the control end of the first MOS transistor M1 is connected to the clamping node and receives the clamping voltage V CLAMP . It can be understood that the amplifier U1 in this embodiment can be powered by a single power supply or a dual power supply.

[0054] The first end of the second MOS transistor M2 is connected to the second end of the second power transistor M4, the second end of the second MOS transistor M2 is indirectly connected to the power supply voltage V IN , the control end of the second MOS transistor M2 is connected to the clamping node and receives the clamping voltage V CLAMP . The first ends of the first MOS transistor M1 and the second MOS transistor M2 are source electrodes, the second ends are drain electrodes, and the control ends are gate electrodes.

[0055] The control end of the second power transistor M4 is connected to the output end of the amplifier U1, and the first end of the second power transistor M4 is connected to the reference potential GND.

[0056] It is understandable that in this embodiment, the voltage at the output terminal of the amplifier U1 is less than the voltage at the control terminal of the first power transistor M3, and the voltage at the power supply terminal of the amplifier U1 is less than the clamping voltage V CLAMP .

[0057] In this embodiment, the first MOS transistor M1 and the second MOS transistor M2 are NMOS transistors, and the second power transistor M4 is an NMOS transistor.

[0058] Furthermore, the first MOS transistor M1 and the second MOS transistor M2 are high-voltage NMOS transistors, and the second power transistor M4 is a low-voltage NMOS transistor. It is understandable that in the field of MOS transistor design and production applications, a low-voltage MOS transistor refers to a device in which V GS and V DS need to be less than 5V; while a high-voltage MOS transistor refers to a device in which V GS < 5V, but V DS is greater than 5V.

[0059] Furthermore, the buffer unit 20 further includes a second resistor R2 and a third resistor R3.

[0060] The first end of the second resistor R2 is connected to the power supply voltage V IN , and the second end of the second resistor R2 is connected to the second end of the first MOS transistor M1. The first end of the third resistor R3 is connected to the power supply voltage V IN , and the second end of the third resistor R3 is connected to the second end of the second MOS transistor M2.

[0061] The low-dropout linear regulator in this embodiment is suitable for low-power circuits. Therefore, the first resistor R1 can adopt a resistor device with a high resistance value. In this embodiment, the first MOS transistor M1 and the second MOS transistor M2 of the buffer unit 20 are high-voltage NMOS transistors (for example, the gate-source threshold voltage V TH of the first MOS transistor M1 and the second MOS transistor M2 is 2V). When the clamping voltage V CLAMP is about 6V, the first MOS transistor M1 and the second MOS transistor M2 can be regarded as being in the conducting state. Then, the voltage at the first end (source voltage) of the first MOS transistor M1 and the second MOS transistor M2 is V CLAMP -V TH (for example, about 5V). Therefore, the amplifier U1 and the second power transistor M4 can adopt low-voltage devices, thereby improving the working efficiency of the low-dropout linear regulator.

[0062] As Figure 1 shown, in this embodiment, the transient protection unit 40 is connected between the clamping voltage V CLAMP and the output voltage V OUT , and is used for the power supply voltage V INWhen it drops rapidly by a large margin, based on the output voltage V OUT clamps the clamping voltage V CLAMP for clamping.

[0063] The transient protection unit 40 includes a first diode D1. The anode of the first diode D1 is directly or indirectly connected to the output node, and the cathode of the first diode D1 is directly or indirectly connected to the clamping node.

[0064] The transient protection unit 40 further includes a filter capacitor C1 and a filter resistor R6. The first end of the filter capacitor C1 is connected to the reference potential GND, the second end of the filter capacitor C1 is connected to the first end of the filter resistor R6 and the clamping node, and the second end of the filter resistor R6 is connected to the cathode of the first diode D1.

[0065] The low dropout linear regulator in this embodiment includes two states:

[0066] The first state (the power supply voltage V IN normal operating state), the voltage clamping unit 30 uses the reverse breakdown characteristic of the second diode Z1 to generate a clamping voltage V of about 6V CLAMP . At the same time, due to the large resistance value of the first resistor R1, the power consumption current of the low dropout linear regulator is relatively low. The buffer unit 20 provides the operating voltage for the amplifier U1 and the second power transistor M4 in the LDO unit 10 based on the clamping voltage V CLAMP . The amplifier U1 is used to amplify the difference between the feedback voltage V FB and the reference voltage V REF . The gate-source voltage V GS of the second power transistor M4 increases or decreases the current to control the gate-source voltage V GS of the first power transistor M3. The gate-source voltage V GS of the first power transistor M3 increases or decreases the current to control the output voltage V OUT . Finally, the feedback voltage V FB and the reference voltage V REF form a negative feedback through the amplifier U1 to achieve the stability of the output voltage V OUT . In the first state, the anode voltage (output voltage V OUT ) of the first diode D1 is less than the cathode voltage (clamping voltage V CLAMP ), and the first diode D1 is in the reverse bias state, and the transient protection unit 40 does not work.

[0067] The second state (the power supply voltage V IN rapidly drops from a high voltage to a low voltage). If there is no transient protection unit 40 proposed in this embodiment: If the resistance value of the first resistor R1 is large, the parasitic capacitance at both ends of the first resistor R1 will also be large. Therefore, when the power supply voltage V INWhen the voltage drops rapidly and significantly (for example, when the voltage drops from 48V to 5.5V with a slew rate of 10V / μs), due to the capacitive coupling effect of parasitic capacitance, the clamping voltage V CLAMP may drop significantly (for example, drop below 1V), which may cause the LDO unit 10 to collapse, and the output voltage V OUT drops below 1V. Based on the transient protection unit 40 proposed in this embodiment, when the power supply voltage V IN drops rapidly and significantly (for example, when the voltage drops from 48V to 5.5V with a slew rate greater than or equal to 10V / μs), the anode voltage of the first diode D1 (i.e., the output voltage V OUT ) is greater than the cathode voltage (i.e., the clamping voltage V CLAMP ), and the first diode D1 is in the forward conduction state. Based on the conduction voltage drop of the first diode D1 (for example, 0.7V), the clamping voltage V CLAMP is clamped to V OUT -0.7V, significantly improving the transient response when the regulator has a wide power supply voltage V IN range.

[0068] Simulation shows that under the same power supply voltage V IN linear buck transient, the output of the "typical 5V-LDO" remains at the minimum value, for example, 4.4V, while the clamping voltage V CLAMP can be maintained above 3V to keep the buffer unit 20 working. Therefore, this embodiment can significantly improve the output performance of the LDO.

[0069] The low-dropout linear regulator based on buck transient protection in this embodiment is also applicable to providing a stable output voltage for a larger system (such as a DC-DC or SOC).

[0070] From the above technical solutions, it can be seen that the present utility model has the following beneficial effects:

[0071] When the power supply voltage V IN drops rapidly and significantly, the present utility model clamps the clamping voltage V CLAMP through a diode to prevent the clamping voltage V CLAMP from dropping instantaneously following the power supply voltage V IN , avoiding the collapse of the LDO unit, and significantly improving the transient response performance of the low-dropout linear regulator;

[0072] The present utility model uses a resistor device and a diode to generate the clamping voltage V CLAMP , reducing the current power consumption of the low-dropout linear regulator, and some devices in the LDO unit can use low-voltage devices, improving the working efficiency of the low-dropout linear regulator, and accelerating the transient response of the regulator without increasing current consumption.

[0073] For those skilled in the art, it is obvious that the present utility model is not limited to the details of the above-described exemplary embodiments, and the present utility model can be implemented in other specific forms without departing from the spirit or basic characteristics of the present utility model. Therefore, in any regard, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present utility model is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present utility model. Any reference signs in the claims should not be construed as limiting the claims involved.

[0074] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A low dropout linear regulator based on step-down transient protection, characterized in that, The low dropout linear regulator includes: An LDO unit, including an amplifier, a first power transistor, and a voltage dividing unit. The first end of the first power transistor is connected to the power supply voltage, the second end is connected to the output node, the voltage dividing unit is connected between the output node and the reference potential, the voltage dividing unit includes a voltage dividing node, and the voltage dividing node is connected to the first input terminal of the amplifier; A voltage clamping unit, connected between the power supply voltage and the reference potential, for generating a clamping voltage at the clamping node; A buffer unit, connected between the power supply voltage and the reference potential, and connected to the control terminal of the first power transistor, the output terminal and the power supply port of the amplifier; A transient protection unit, connected between the clamping node and the output node, for clamping the clamping voltage based on the output voltage on the output node when the power supply voltage decreases.

2. The low dropout linear regulator based on step-down transient protection according to claim 1, wherein The transient protection unit includes a first diode, the anode of the first diode is directly or indirectly connected to the output node, and the cathode of the first diode is directly or indirectly connected to the clamping node.

3. The low dropout linear regulator based on step-down transient protection according to claim 2, characterized in that, The transient protection unit further includes a filter capacitor and a filter resistor. The first end of the filter capacitor is connected to the reference potential, the second end of the filter capacitor is connected to the first end of the filter resistor and the clamping node, and the second end of the filter resistor is connected to the cathode of the first diode.

4. The low dropout linear regulator based on buck transient protection according to claim 1, wherein The voltage clamping unit includes a first resistor and a second diode; wherein, The first end of the first resistor is connected to the power supply voltage, the second end is connected to the clamping node and generates a clamping voltage; The first end of the second diode is connected to the reference potential, the second end is connected to the clamping node, and the clamping voltage is less than the power supply voltage.

5. The low dropout linear regulator based on buck transient protection according to claim 1, characterized in that The buffer unit includes a first MOS transistor, a second MOS transistor, and a second power transistor; wherein, The first end of the first MOS transistor is connected to the power supply port of the amplifier, the second end is indirectly connected to the power supply voltage, and the control terminal is connected to the clamping node; The first end of the second MOS transistor is connected to the second end of the second power transistor, the second end is indirectly connected to the power supply voltage, and the control terminal is connected to the clamping node; The control terminal of the second power transistor is connected to the output terminal of the amplifier, and the first end is connected to the reference potential; The voltage at the output terminal of the amplifier is less than the voltage at the control terminal of the first power transistor, and the voltage at the power supply port is less than the clamping voltage.

6. The low dropout linear regulator based on step-down transient protection according to claim 5, characterized in that, The first MOS transistor and the second MOS transistor are NMOS transistors; and / or, The second power transistor is an NMOS transistor.

7. The low dropout linear regulator based on step-down transient protection according to claim 5, characterized in that, The buffer unit further includes a second resistor and a third resistor; The first end of the second resistor is connected to the power supply voltage, and the second end is connected to the second end of the first MOS transistor; The first end of the third resistor is connected to the power supply voltage, and the second end is connected to the second end of the second MOS transistor.

8. The low dropout linear regulator based on buck transient protection according to claim 1, wherein The voltage dividing unit includes a fourth resistor and a fifth resistor; wherein, The first end of the fourth resistor is connected to the output node, and the second end is connected to the voltage dividing node; The first end of the fifth resistor is connected to the voltage dividing node, and the second end is connected to the reference potential.

9. The low dropout linear regulator based on buck transient protection according to claim 1, wherein The first power transistor is a PMOS transistor.

10. The low dropout linear regulator based on step-down transient protection according to claim 1, wherein The LDO unit further includes a load capacitor. The first end of the load capacitor is connected to the output node, and the second end of the load capacitor is connected to the reference potential.

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