Power supply device and test machine

Abstract

The utility model relates to a power supply device and a testing machine, the power supply device comprises a main loop, a voltage loop, a current loop and a clamping circuit, in a pressurization mode, when a detection current output by the clamping circuit at the current loop is in a set current clamping range, the output impedance is high resistance; and when the detection current output by the current loop is not in a set current clamping range, the clamping circuit triggers the clamping current to carry out analog output, and the output impedance is switched to low resistance, so that the output of the main loop is equivalent to a constant current source. In the current adding mode, when the detection voltage output by the clamping circuit at the voltage loop is within a set voltage clamping range, the output impedance is high resistance; and when the detection voltage output by the voltage loop is not in a set voltage clamping range, the clamping circuit triggers the clamping voltage to perform analog output, and the output impedance is switched to low resistance, so that the output of the main loop is equivalent to a constant voltage source. The simulation regulation function is achieved, and the response speed is high.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor testing, and particularly to a power supply device and a tester. Background Art

[0002] Semiconductor automatic testing refers to using Automatic Test Equipment (ATE) to detect various parameter indicators of a Device Under Test (DUT), and eliminating defective products to control the ex-factory quality of the test device. The power supply board in semiconductor testing equipment is used to provide voltage or current excitation to the device under test, and usually has functions such as Forward Voltage (FV), Measure Voltage (MV), Forward Current (FI), and Measure Current (MI) and their combinations.

[0003] When there are defective products in the device under test, it will cause overvoltage or overcurrent in the output signal of the semiconductor testing equipment. Therefore, it is necessary to add a clamping protection mechanism to the output signal to protect the device under test from secondary damage. In traditional power supply boards, a fixed voltage clamping circuit is usually adopted, using a zener diode operating in the reverse breakdown state, or a fixed current clamping circuit is adopted, where the current passes through a resistor to generate a voltage drop, and the voltage drop is used to form a feedback to the circuit to achieve the purpose of current clamping. The traditional power supply board uses a fixed clamping circuit, and the clamping value is fixed, making it difficult to achieve the function of analog adjustment. Summary of the Utility Model

[0004] Based on this, in view of the above problems, it is necessary to provide a power supply device and a tester that can achieve the function of analog adjustment.

[0005] In the first aspect of this application, a power supply device is provided, including a main loop, a voltage loop, a current loop, and a clamping circuit. The main loop is connected to the current loop, the current loop is connected to a load, the voltage loop is connected to the load, and the clamping circuit is connected to the voltage loop, the current loop, and the main loop. The current loop is used to detect the current of the load and output the detected current to the clamping circuit. The voltage loop is used to detect the voltage of the load and output the detected voltage to the clamping circuit. The main loop selects to access the detected voltage output by the voltage loop or the detected current output by the current loop.

[0006] In the pressurization mode, when the detected current output by the current loop is within the set current clamping range, the output impedance of the clamping circuit is high impedance. When the detected current output by the current loop is not within the set current clamping range, the clamping current is triggered for analog output, and the output impedance is switched to low impedance, so that the output of the main loop is equivalent to a constant current source.

[0007] In the current-adding mode, when the detected voltage output by the voltage loop is within the set voltage clamping range, the clamping circuit has a high impedance output; when the detected voltage output by the voltage loop is not within the set voltage clamping range, the clamping voltage is triggered for analog output, and the output impedance is switched to a low impedance, so that the output of the main loop is equivalent to a constant voltage source.

[0008] In one embodiment, the main loop includes an error comparison circuit, an integration circuit, and a power amplifier. The error comparison circuit is connected to the integration circuit, the clamping circuit, the current loop, and the voltage loop. The power amplifier is connected to the integration circuit and the current loop.

[0009] In one embodiment, the error comparison circuit includes an error comparator, a switching switch SW2, a resistor R11, a resistor R12, a resistor R13, a resistor R14, and a resistor R15. The non-inverting input terminal of the error comparator is grounded. The inverting input terminal of the error comparator is connected to the first ends of the resistor R13, the resistor R14, and the resistor R15. The second end of the resistor R13 is connected to the node voltage. The second end of the resistor R14 is connected to the stationary contact of the switching switch SW2. The first moving contact of the switching switch SW2 is connected to the current loop. The second moving contact of the switching switch SW2 is connected to the voltage loop. The second end of the resistor R15 is connected to the output terminal of the error comparator. The first end of the resistor R11 is connected to the output terminal of the error comparator. The second end of the resistor R11 is connected to the clamping circuit and the first end of the resistor R12. The second end of the resistor R12 is connected to the integration circuit.

[0010] In one embodiment, the integration circuit includes an integrator and a capacitor. The non-inverting input terminal of the integrator is grounded. The inverting input terminal of the integrator is connected to the second end of the resistor R12 and the first end of the capacitor. The second end of the capacitor is connected to the output terminal of the integrator. The output terminal of the integrator is connected to the power amplifier.

[0011] In one embodiment, the current loop includes a sampling resistor Rs and an instrumentation amplifier U3. The first end of the sampling resistor Rs is connected to the power amplifier. The second end of the sampling resistor Rs is connected to the first end of the load. The non-inverting input terminal of the instrumentation amplifier U3 is connected to the first end of the sampling resistor Rs. The inverting input terminal of the instrumentation amplifier U3 is connected to the second end of the sampling resistor Rs. The output terminal of the instrumentation amplifier U3 is connected to the error comparison circuit and the clamping circuit.

[0012] In one embodiment, the voltage loop includes an instrumentation amplifier U4. The non-inverting input terminal of the instrumentation amplifier U4 is connected to the first end of the load, the inverting input terminal of the instrumentation amplifier U4 is connected to the second end of the load, and the output terminal of the instrumentation amplifier U4 is connected to the error comparison circuit and the clamping circuit.

[0013] In one embodiment, the clamping circuit includes a switching switch SW3, an input resistance circuit, a feedback resistance circuit, an output circuit, and more than two operational amplifiers. The stationary contact of the switching switch SW3 is connected to the input resistance circuit, the first moving contact of the switching switch SW3 is connected to the voltage loop, the second moving contact of the switching switch SW3 is connected to the current loop, the input resistance circuit is connected to the non-inverting input terminals of the operational amplifiers, the feedback resistance circuit is connected to the inverting input terminals of the operational amplifiers and the main loop, and the output terminals of the operational amplifiers are connected to the main loop through the output circuit.

[0014] In one embodiment, the operational amplifiers include an amplifier U5 and an amplifier U6; the input resistance circuit includes a resistor R5, a resistor R6, a resistor R7, and a resistor R8 connected in series in sequence, and the other end of the resistor R5 is connected to a negative voltage, the other end of the resistor R8 is connected to a positive voltage, the common terminal of the resistor R5 and the resistor R6 is connected to the non-inverting input terminal of the amplifier U5, the common terminal of the resistor R6 and the resistor R7 is connected to the stationary contact of the switching switch SW3, and the common terminal of the resistor R7 and the resistor R8 is connected to the non-inverting input terminal of the amplifier U6.

[0015] In one embodiment, the feedback resistance circuit includes a resistor R3, a resistor R4, and a resistor network. The first end of the resistor R3 is connected to the inverting input terminals of the amplifier U5, the amplifier U6, and the first end of the resistor R4, the second end of the resistor R3 is connected to the main loop, the second end of the resistor R4 is grounded, and the resistor network is connected in parallel with the resistor R3;

[0016] The output circuit includes a diode D1 and a diode D2. The anode of the diode D1 is connected to the output terminal of the amplifier U5, the cathode of the diode D1 is connected to the anode of the diode D2 and the main loop, and the cathode of the diode D2 is connected to the output terminal of the amplifier U6.

[0017] The second aspect of the present application provides a testing machine, including a measurement module and the above-mentioned power supply device. The measurement module is connected to the current loop and the voltage loop, and performs parameter measurement according to the detected current output by the current loop and the detected voltage output by the voltage loop; wherein, the parameter measurement modes include at least one of a voltage application and voltage measurement mode, a voltage application and current measurement mode, a current application and voltage measurement mode, and a current application and current measurement mode.

[0018] In the above power supply device and testing machine, in the pressurization mode, when the detected current output by the current loop is within the set current clamping range, the output impedance of the clamping circuit is high impedance; when the detected current output by the current loop is not within the set current clamping range, the clamping current is triggered for analog output, and the output impedance is switched to low impedance, so that the output of the main loop is equivalent to a constant current source. In the current addition mode, when the detected voltage output by the voltage loop is within the set voltage clamping range, the output impedance of the clamping circuit is high impedance; when the detected voltage output by the voltage loop is not within the set voltage clamping range, the clamping voltage is triggered for analog output, and the output impedance is switched to low impedance, so that the output of the main loop is equivalent to a constant voltage source. By using the clamping circuit to monitor the current in the pressurization mode and detect the voltage in the current addition mode, when the current / voltage is not within the corresponding clamping range, the clamping current / clamping voltage is triggered, and the output impedance is switched to low impedance by using the analog loop regulation, so that the output of the main loop is equivalent to a constant current source / constant voltage source, realizing the analog regulation function and having a fast response speed. Description of the Drawings

[0019] Figure 1 It is a schematic structural diagram of a power supply device in an embodiment;

[0020] Figure 2 It is a schematic structural principle diagram of the main loop, voltage loop, and current loop in an embodiment;

[0021] Figure 3 It is a schematic structural principle diagram of the clamping circuit in an embodiment. Detailed Embodiment

[0022] In order to make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0024] It can be understood that "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is an electrical signal or data transfer between the connected circuits, modules, units, etc.

[0025] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising", "has / including", etc. specify the presence of the stated features, integers, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, operations, components, parts, or combinations thereof.

[0026] In one embodiment, a power supply device is provided, which may specifically be a VI (voltage-current) source, such as Figure 1 As shown, the power supply device includes a main loop 110, a current loop 120, a voltage loop 130, and a clamping circuit 140. The main loop 110 is connected to the current loop 120, the current loop 120 is connected to a load DUT, the voltage loop 130 is connected to the load DUT, and the clamping circuit 140 is connected to the voltage loop 130, the current loop 120, and the main loop 110. The current loop 120 is used to detect the current of the load DUT and output the detected current to the clamping circuit 140. The voltage loop 130 is used to detect the voltage of the load DUT and output the detected voltage to the clamping circuit 140. The main loop 110 selects to access the detected voltage output by the voltage loop 130 or the detected current output by the current loop 120. Among them, the load DUT may be a chip under test or other semiconductor devices under test. The voltage loop 130 is connected to the first end of the load DUT through a high-potential measurement line HS and to the second end of the load DUT through a low-potential measurement line LS to detect the voltage across the load DUT, and the second end of the load DUT may be grounded. The main loop 110 selects to access the detected current output by the current loop 120 or the detected voltage output by the voltage loop 130 according to the actual working mode to perform current or voltage regulation and achieve constant current or constant voltage output. Correspondingly, the clamping circuit 140 selects to access the detected voltage output by the voltage loop 130 or the detected current output by the current loop 120 to analyze whether a voltage clamping or current clamping action needs to be performed.

[0027] In the forced voltage (FV) mode, the main loop 110 is adjusted according to the accessed node voltage FIN_DAC and the detected voltage output by the voltage loop 130, and outputs a constant voltage to the load DUT; when the detected current output by the current loop 120 is within the set current clamping range, the clamping circuit 140 outputs a high impedance; when the detected current output by the current loop 120 is not within the set current clamping range, the clamping circuit 140 triggers current clamping for analog output and switches the output impedance to a low impedance, so that the output of the main loop 110 is equivalent to a constant current source. In the forced current (FI) mode, the main loop 110 is adjusted according to the accessed node voltage FIN_DAC and the detected current output by the current loop 120, and outputs a constant current to the load DUT; when the detected voltage output by the voltage loop 130 is within the set voltage clamping range, the clamping circuit 140 outputs a high impedance; when the detected voltage output by the voltage loop 130 is not within the set voltage clamping range, the clamping circuit 140 triggers voltage clamping for analog output and switches the output impedance to a low impedance, so that the output of the main loop 110 is equivalent to a constant voltage source.

[0028] Specifically, the specific numerical ranges of the current clamping range and the voltage clamping range are not unique and can be set according to actual needs. In the voltage application mode, the clamping circuit 140 compares the detected current output by the current loop 120 with the set current clamping range to determine whether to trigger current clamping. If the detected current is within the current clamping range, current clamping is not triggered, and the output impedance of the clamping circuit 140 is high impedance; if the detected current is not within the current clamping range, current clamping is triggered, the output impedance of the clamping circuit 140 is low impedance, and the output of the main loop 110 is equivalent to a constant current source, and the current is output according to the set current clamping value. In the current application mode, the clamping circuit 140 compares the detected voltage output by the voltage loop 130 with the set voltage clamping range to determine whether to trigger voltage clamping; if the detected voltage is within the voltage clamping range, voltage clamping is not triggered, the output impedance of the clamping circuit 140 is high impedance, if the detected voltage is not within the clamping range, voltage clamping is triggered, the output impedance of the clamping circuit 140 is low impedance, and the output of the main loop 110 is equivalent to a constant voltage source, and the voltage is output according to the set voltage clamping value. The working principle of the clamping circuit 140 is to build an operational amplifier to amplify the difference by a set amplification factor when the voltage or current exceeds the range to generate an analog output, and use an analog loop adjustment to switch the output impedance to low impedance, so that the output of the main loop 110 is equivalent to a constant current source / constant voltage source, which is automatically and real-time adjusted by hardware negative feedback, suitable for clamping protection of the VI source, and has a fast response speed, with a response speed of the order of microseconds. Among them, the amplification factor of the clamping circuit 140 is adjustable. For example, by switching the connection relationship between components such as resistors configured in the internal operational amplifier, the amplification factor of the difference can be changed, and the clamping circuit 140 can include at least two levels of amplification factors to adapt to different application scenarios. In addition, the power supply device may further include a switch SW0, and the current loop 120 is connected to the first end of the load DUT through the switch SW0.

[0029] It can be understood that the specific circuit structures of the various modules in the power supply device are not unique. In one embodiment, as Figure 2As shown, the main loop 110 includes an error comparison circuit 112, an integration circuit 114, and a power amplifier PA. The error comparison circuit 112 is connected to the integration circuit 114, a clamping circuit 140, a current loop 120, and a voltage loop 130. The power amplifier PA is connected to the integration circuit 114 and the current loop 120. According to the actual working mode, the error comparison circuit 112 accesses the detected current output by the current loop 120 or the detected voltage output by the voltage loop 130, compares the node voltage FIN_DAC with the accessed detected current / detected voltage, outputs the comparison result to the integration circuit 114 for processing, and then outputs it after being amplified by the power amplifier PA. When the circuit reaches a steady state, the output of the error comparison circuit 112 is 0, and the output of the integration circuit 114 is stable. When the clamping circuit 140 does not trigger voltage clamping or current clamping, the input of the integration circuit 114 is affected by the output of the error comparison circuit 112. When the clamping circuit 140 triggers voltage clamping or current clamping, the input of the integration circuit 114 is only affected by the output of the clamping circuit 140.

[0030] Among them, the error comparison circuit 112 includes an error comparator U1, a switching switch SW2, resistors R11, R12, R13, R14, and R15. The non-inverting input terminal of the error comparator U1 is grounded. The inverting input terminal of the error comparator is connected to the first ends of the resistor R13, the resistor R14, and the resistor R15. The second end of the resistor R13 is connected to the node voltage FIN_DAC. The second end of the resistor R14 is connected to the stationary contact of the switching switch SW2. The first moving contact of the switching switch SW2 is connected to the current loop 120. The second moving contact of the switching switch SW2 is connected to the voltage loop 130. The second end of the resistor R15 is connected to the output terminal of the error comparator U1. The first end of the resistor R11 is connected to the output terminal of the error comparator U1. The second end of the resistor R11 is connected to the clamping circuit 140 and the first end of the resistor R12. The second end of the resistor R12 is connected to the integration circuit 114. By controlling the switching switch SW2, the current loop 120 or the voltage loop 130 can be connected, so as to access the detected current or detected voltage to the error comparator U1. Further, the integration circuit 114 includes an integrator U2 and a capacitor C1. The non-inverting input terminal of the integrator U2 is grounded. The inverting input terminal of the integrator U2 is connected to the second end of the resistor R12 and the first end of the capacitor C1. The second end of the capacitor C2 is connected to the output terminal of the integrator U2. The output terminal of the integrator U2 is connected to the power amplifier PA.

[0031] In one embodiment, continue to refer to Figure 2, the current loop 120 may include a sampling resistor Rs and an instrumentation amplifier U3. The first end of the sampling resistor Rs is connected to the power amplifier PA, and the second end of the sampling resistor Rs is connected to the first end of the load DUT. Specifically, the second end of the sampling resistor Rs is connected to the first end of the load DUT through a switch SW0. A high-potential application line HF is connected between the first end of the load DUT and the switch SW0, and a low-potential application line LF is connected between the second end of the load DUT and the ground terminal. The non-inverting input terminal of the instrumentation amplifier U3 is connected to the first end of the sampling resistor Rs, the inverting input terminal of the instrumentation amplifier U3 is connected to the second end of the sampling resistor Rs, and the output terminal of the instrumentation amplifier U3 is connected to the error comparison circuit 112 and the clamping circuit 140, specifically connected to the first moving contact of the switching switch SW2 in the error comparison circuit 112. Further, the voltage loop 130 may include an instrumentation amplifier U4. The non-inverting input terminal of the instrumentation amplifier U4 is connected to the first end of the load DUT, the inverting input terminal of the instrumentation amplifier U4 is connected to the second end of the load DUT, and the output terminal of the instrumentation amplifier U4 is connected to the error comparison circuit 112 and the clamping circuit 140, specifically connected to the second moving contact of the switching switch SW2 in the error comparison circuit 112.

[0032] In addition, the output terminals of the instrumentation amplifier U3 and the instrumentation amplifier U4 may also be connected to the measurement unit MEASURE through a switching switch SW1, and the detection current and detection voltage are accessed through the measurement unit MEASURE for parameter measurement.

[0033] Referring to Figure 2 , the pressurization (FV) function principle of the power supply device is as follows: The switching switch SW2 is turned on to connect the voltage loop 130, the node voltage FIN_DAC is set, the detected voltage output by the voltage loop 130 is received, the main loop 110, the load, and the voltage loop 130 form a feedback regulation loop, and the main loop 110 is regulated based on the set node voltage FIN_DAC and the detected voltage fed back by the voltage loop 130, so that the FORCE terminal outputs a constant voltage. Specifically, the voltage loop 130 detects the voltage V at both ends of the load DUT DUT , assuming that the gain of the voltage loop 130 is A V1 , using V HS and V LS to represent the node voltages of the high-potential measurement line HS and the low-potential measurement line LS respectively, V DUT = V HS - V LS , the node voltage FIN_DAC is represented as V DAC . When the circuit reaches a steady state, the output of the error comparator U1 is 0, and the integrator U2 outputs stably. At this time, V DUT = V DAC / A V1 .

[0034] The current addition (FI) function principle of the power supply device is as follows: The switching switch SW2 connects the current loop 120, sets the node voltage FIN_DAC, receives the detected current output by the current loop 120. The main loop 110 and the current loop 120 form a feedback loop. The main loop 110 adjusts based on the set node voltage FIN_DAC and the detected current fed back by the current loop 120, so that a constant current is output at the FORCE terminal. The current loop 120 samples the voltage drop across both ends of the sampling resistor Rs and divides it by the resistance value of the sampling resistor Rs, which is the current flowing through both ends of the load DUT. Assume the gain of the current loop 120 is A I1 , the resistance value of the sampling resistor Rs is Rs. When the circuit reaches a steady state, the output of the error comparator U1 is 0, and the output of the integrator U2 is stable. At this time, I = V DAC / (A I1 *Rs).

[0035] The voltage measurement (MV) function principle of the power supply device is as follows: The switching switch SW1 is closed, and the internal ADC (analog-to-digital converter) of the measurement unit MEASURE acquires the MV node voltage V ADC , and calculates the load voltage according to V DUT = V ADC / -A V1 . The current measurement (MI) function principle of the power supply device is as follows: The switching switch SW1 is closed, and the internal ADC of the measurement unit MEASURE acquires the MI node voltage V ADC , and calculates the current flowing through the load resistor Rs according to I = V ADC / (-A I1 *Rs).

[0036] The function principle of the power supply device for pressure addition and voltage measurement (FVMV) is as follows: The switching switch SW1 is closed, the switching switch SW2 connects the voltage loop 130. While a constant voltage is output at the FORCE terminal, the voltage across the load DUT is measured. The function principle of the power supply device for pressure addition and current measurement (FVMI) is as follows: The switching switch SW1 is closed, the switching switch SW2 connects the voltage loop 130. While a constant voltage is output at the FORCE terminal, the current flowing through the load DUT is measured. The function principle of the power supply device for current addition and voltage measurement (FIMV) is as follows: The switching switch SW1 is closed, the switching switch SW2 connects the current loop 120. While a constant current is output at the FORCE terminal, the voltage across the load DUT is measured. The function principle of the power supply device for current addition and current measurement (FIMI) is as follows: The switching switch SW1 is closed, the switching switch SW2 connects the current loop 120. While a constant current is output at the FORCE terminal, the current flowing through the load DUT is measured.

[0037] The principle of the forced voltage and current clamping (FVCI) function of the power supply device is as follows: The switching switch SW2 connects to the voltage loop 130, and the FORCE terminal outputs a constant voltage. When the current clamping is not triggered, the output impedance of the clamping circuit 140 is high impedance, and the input of the integrator U2 is affected by the output of the error comparator U1. When the current clamping is triggered, the output impedance of the clamping circuit 140 is low impedance, and the input of the integrator U2 is only affected by the output of the clamping circuit 140. The output of the FORCE terminal is equivalent to a constant current source, and the current is output according to the set current clamping value.

[0038] The principle of the forced current and voltage clamping (FICV) function of the power supply device is as follows: The switching switch SW2 connects to the current loop 120, and the FORCE terminal outputs a constant current. When the voltage clamping is not triggered, the output impedance of the clamping circuit 140 is high impedance, and the input of the integrator U2 is affected by the output of the error comparator U1. When the voltage clamping is triggered, the output impedance of the clamping circuit 140 is low impedance, and the input of the integrator U2 is only affected by the output of the clamping circuit 140. The output of the FORCE terminal is equivalent to a constant voltage source, and the voltage is output according to the set voltage clamping value.

[0039] In one embodiment, as Figure 3 shown, the clamping circuit 140 includes a switching switch SW3, an input resistance circuit 142, a feedback resistance circuit 144, an output circuit 146, and two or more operational amplifiers. The stationary contact of the switching switch SW3 is connected to the input resistance circuit 142. The first moving contact of the switching switch SW3 is connected to the voltage loop 130, specifically to the output terminal of the instrumentation amplifier U4. The second moving contact of the switching switch SW3 is connected to the current loop 120, specifically to the output terminal of the instrumentation amplifier U3. The input resistance circuit 142 is connected to the non-inverting input terminals of the operational amplifiers. The feedback resistance circuit 144 is connected to the inverting input terminals of the operational amplifiers and the main loop 110, specifically to the second end of the resistor R11 and the first end of the resistor R12. The output terminals of the operational amplifiers are connected to the main loop 110 through the output circuit 146, specifically to the second end of the resistor R11 and the first end of the resistor R12. By controlling the switching switch SW3, the detected current output by the current loop 120 or the detected voltage output by the voltage loop 130 can be switched to be connected, and it can be determined whether the current clamping or voltage clamping action is required.

[0040] Among them, the number of operational amplifiers can be two or more. In this embodiment, the operational amplifiers include amplifier U5 and amplifier U6. The input resistance circuit 142 includes resistors R5, R6, R7, and R8 connected in series in sequence. The other end of resistor R5 is connected to the negative voltage Clamp_N_DAC, the other end of resistor R8 is connected to the positive voltage Clamp_P_DAC. The common terminal of resistor R5 and resistor R6 is connected to the non-inverting input terminal of amplifier U5. The common terminal of resistor R6 and resistor R7 is connected to the stationary contact of switch SW3. The common terminal of resistor R7 and resistor R8 is connected to the non-inverting input terminal of amplifier U6. Further, the feedback resistance circuit 144 may include resistor R3, resistor R4, and a resistor network. The first end of resistor R3 is connected to the inverting input terminals of amplifier U5 and amplifier U6 and the first end of resistor R4. The second end of resistor R3 is connected to the main loop, specifically connected to the second end of resistor R11 and the first end of resistor R12. The second end of resistor R4 is grounded. The resistor network is in parallel with resistor R3. Among them, the resistor network includes at least one group of switches and resistors. The switches and resistors in the same group are connected in series and then in parallel with resistor R3. For example, the resistor network may include switch SW4 and resistor R2. Switch SW4 and resistor R2 are connected in series and then in parallel with resistor R3.

[0041] The output circuit 146 may include diode D1 and diode D2. The anode of diode D1 is connected to the output terminal of amplifier U5. The cathode of diode D1 is connected to the anode of diode D2 and the main loop 110, specifically connected to the second end of resistor R11 and the first end of resistor R12. The cathode of diode D2 is connected to the output terminal of amplifier U6.

[0042] Referring to Figure 3 , taking the clamping as an example, the load voltage V DUT =-MV_Clamp. The switch SW4 adjusts the amplification factor of the clamping circuit 140. Clamp_N_DAC is a negative voltage. When V DUT <Clamp_N_DAC, the negative clamping is triggered. Clamp_P_DAC is a positive voltage. When V DUT >Clamp_P_DAC, the positive clamping is triggered. The relationship between the input and the output is as follows. Taking the case where switch SW4 is off as an example,

[0043]

[0044] Among them, when the detected voltage is greater than or equal to the negative voltage and less than or equal to the positive voltage, amplifiers U5 and U6 have no output, and the output of the clamping circuit 140 is related to the feedback resistor circuit 144. Specifically, resistors R2, R3, and R4 can be designed as high-value resistors to make the output of the clamping circuit 140 have a high impedance. When the detected voltage is less than the negative voltage or greater than the positive voltage, amplifier U5 or amplifier U6 outputs a voltage, and diode D1 or diode D2 conducts. Amplifier U5, diode D1, and resistors R3 and R4 form a non-inverting operational amplifier, or amplifier U6, diode D2, and resistors R3 and R4 form a non-inverting operational amplifier, so that the output of the clamping circuit 140 switches to a low impedance.

[0045] It can be understood that the principle of regulating the clamping current of the clamping circuit 140 is similar to the principle of clamping voltage, which will not be elaborated here.

[0046] The principle of forced voltage clamping current (FVCI) can be summarized as follows:

[0047] Step 1: In the initial circuit, switch SW0 and switch SW1 are closed, switch SW2 connects to the voltage loop 130, switch SW3 connects to the MI_Clamp node of the current loop 120, the input of the main loop 110 is the node voltage FIN_DAC. At this time, the value of FIN_DAC is 0, the output values of the voltage loop 130 and the current loop 120 are both 0, the voltage value of node MV is 0, and the output of the clamping circuit 140 has a high impedance, where the voltage value of node MV is the voltage value at the node where the measurement module is connected to the voltage loop.

[0048] Step 2: When the value of the node voltage FIN_DAC is the set value, the detected voltage output by the voltage loop 130 is input to the error comparator U1. The node voltage FIN_DAC and the detected voltage output by the voltage loop 130 are compared for error in the error comparator U1 to obtain the output voltage of the error comparator U1.

[0049] Step 3: The output voltage of the error comparator U1 is input to the integrator U2, and the integrator U2 controls the output of the power amplifier PA.

[0050] Step 4: The output voltage of the power amplifier PA generates a voltage V on the load DUT. DUT The voltage loop 130 collects the voltage V DUT as a feedback signal and inputs it to the main loop 110. The voltage value of node MV is the collected voltage V of the voltage loop 130. DUT value;

[0051] Step 5: During the above process, the current of the load DUT flows through the sampling resistor Rs of the current loop 120, generating a voltage drop, which is then signal-conditioned by the current loop 120. The output MI_Clamp signal is input to the clamping circuit 140 through the MI_Clamp node, where the MI_Clamp signal is the MI_Clamp current value;

[0052] Step 6: The MI_Clamp signal enters the clamping circuit 140. If the -MI_Clamp current value exceeds the positive clamping value or is lower than the negative clamping value, the node Clamp_OUT of the clamping circuit 140 outputs a negative voltage or a positive voltage. The output impedance of the clamping circuit 140 is a low resistance, close to 0Ω, equivalent to an ideal voltage source. Under the action of the resistor R11 in the main loop 110, the input of the integrator U2 is only affected by the output of the clamping circuit 140, and the output of the clamping circuit 140 will forcibly change the output of the integrator U2. After triggering the current clamping, the output of the main loop is equivalent to a constant current source, and the current is output according to the set current clamping value. If it does not exceed the clamping range, the output of the node Clamp_OUT of the clamping circuit 140 is a high resistance, and the input of the integrator U2 is only affected by the output of the error comparator U1.

[0053] The principle of the current clamping and voltage clamping (FICV) can be summarized as follows:

[0054] Step 1: In the initial circuit, the switching switch SW0 and the switching switch SW1 are closed, the switching switch SW2 is connected to the current loop 120, the switching switch SW3 is connected to the MV_Clamp node of the voltage loop 130, and the input of the main loop 110 is the node voltage FIN_DAC. At this time, the value of FIN_DAC is 0, the output values of both the voltage loop 130 and the current loop 120 are 0, the node MI current value is 0, and the output of the clamping circuit 140 is a high resistance, where the node MI current value is the current value at the node where the measurement module is connected to the current loop.

[0055] Step 2: The node voltage FIN_DAC and the voltage output by the current loop 120 are error-compared in the error comparator U1 to obtain the output voltage of the error comparator, where the voltage output by the current loop 120 is determined according to the detected current and the resistor Rs of the current loop 120;

[0056] Step 3: The output voltage of the error comparator U1 is input to the integrator U2, and the integrator U2 controls the output of the power amplifier PA;

[0057] Step 4: The output current of the power amplifier PA generates a voltage drop on the sampling resistor Rs, which is conditioned by the current loop 120 and then input to the main loop 110 as a feedback signal, that is, the node MI current value is the feedback signal;

[0058] Step 5: In the above steps, the voltage loop 130 continuously detects the voltage V of the load DUT DUT, the voltage loop 130 outputs the MV_Clamp signal, which is output to the clamping circuit 140 via the MV_Clamp node. The MV_Clamp signal is the voltage V DUT .

[0059] Step 6: The MV_Clamp signal enters the clamping circuit 140. If -MV_Clamp exceeds the positive clamping value or is lower than the negative clamping value, the clamping circuit 140 outputs a negative voltage or a positive voltage at the Clamp_OUT node. The output impedance of the clamping circuit 140 is low impedance, close to 0Ω, equivalent to an ideal voltage source. Under the action of the resistor R11, the input of the integrator U2 is only affected by the output of the clamping circuit 140, and the output of the clamping circuit 140 will forcefully change the output of the integrator. After the clamping voltage is triggered, the output of the main loop is equivalent to a constant voltage source, and the voltage is output according to the set clamping voltage value. If it does not exceed the clamping range, the clamping circuit 140 outputs a high impedance at the Clamp_OUT node, and the input of the integrator U2 is only affected by the output of the error comparator U1.

[0060] In one embodiment, a testing machine is further provided, including a measurement module and the above-mentioned power supply device. The measurement module is connected to the current loop and the voltage loop, and performs parameter measurement according to the detected current output by the current loop and the detected voltage output by the voltage loop. Among them, the parameter measurement modes include at least one of a voltage application and voltage measurement mode, a voltage application and current measurement mode, a current application and voltage measurement mode, and a current application and current measurement mode. As Figure 2 shown, the measurement module may specifically include a measurement unit MEASURE and a switching switch SW1. The measurement unit MEASURE is connected to the output terminals of the instrumentation amplifier U3 and the instrumentation amplifier U4 through the switching switch SW1.

[0061] The above-mentioned power supply device and testing machine have the following advantages:

[0062] 1. The response speed of the clamping circuit 140 is fast. The clamping adjustment process does not require digital intervention and adopts an analog loop adjustment. When the input of the clamping circuit 140 exceeds the clamping setting range, the difference will be amplified by a factor of (1 + R3 / R4). The output of the clamping circuit 140 forces a change in the input of the integrator U2, and is automatically and real-time adjusted by hardware negative feedback. By selecting an operational amplifier with high bandwidth and high slew rate, the clamping circuit 140 can achieve an adjustment speed at the microsecond level.

[0063] 2. The clamping circuit 140 is selectively connected to the voltage loop 130 or the current loop 120 and adaptively connected to the output of the main loop 110 to form a voltage clamping current mode and a current clamping voltage mode, saving design costs. Specifically, the clamping circuit 140 is selectively connected to the voltage loop 130 and the current loop 120 through the switching switch SW3. The voltage clamping range or the current potential range is set by the positive voltage Clamp_P_DAC and the negative voltage Clamp_N_DAC. The input of the clamping circuit 140 comes from the output of the voltage loop 130 or the current loop 120. If the gain coefficient of the amplifier in the voltage loop 130 or the current loop 120 is changed, the output voltage or current range of the main loop 110 can be expanded, while the output range of the voltage loop 130 or the current loop 120 will not be affected by the gain. This enables the positive voltage Clamp_P_DAC and the negative voltage Clamp_N_DAC of the clamping circuit 140 to adapt to the voltage or current level of the FORCE terminal with only one gear configured.

[0064] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0065] The above-described embodiments merely represent several implementation manners of the present application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the utility model patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A power supply device, characterized in that, It includes a main loop, a voltage loop, a current loop, and a clamping circuit. The main loop is connected to the current loop, the current loop is connected to a load, the voltage loop is connected to the load, and the clamping circuit is connected to the voltage loop, the current loop, and the main loop. The current loop is used to detect the current of the load and output a detected current to the clamping circuit. The voltage loop is used to detect the voltage of the load and output a detected voltage to the clamping circuit. The main loop selectively accesses the detected voltage output by the voltage loop or the detected current output by the current loop. In the voltage application mode, when the detected current output by the current loop is within the set current clamping range, the output impedance of the clamping circuit is high impedance. When the detected current output by the current loop is not within the set current clamping range, the clamping current is triggered for analog output, and the output impedance is switched to low impedance, so that the output of the main loop is equivalent to a constant current source. In the current application mode, when the detected voltage output by the voltage loop is within the set voltage clamping range, the output impedance of the clamping circuit is high impedance. When the detected voltage output by the voltage loop is not within the set voltage clamping range, the clamping voltage is triggered for analog output, and the output impedance is switched to low impedance, so that the output of the main loop is equivalent to a constant voltage source.

2. The power supply device according to claim 1, wherein The main loop includes an error comparison circuit, an integration circuit, and a power amplifier. The error comparison circuit is connected to the integration circuit, the clamping circuit, the current loop, and the voltage loop. The power amplifier is connected to the integration circuit and the current loop.

3. The power supply device according to claim 2, wherein The error comparison circuit includes an error comparator, a switching switch SW2, resistors R11, R12, R13, R14, and R15. The non-inverting input terminal of the error comparator is grounded. The inverting input terminal of the error comparator is connected to the first ends of resistors R13, R14, and R15. The second end of resistor R13 is connected to a node voltage. The second end of resistor R14 is connected to the stationary contact of switching switch SW2. The first moving contact of switching switch SW2 is connected to the current loop. The second moving contact of switching switch SW2 is connected to the voltage loop. The second end of resistor R15 is connected to the output terminal of the error comparator. The first end of resistor R11 is connected to the output terminal of the error comparator. The second end of resistor R11 is connected to the clamping circuit and the first end of resistor R12. The second end of resistor R12 is connected to the integration circuit.

4. The power supply device according to claim 3, characterized in that, The integration circuit includes an integrator and a capacitor. The non-inverting input terminal of the integrator is grounded. The inverting input terminal of the integrator is connected to the second end of resistor R12 and the first end of the capacitor. The second end of the capacitor is connected to the output terminal of the integrator. The output terminal of the integrator is connected to the power amplifier.

5. The power supply device according to claim 2, characterized in that, The current loop includes a sampling resistor Rs and an instrumentation amplifier U3. The first end of the sampling resistor Rs is connected to the power amplifier, the second end of the sampling resistor Rs is connected to the first end of the load, the non-inverting input terminal of the instrumentation amplifier U3 is connected to the first end of the sampling resistor Rs, the inverting input terminal of the instrumentation amplifier U3 is connected to the second end of the sampling resistor Rs, and the output terminal of the instrumentation amplifier U3 is connected to the error comparison circuit and the clamping circuit.

6. The power supply device according to claim 2, characterized in that The voltage loop includes an instrumentation amplifier U4. The non-inverting input terminal of the instrumentation amplifier U4 is connected to the first end of the load, the inverting input terminal of the instrumentation amplifier U4 is connected to the second end of the load, and the output terminal of the instrumentation amplifier U4 is connected to the error comparison circuit and the clamping circuit.

7. The power supply device according to claim 1, characterized in that, The clamping circuit includes a switching switch SW3, an input resistance circuit, a feedback resistance circuit, an output circuit, and more than two operational amplifiers. The stationary contact of the switching switch SW3 is connected to the input resistance circuit, the first moving contact of the switching switch SW3 is connected to the voltage loop, the second moving contact of the switching switch SW3 is connected to the current loop, the input resistance circuit is connected to the non-inverting input terminals of the operational amplifiers, the feedback resistance circuit is connected to the inverting input terminals of the operational amplifiers and the main loop, and the output terminals of the operational amplifiers are connected to the main loop through the output circuit.

8. The power supply device according to claim 7, characterized in that, The operational amplifier includes an amplifier U5 and an amplifier U6; the input resistance circuit includes a resistor R5, a resistor R6, a resistor R7, and a resistor R8 connected in series in sequence, and the other end of the resistor R5 is connected to a negative voltage, the other end of the resistor R8 is connected to a positive voltage, the common terminal of the resistor R5 and the resistor R6 is connected to the non-inverting input terminal of the amplifier U5, the common terminal of the resistor R6 and the resistor R7 is connected to the stationary contact of the switching switch SW3, and the common terminal of the resistor R7 and the resistor R8 is connected to the non-inverting input terminal of the amplifier U6.

9. The power supply device according to claim 8, wherein The feedback resistance circuit includes a resistor R3, a resistor R4, and a resistor network. The first end of the resistor R3 is connected to the inverting input terminals of the amplifier U5, the amplifier U6, and the first end of the resistor R4, the second end of the resistor R3 is connected to the main loop, the second end of the resistor R4 is grounded, and the resistor network is connected in parallel with the resistor R3; The output circuit includes a diode D1 and a diode D2. The anode of the diode D1 is connected to the output terminal of the amplifier U5, the cathode of the diode D1 is connected to the anode of the diode D2 and the main loop, and the cathode of the diode D2 is connected to the output terminal of the amplifier U6.

10. A testing machine, characterized in that, It includes a measurement module and the power supply device according to any one of claims 1-9. The measurement module is connected to the current loop and the voltage loop, and performs parameter measurement according to the detected current output by the current loop and the detected voltage output by the voltage loop; wherein, the parameter measurement modes include at least one of a voltage measurement mode under voltage application, a current measurement mode under voltage application, a voltage measurement mode under current application, and a current measurement mode under current application.

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