Fin field effect transistor device

Abstract

A fin field effect transistor device is provided. In one example, a fin field effect transistor (FinFET) device includes a substrate, a fin structure disposed on the substrate, a segmented channel region formed in the fin structure, two source / drain regions separated by the segmented channel region, and a gate structure surrounding the segmented channel region. The segmented channel area further comprises a plurality of channel sections sequentially arranged in the segmented channel area, and the channel sections comprise the first channel section and the second channel section. The first channel section includes a first channel barrier material dispersed in the first channel section and has a first energy barrier. When the FinFET device is not started, the carrier flow path of the first energy barrier between the two source / drain regions is at least 0.1 electron volt.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to semiconductor devices, and more particularly, to fin field-effect transistor (FET) devices. Background Art

[0002] The semiconductor industry has advanced to nanotechnology process nodes to pursue higher device density, higher performance, and lower costs. With this development, challenges from manufacturing and design issues have shaped the development of three-dimensional designs, such as fin field-effect transistor (FinFET) devices and gate all-around (GAA) nanosheet or nanowire channel field-effect transistor (GAAFET). A typical FinFET device is made of thin "fins" (or fin structures) extending from a substrate. The fins typically comprise silicon and form the body of the transistor device. The channel of the transistor is formed in the vertical fins. A gate is disposed above the fins (e.g., surrounding the fins). This type of gate can better control the channel. Other advantages of FinFET devices include reduced short-channel effects and higher current. Summary of the Utility Model

[0003] Some embodiments of the present disclosure provide a fin field-effect transistor device. The fin field-effect transistor device includes a substrate, a fin structure disposed on the substrate and extending along a horizontal direction, a segmented channel region formed in the fin structure and extending along the horizontal direction, two source / drain regions formed in the fin structure and separated by the segmented channel region, and a gate structure formed on the fin structure and surrounding the segmented channel region. The segmented channel region includes a plurality of channel segments sequentially disposed in the segmented channel region and extending along the horizontal direction, and the plurality of channel segments includes a first channel segment and a second channel segment. The first channel segment includes a first channel blocking material and has a first energy barrier, and when the fin field-effect transistor device is not activated, the first energy barrier of the carrier flow path between the two source / drain regions is at least 0.1 electron volts.

[0004] Some embodiments of the present disclosure provide a fin field-effect transistor device. The fin field-effect transistor device includes a substrate, a fin structure disposed on the substrate and extending along a horizontal direction, a segmented channel region formed in the fin structure and extending along the horizontal direction, two source / drain (S / D) regions formed in the fin structure and separated by the segmented channel region, and a gate structure formed on the fin structure and surrounding the segmented channel region. The segmented channel region includes a first channel segment, a second channel segment, a third channel segment, a fourth channel segment, and a fifth channel segment sequentially arranged along the horizontal direction. The second channel segment is located between the first channel segment and the third channel segment, and the fourth channel segment is located between the third channel segment and the fifth channel segment. The second channel segment includes a first channel blocking material and has a first energy barrier, and the fourth channel segment includes a second channel blocking material and has a second energy barrier. When the fin field-effect transistor device is not activated, the first energy barrier and the second energy barrier of the carrier flow path between the two source / drain regions are at least 0.1 electron volts.

[0005] Some embodiments of the present disclosure provide a fin field-effect transistor device, and include a substrate, a fin structure, a shallow trench isolation, two source / drain regions, a channel region, and a gate structure. The fin structure is disposed on the substrate and extends along a horizontal direction. The shallow trench isolation is disposed in the substrate and is located on both sides of the fin structure. The two source / drain regions are disposed in at least one fin structure. The channel region is disposed in the fin structure and is located between the two source / drain regions, and the channel region includes channel segments. The gate structure is disposed on the fin structure and surrounds the channel region of the fin structure. The channel segment has an energy barrier, and when the fin field-effect transistor device is not activated, the energy barrier of the carrier flow path between the two source / drain regions is at least 0.1 electron volts. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that various features are not drawn to scale in accordance with standard practice in the industry. In practice, for clarity of discussion, the dimensions of various features may be increased or decreased arbitrarily.

[0007] Figure 1A A perspective schematic diagram of an example FinFET device according to some embodiments is shown;

[0008] Figure 1B A perspective schematic diagram of an example GAAFET device according to some embodiments is shown;

[0009] Figure 2A A cross-sectional schematic diagram of an example FinFET device according to some embodiments along a first horizontal direction is shown;

[0010] Figure 2B Shown according to some embodimentsFigure 2A Perspective schematic diagram of the exemplary fin structure shown;

[0011] Figure 3A Cross-sectional schematic diagram of another example of a FinFET device along a first horizontal direction according to some embodiments;

[0012] Figure 3B Illustrates according to some embodiments Figure 3A Perspective schematic diagram of the exemplary fin structure shown;

[0013] Figure 4A Cross-sectional schematic diagram of yet another example of a FinFET device along a first horizontal direction according to some embodiments;

[0014] Figure 4B Illustrates according to some embodiments Figure 4A Perspective schematic diagram of the exemplary fin structure shown;

[0015] Figure 5A Cross-sectional schematic diagram of still another example of a FinFET device along a first horizontal direction according to some embodiments;

[0016] Figure 5B Illustrates according to some embodiments Figure 5A Perspective schematic diagram of the exemplary fin structure shown;

[0017] Figure 6A Cross-sectional schematic diagram of yet another example of a FinFET device along a first horizontal direction according to some embodiments;

[0018] Figure 6B Illustrates according to some embodiments Figure 6A Perspective schematic diagram of the exemplary fin structure shown;

[0019] Figure 7 Illustrates according to some embodiments Figure 4A Exemplary schematic diagram of the energy band diagram of a FinFET device;

[0020] Figure 8 Flowchart of an exemplary method for manufacturing a semiconductor device according to some embodiments;

[0021] Figures 9A to 9E Illustrates according to some embodiments the use of Figure 8 Perspective schematic diagram of an exemplary semiconductor device at various stages manufactured using the method shown;

[0022] Figure 9F Illustrates according to some embodiments the use of Figure 8Cross-sectional schematic view of an exemplary semiconductor device in one of the stages and along a first horizontal direction manufactured by the method shown; and

[0023] Figures 9G to 9H Illustrates the use according to some embodiments Figure 8 Cross-sectional schematic views of exemplary semiconductor devices in various stages and along a second horizontal direction manufactured by the method shown.

[0024]

Symbol Explanation

[0025] 100: FinFET device

[0026] 100A: FinFET device

[0027] 100B: GAAFET device

[0028] 101: Substrate

[0029] 102: Fin structure

[0030] 102a, 102b, 102c: Fin structures

[0031] 103: Segmented channel region / channel region

[0032] 104, 106: Source / drain region / S / D region

[0033] 110: Gate structure

[0034] 112: Gate electrode layer

[0035] 114: Gate dielectric layer

[0036] 116: Gate spacer

[0037] 118: Hard mask layer

[0038] 192: Linear channel / one-dimensional linear channel / 1D linear channel

[0039] 200, 300, 400, 500, 600: FinFET devices

[0040] 202: First channel segment / channel segment

[0041] 204: Second channel segment / channel segment

[0042] 302: First channel segment / channel segment

[0043] 304: Second channel segment / channel segment

[0044] 306: Third channel segment / channel segment

[0045] 400a, 400b, 400c: FinFET Devices

[0046] 402: First Channel Segment / Channel Segment

[0047] 404: Second Channel Segment / Channel Segment

[0048] 406: Third Channel Segment / Channel Segment

[0049] 408: Fourth Channel Segment / Channel Segment

[0050] 410: Fifth Channel Segment / Channel Segment

[0051] 502: First Channel Segment / Channel Segment

[0052] 504: Second Channel Segment / Channel Segment

[0053] 506: Third Channel Segment / Channel Segment

[0054] 508: Fourth Channel Segment / Channel Segment

[0055] 510: Fifth Channel Segment / Channel Segment

[0056] 602: First Channel Segment

[0057] 604: Second Channel Segment

[0058] 606: Third Channel Segment

[0059] 608: Fourth Channel Segment

[0060] 700: Energy Band Diagram

[0061] 800: Method

[0062] 802, 804, 806, 808: Steps

[0063] 900: Semiconductor Device

[0064] 902: Mandrel Layer

[0065] 903: Continuous Channel Region

[0066] 904, 906: Trenches

[0067] 912, 914, 916, 918, 920: Continuous Channel Segment / Channel Segment

[0068] 922, 924: S / D Regions

[0069] 930: Continuous Gate Structure

[0070] 932: Continuous Gate Metal Layer

[0071] 934: Continuous gate dielectric

[0072] L, L1: Length

[0073] W: Width

[0074] X, Y, Z: Directions

[0075] X-X’, Y-Y’: Lines Detailed implementation

[0076] The following disclosure provides many different embodiments or examples for implementing different features of this disclosure. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these specific examples are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, this disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0077] In addition, for ease of description, spatially relative terms (such as “underlying,” “below,” “bottom,” “overlying,” “upper,” and the like) may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. In addition to the orientation depicted in the figures, spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and thus the spatially relative descriptive terms used herein may be interpreted accordingly.

[0078] In addition, the source / drain region (or S / D region) may refer to the source or the drain individually or collectively depending on the context. For example, a device may include a first source / drain region and a second source / drain region as well as other components. The first source / drain region may be a source region, and the second source / drain region may be a drain region, or vice versa. Those of ordinary skill in the art can understand various variations, modifications, and alternatives of the embodiments of this disclosure.

[0079] This disclosure describes some embodiments. Additional steps may be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the described stages may be replaced or deleted. Some of the features described below may be replaced or deleted, and additional features may be added for different embodiments. Although some embodiments are discussed in terms of steps performed in a specific order, these operations may be performed in another logical order.

[0080] Overview

[0081] In a FinFET, the source region and the drain region are heavily doped. The source region and the drain region each have a first semiconductor type (e.g., n-type for NMOS and p-type for PMOS). One problem with a bulk FinFET is that leakage current occurs through the channel region along the path between the source and the drain. The leakage current through the channel region in the fin between the source and the drain is also referred to as punch-through leakage.

[0082] Punch-through leakage typically occurs when a small and unexpected current flows through the channel region between the source region and the drain region, even when the FinFET device is in the "OFF" state. Such leakage current may have some negative consequences, such as increased power consumption, reduced efficiency, and degraded performance. Punch-through leakage in a FinFET device may also cause standby power consumption in digital circuits or signal attenuation and reduced voltage tolerance in analog circuits.

[0083] The present disclosure provides a technique for solving the above punch-through leakage problem. An insight provided in the present disclosure relates to a novel FinFET device having a segmented channel region with a channel blocking material. According to some embodiments, the FinFET device includes a fin structure and a segmented channel region formed in the fin structure. The segmented channel region includes a plurality of channel segments, and at least one channel segment includes a channel blocking material configured to increase the energy barrier of the channel segment.

[0084] A FinFET device having a segmented channel region with a channel blocking material can provide at least the following advantages. First, by employing a channel blocking material (e.g., an epitaxial layer or a dopant having a higher work function than the base material of the channel) in a specific channel segment of the channel region, the height of the energy barrier at the interface between the specific channel segment and other channel segments and / or at the interface between the specific channel segment and the source / drain (S / D) region can be effectively increased. This increase in the energy barrier can effectively prevent or reduce punch-through leakage that may occur when the FinFET device is in the "OFF" state (i.e., when the FinFET device is not activated or when the voltage across the FinFET device is lower than the threshold voltage (Vt) without the channel blocking material). As a result, the ON / OFF control and power efficiency of the FinFET device can be improved. In particular, punch-through leakage can be improved in applications of the FinFET device at or near absolute zero.

[0085] Additionally, by selectively introducing a channel-blocking material into a small segment of the channel region, control over the conductive characteristics of the FinFET device can be achieved. The carrier concentration and mobility in a specific portion of the channel region can be adjusted to optimize the performance, threshold voltage, and other electrical characteristics of the FinFET device.

[0086] Furthermore, selectively including a channel-blocking material in a segment of the channel region allows for greater design flexibility, and the optimization of the FinFET device provides tailored channel characteristics to meet specific performance requirements and address issues arising from device scaling. As one example, during the same manufacturing process, multiple FinFET devices with segmented channel regions having channel-blocking materials can be formed in a given area, thereby resulting in a higher device integration density and improvements in overall wafer functionality and packaging density.

[0087] Further, the segmented channel region described in this disclosure can be widely applied to other types of field-effect transistor devices besides FinFETs, including but not limited to planar transistor devices, silicon-on-insulator (SOI) devices, GAAFETs, high-voltage (HD) devices, complementary metal-oxide-semiconductor (CMOS), diffused MOS (DMOS) devices, bipolar-CMOS-DMOS (BCD) devices, and the like.

[0088] Exemplary FinFET device having a segmented channel region

[0089] Figure 1AA perspective schematic diagram of an exemplary FinFET device 100A is shown. In the example shown, the FinFET device 100A includes, among other components, a fin structure 102 and a gate structure 110. The fin structure 102 extends in a first horizontal direction (i.e., the X direction), and includes two source / drain regions (S / D regions described later) 104 and 106, and a segmented channel region 103 that extends in the first horizontal direction, and the segmented channel region 103 is located between the two S / D regions 104 and 106 and connects the two S / D regions 104 and 106. The gate structure 110 extends in a second horizontal direction (i.e., the Y direction), and is disposed on the segmented channel region 103 and surrounds the segmented channel region 103. The two S / D regions 104 and 106 are formed on the extending portions of the fin structure 102 located on opposite sides of the gate structure 110 along the first horizontal direction. The effective channel length of the FinFET device 100 is determined by the length L of the gate structure 110 along the first horizontal direction. It should be noted that a plurality of FinFET devices 100A can be arranged, for example, in an array pattern of rows, columns, or rows and columns, in the active region (or device region) on a substrate (not shown).

[0090] Figure 1B A perspective schematic diagram of an exemplary GAAFET device 100B is shown. In the example shown, the GAAFET device 100B includes, among other components, a plurality of one-dimensional (1D) linear channels 192 (also referred to as "nanosheet channels") and a gate structure 110. Similar to the Figure 1A FinFET device 100A shown, the 1D linear channels 192 of the GAAFET device 100B can include two S / D regions 104 and 106 formed in the extending portions of the linear channels 192 on opposite sides of the gate structure 110. The 1D linear channels 192 can also include a segmented channel region (not shown), and the segmented channel region extends between the two S / D regions 104 and 106 in the first horizontal direction and connects the two S / D regions 104 and 106, and is surrounded by the gate structure 110.

[0091] It should be noted that Figure 1A and Figure 1B the FinFET device 100A and the GAAFET device 100B shown are only for illustrative purposes of the embodiments of the present disclosure and are not intended to limit the present disclosure. Also, various other microstructures or nanostructure FET devices that can apply the segmented channel region 103 are also within the scope of the present disclosure, such as nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon transistors, dyed channel transistors, etc.

[0092] FinFET and GAAFET devices offer several advantages over traditional Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) devices (also known as planar devices). These advantages can include better wafer area efficiency, improved carrier mobility, and improved compatibility with the manufacturing processes of planar devices. Therefore, it can be desirable to design an IC wafer using FinFET or GAAFET devices for part or all of the integrated circuit (IC) wafer.

[0093] However, some FinFET and GAAFET devices may have a uniform channel profile and may thus suffer from the punch-through leakage as described above. Accordingly, various embodiments of the present disclosure provide FinFET devices or GAAFET devices with a segmented channel region or a heterogeneous channel structure to have reduced or minimized punch-through leakage. Figures 2A to 6B Various examples of FinFET devices with a segmented channel region are illustrated. For clarity, Figure 1A a three-dimensional axis X, Y, and Z is illustrated, and the X, Y, and Z axes are aligned with Figures 2A to 6B each of the axes in, and the X, Y, and Z axes may also be referred to as the X, Y, and Z directions.

[0094] Figures 2A to 2B An exemplary FinFET device 200 is illustrated. Figure 2A FIG. is a cross-sectional schematic view of the FinFET device 200 along a first horizontal direction. Figure 2B FIG. is Figure 2A a perspective view of the fin structure 102 of the FinFET device 200 shown in FIG. In the illustrated example, the FinFET device 200 includes a substrate 101, a fin structure 102, and a gate structure 110. The substrate 101 may be a silicon substrate. Alternatively, the substrate 101 may include another elemental semiconductor, such as germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. In some embodiments, the substrate 101 is a semiconductor-on-insulation (SOI).

[0095] As described above, the fin structure 102 extends along a first horizontal direction and includes two S / D regions 104 and 106 respectively located at two ends of the fin structure 102, and includes a segmented channel region 103 disposed between the fin structures 102 and connecting the two S / D regions 104 and 106. A gate structure 110 is disposed on the segmented channel region 103 and surrounds the segmented channel region 103 (i.e., covers the top surface and sidewalls of the segmented channel region 103). The gate structure 110 includes a gate electrode layer 112, a gate dielectric layer 114, two gate spacers 116, and a hard mask layer 118.

[0096] The gate dielectric layer 114 is formed on the segmented channel region 103 of the fin structure 102 and surrounds the segmented channel region 103 of the fin structure 102, and the gate electrode layer 112 is formed on the gate dielectric layer 114. The gate dielectric layer 114 and the gate electrode layer 112 can be formed using deposition processes known in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), combinations thereof, or other suitable processes. In some embodiments, the gate dielectric layer 114 includes a hafnium oxide (HfO2) material and has a thickness (measured along the Z direction) between about 1 nm and about 5 nm. In some embodiments, the gate electrode layer 112 includes a titanium nitride (TiN) material and has a thickness (measured along the Z direction) between about 1 nm and about 50 nm.

[0097] The gate spacers 116 are formed around the long sides of the gate structure 110. In other words, the gate spacers 116 extend along the Y direction in an extended growth manner. The gate spacers 116 are formed by depositing spacer material over the gate structure 110 and then performing patterning and etching processes on the spacer material. The gate spacers 116 can include a dielectric material. In some embodiments, the gate spacers 116 include silicon oxide or silicon nitride. Each gate spacer 116 has a width of about 1 nm to about 20 nm in the X direction. The hard mask layer 118 is configured to pattern the gate structure 110, for example, by etching. In some embodiments, the hard mask layer 118 is made of a dielectric material such as silicon oxide.

[0098] The channel length L of the segmented channel region 103 can be substantially the same as the length L of the gate structure 110 along the first horizontal direction. In some embodiments, the channel length L is about 5 nm to about 50 nm in the first horizontal direction. In some embodiments, the channel length L is 5 nm to 45 nm, 5 nm to 35 nm, 5 nm to 25 nm, 5 nm to 15 nm, or 5 nm to 15 nm. Additionally, as Figure 2BAs shown, in a second horizontal direction (e.g., the Y direction) perpendicular to the first horizontal direction, the fin structure 102 has a width W.

[0099] The segmented channel region 103 may include a substrate semiconductor material (e.g., Si, Ge, SiGe) or a group III-V compound semiconductor material (e.g., gallium arsenide (GaAs) and indium phosphide (InP)). In one embodiment, the segmented channel region 103 includes Si as the substrate semiconductor material.

[0100] The segmented channel region 103 also includes a plurality of channel segments, and the channel segments include a first channel segment 202 and a second channel segment 204. The channel segments used in this disclosure are also referred to as "channel sub-regions", and "channel segments" and "channel sub-regions" can be used interchangeably. The channel segments 202 and 204 may be arranged in the first horizontal direction. In the example shown, the channel segments 202 and 204 are adjacent to each other. However, the channel segments 202 and 204 may also be separated from each other along the first horizontal direction. In the example shown, the channel segments 202 and 204 are respectively connected to two S / D regions 104 and 106. However, in an alternative embodiment, the channel segments 202 / 204 may be spaced apart from the S / D regions 104 / 106 by providing another channel segment between the channel segments 202 / 204.

[0101] The channel segments 202 and 204 have different material compositions. In some embodiments, the channel segments 202 and 204 include different dopants (e.g., different doping elements or dopants of different semiconductor types). In some embodiments, the channel segments 202 and 204 have different doping concentrations. In some embodiments, the channel segments 202 and 204 include different materials (e.g., epitaxial layers). In some embodiments, the channel segments 202 and 204 include the same material, but have different crystal structures or crystal orientations of the lattice (e.g., crystal orientations 110 or 111). Therefore, the segmented channel region 103 is essentially heterogeneous. That is to say, the FinFET device 200 has a heterogeneous channel structure.

[0102] In some embodiments, at least one of channel segments 202 and 204 includes a channel blocking material for increasing the blocking characteristics of channel region 103. The term "channel blocking material" as used in this disclosure refers to any dopant or material introduced into channel region 103 to change the electrical properties of the channel region, enhance the blocking effect, increase the threshold voltage (Vt) of the FinFET device, and reduce the punch-through leakage effect of the FinFET device. Channel blocking materials include, for example, but are not limited to, blocking dopants such as boron (B), indium (In), gallium (Ga), phosphorus (P), arsenic (As), antimony (Sb); alloy materials such as silicon germanium (SiGe), silicon germanium carbon (SiGeC), indium gallium arsenide (InGaAs); dielectric materials such as silicon dioxide (SiO2), hafnium dioxide (HfO2), or aluminum oxide (Al2O3); metal compound materials such as tantalum nitride (TaN), titanium nitride (TiN), or hafnium silicate (HfSiO); and other suitable materials. Depending on the semiconductor type of the FinFET (e.g., n-type or p-type), additional examples of channel blocking materials include Ga2O3, TiO2, InP, GaAs, GaP, CdSe, TaON, WO3, ZrO2, ZnS, SiC, SrTiO3, etc.

[0103] It should be noted that although some dopants such as B, In, Ga, P, As, and Sb are also commonly used in general channel regions to increase the carrier flow in the channel, when dopants are introduced in a segment (e.g., channel segment 202) or local region of the channel region, these dopant configurations with significantly higher doping concentrations are used as channel blockers to change the electrical characteristics of the channel segment and the entire channel region and enhance the blocking effect. In other words, the concentration profile of a specific dopant can vary in the first horizontal direction across the channel region.

[0104] In some embodiments, the channel blocking material is in the form of a dopant (i.e., a channel blocking dopant). The channel blocking dopant has the same semiconductor type (e.g., p-type or n-type) as source / drain regions 104 and 106. In some embodiments, the channel blocking dopant has a semiconductor type opposite to that of source / drain regions 104 and 106. In some embodiments, the channel blocking dopant is the same as the dopant in the source / drain regions.

[0105] In some embodiments, the channel region has a base semiconductor material of Si, and the channel blocking material in a specific channel segment (e.g., the first channel segment 202 or the second channel segment 204) is SiGe, where the weight percentage concentration of Ge in the specific channel segment is at least 5%. In some embodiments, the channel blocking material is an epitaxially grown SiGe layer of the specific channel segment. In some embodiments, Ge is a channel blocking dopant distributed or dispersed in the specific channel segment, and the weight percentage concentration of Ge in the specific channel segment is 5%. In some embodiments, the weight percentage concentration of Ge in the specific channel segment is 5% to 40%.

[0106] In some embodiments, the channel blocking material has a work function of at least 0.1 electron volts (eV) compared to the base material of the channel (e.g., Si). In some embodiments, the work function of the channel blocking material is at least 0.1 eV, at least 0.2 eV, at least 0.3 eV, at least 0.4 eV, or at least 0.5 eV higher than the work function of the base material of the channel (e.g., Si). In some embodiments, the work function of the channel blocking material is 0.1 eV to 1.0 eV, 0.1 eV to 0.8 eV, 0.1 eV to 0.6 eV, 0.1 eV to 0.4 eV, or 0.1 eV to 0.2 eV higher than the work function of the base material of the channel.

[0107] In some embodiments, the channel blocking material can be introduced into at least one channel segment (e.g., the channel segment 202) by an epitaxial growth process, and the channel segment 202 can be composed of the channel blocking material. In an alternative embodiment, the channel blocking dopant can be introduced into at least one channel segment (e.g., the channel segment 202) by an ion implantation process, and the channel segment 202 includes the channel blocking material as the channel blocking dopant, and the channel blocking dopant is distributed or dispersed in the channel base material (e.g., silicon).

[0108] Although both epitaxial growth and implantation can be used to introduce the channel blocking material into a specific channel segment, epitaxial growth and implantation have their respective advantages. As an example, epitaxial growth better controls doping and achieves a more uniform doping distribution. In the epitaxial growth process, the channel blocking material is deposited layer by layer, forming a well-defined doping concentration. Since the deposited material is similar to the crystal structure of the substrate, epitaxial growth can also minimize crystal damage in the channel segment. Therefore, at least in part due to the crystal quality and the interface between the epitaxial layer and the substrate usually having higher quality, the epitaxially grown channel blocking material introduced into the channel segment can improve the electrical characteristics. Epitaxial growth can also achieve precise control of the doping concentration and depth of the channel blocking material.

[0109] In comparison, implantation, which introduces dopants through ion bombardment, may result in non-uniform doping and possible damage to the lattice of the doped region. However, precise control of the dopant distribution can be achieved by adjusting the implantation energy and dose. Therefore, implantation offers greater flexibility in adjusting the doping profile and doping concentration.

[0110] In some embodiments, the lengths L1 of the first channel segment 202 and the second channel segment 204 can be about 1 nm to 50 nm, 1 nm to 45 nm, 1 nm to 35 nm, 1 nm to 35 nm, 25 nm, 1 nm to 20 nm, 1 nm to 15 nm, 1 nm to 10 nm, 1 nm to 5 nm, or 1 nm to 3 nm, respectively. In some embodiments, the percentage of the channel segment length L1 in the channel length L of the entire channel region 103 is 1% to 99%, 1% to 90%, 1% to 75%, 1% to 50%, 1% to 40%, 1% to 30%, 1% to 20%, 1% to 10%, or 1% to 5%. In some embodiments, the total length of the channel region 103 including the channel blocking material is about 1 nm to 50 nm, 1 nm to 45 nm, 1 nm to 35 nm, 1 nm to 25 nm, 1 nm to 20 nm, 1 nm to 15 nm, 1 nm to 10 nm, 1 nm to 5 nm, or 1 nm to 3 nm. In some embodiments, the percentage of the total length of the channel region including the channel blocking material in the channel length L of the entire channel region 103 is 1% to 99%, 1% to 90%, 1% to 75%, 1% to 50%, 1% to 40%, 1% to 30%, 1% to 20%, 1% to 10%, or 1% to 5%.

[0111] In some embodiments, the first channel segment 202 includes the channel blocking material, while the second channel segment 204 does not contain or substantially does not contain the channel blocking material. For example, the first channel segment 202 can be an epitaxial layer composed of SiO2 as the channel blocking material, while the second channel segment 204 can be substantially free of SiO2.

[0112] In some embodiments, when the FinFET device is not activated, the first channel segment 202 has an energy barrier height of at least 0.1 electron volts (eV) in the carrier flow path between the two S / D regions 104 and 106. The term "energy barrier height" as used in this disclosure refers to the energy difference between two adjacent / adjacent channel interfaces in the FinFET device, or the energy difference between one of the two S / D regions in the FinFET device and its adjacent / adjacent channel segment to which it is connected. The energy barrier height generally represents the energy barrier that carriers (electrons or holes) must overcome to move from one channel segment in the channel region to another, or from the S / D region to an adjacent channel segment. In some embodiments, the first channel segment 202 has an energy barrier height of at least 0.1 eV, at least 0.2 eV, at least 0.3 eV, at least 0.4 eV, or at least 0.5 eV. In some embodiments, the first channel segment 202 has an energy barrier height of 0.1 eV to 1.0 eV, 0.2 eV to 0.8 eV, or 0.3 eV to 0.6 eV.

[0113] In some embodiments, the segmented channel region 103 includes Si as the base semiconductor material, the first channel segment 202 includes a channel blocking material, and the second channel segment 204 does not contain or substantially does not contain a channel blocking material. For example, the first channel segment 202 can be an epitaxial layer composed of SiGe as the channel blocking material, while the second channel segment 204 can be substantially free of SiGe. In some embodiments, the Ge content in the SiGe contained in the first channel segment 202 is 5% to 40%. Without wishing to be bound by any particular theory, it is believed that the lattice of GeSi can establish an energy barrier in the carrier flow path in the channel region, change the carrier concentration and mobility in the channel region, and thereby reduce or prevent tunneling leakage.

[0114] In some embodiments, both the first channel segment 202 and the second channel segment 204 include a channel blocking material. In some embodiments, the first channel segment 202 and the second channel segment 204 include different channel blocking materials. The first channel segment 202 has a first doping concentration of the channel blocking material / dopant, the second channel segment 204 has a second doping concentration of the channel blocking material / dopant, and the first doping concentration is at least one order of magnitude (i.e., 10 times) higher than the second doping concentration. In some embodiments, the first doping concentration is 2 to 20 orders of magnitude (i.e., 10 2 to 10 20 times) higher than the second doping concentration. In some embodiments, the doping concentration of the channel blocking material / dopant in the channel segments 202 and 204 is 10 2 to 10 20 atoms / cm 3 、10 10 to 10 20atoms / cm 3 、 10 15 to 10 20 atoms / cm 3 or 10 18 to 10 20 atoms / cm 3 。

[0115] In some embodiments, the first channel segment 202 has a first energy barrier height, the second channel segment 204 has a second energy barrier height, and the first energy barrier height is at least 0.1 eV, at least 0.2 eV, or at least 0.3 eV higher than the second energy barrier height. In some embodiments, the first energy barrier height is 0.1 eV to 1.0 eV, 0.2 eV to 0.8 eV, or 0.3 eV to 0.6 eV higher than the second energy barrier height. In some embodiments, the first energy barrier height is at least twice as high as the second energy barrier height. In some embodiments, the first energy barrier height is 1 to 5 times higher than the second energy barrier height.

[0116] Figures 3A to 3B Illustrates one example of the FinFET device 300. Figure 3A The figure illustrates a cross-sectional schematic view of the FinFET device 300 along a first horizontal direction. Figure 3B Illustrates Figure 3A A perspective schematic view of the fin structure 102 of the FinFET device 300 shown. The FinFET device 300 is a similar variant of the FinFET device 200. Therefore, unless otherwise stated, similar components such as the substrate 101, the fin structure 102, and the gate structure 110 will not be repeated here.

[0117] In the example shown, the fin structure 102 includes a segmented channel region 103. The segmented channel region 103 includes at least three channel segments (i.e., the first channel segment 302, the second channel segment 304, and the third channel segment 306), and the at least three channel segments are arranged in sequence along the first horizontal direction. At least one of the channel segments 302, 304, and 306 includes a channel blocking material / dopant.

[0118] In some embodiments, the channel region 103 comprises Si as the base semiconductor material, and the second channel segment 304 is doped with a channel blocking material / dopant. In some embodiments, the channel blocking material / dopant comprises at least one of SiO2, SiGe, Ga2O3, TiO2, InP, GaAs, GaP, CdSe, TaON, WO3, ZrO2, ZnS, SiC, SrTiO3, TaN, TiN, HfO2, SiGeC, InGaAs, or a combination thereof. In some embodiments, the work function of the channel blocking material / dopant is 0.1 eV to 1.0 eV higher than the work function of Si. In some embodiments, the second channel segment 304 has an energy barrier height of 0.1 eV to 1.0 eV. In some embodiments, the channel blocking dopant in the second channel segment 304 has a doping concentration of 10 2 to 10 20 atoms / cm3. In some embodiments, the first channel segment 302 and the third channel segment 306 substantially do not include the channel blocking material included in the second channel segment 304.

[0119] In some embodiments, the lengths Ll of the first channel segment 302, the second channel segment 304, and the third channel segment 306 can each be about 1 nm to 50 nm, 1 nm to 45 nm, 1 nm to 35 nm, 1 nm to 25 nm, 1 nm to 20 nm, 1 nm to 15 nm, 1 nm to 10 nm, 1 nm to 5 nm, or 1 nm to 3 nm. In some embodiments, the total length of the channel region including the channel blocking material is about 1 nm to 50 nm, 1 nm to 45 nm, 1 nm to 35 nm, 1 nm to 25 nm, 1 nm to 20 nm, 1 nm to 15 nm, 1 nm to 10 nm, 1 nm to 5 nm, or 1 nm to 3 nm.

[0120] In some embodiments, the second channel segment 304 comprises a first channel blocking material, the first channel segment 302 and the third channel segment 306 comprise a second channel blocking material, and the first channel blocking material is different from the second channel blocking material. In some embodiments, the first channel segment 302, the second channel segment 304, and the third channel segment 306 comprise the same channel blocking material, the second channel segment 304 has a first doping concentration, the first channel segment 302 and the third channel segment 306 have a second doping concentration, and the first doping concentration is at least one order of magnitude, at least 2 orders of magnitude, at least 5 orders of magnitude, at least 10 orders of magnitude, or at least 20 orders of magnitude higher than the second doping concentration.

[0121] In some embodiments, the second channel segment 304 has a first energy barrier height, the first channel segment 302 and the third channel segment 306 have a second energy barrier height, and the first energy barrier height is at least 1 time, at least 2 times, or at least 3 times higher than the second energy barrier height.

[0122] Figures 4A to 4B Illustrates one example of the FinFET device 400. Figure 4A Illustrates a cross-sectional schematic view of the FinFET device 400 along a first horizontal direction. Figure 4B Illustrates Figure 4A A perspective view of the fin structure 102 of the illustrated FinFET device 400. The FinFET device 400 is a similar variant of the FinFET devices 100 and 200, and thus, unless otherwise specified, similar components such as the substrate 101, the fin structure 102, and the gate structure 110 will not be repeated here.

[0123] In the illustrated example, the fin structure 102 includes a segmented channel region 103. The segmented channel region 103 includes at least five channel segments (i.e., a first channel segment 402, a second channel segment 404, a third channel segment 406, a fourth channel segment 408, and a fifth channel segment 410), and the at least five channel segments are arranged in sequence in the first horizontal direction. The second channel segment 404 and the fourth channel segment 408 are spaced apart by the third channel segment 406. At least one of the channel segments 402, 404, 406, 408, and 410 includes a channel blocking material / dopant.

[0124] In some embodiments, the channel region 103 includes Si as a base semiconductor material, and the second channel segment 404 and the fourth channel segment 408 are doped with a channel blocking material / dopant. In some embodiments, the second channel segment 404 and the fourth channel segment 408 include the same channel blocking material / dopant. In some embodiments, the channel blocking material / dopant includes at least one of SiO2, SiGe, Ga2O3, TiO2, InP, GaAs, GaP, CdSe, TaON, WO3, ZrO2, ZnS, SiC, SrTiO3, TaN, TiN, HfO2, SiGeC, InGaAs, or a combination thereof. In some embodiments, the work function of the channel blocking material / dopant is 0.1 eV to 1.0 eV higher than the work function of Si. In some embodiments, the second channel segment 404 and the fourth channel segment 408 have an energy barrier height of 0.1 eV to 1.0 eV. In some embodiments, the channel blocking dopants of the second channel segment 404 and the fourth channel segment 408 have 10 2 to 10 20 atoms / cm 3 doping concentration. In some embodiments, the first channel segment 402, the third channel segment 406, and the fifth channel segment 410 substantially do not include the channel blocking material included in the second channel segment 404 and the fourth channel segment 408.

[0125] In some embodiments, the lengths L1 of the channel segments 402, 404, 406, 408, and 410 may each be about 1 nm to 50 nm, 1 nm to 45 nm, 1 nm to 35 nm, 1 nm to 25 nm, 1 nm to 20 nm, 1 nm to 15 nm, 1 nm to 10 nm, 1 nm to 5 nm, or 1 nm to 3 nm. In some embodiments, the total length of the channel region including the channel blocking material is about 1 nm to 50 nm, 1 nm to 45 nm, 1 nm to 35 nm, 1 nm to 25 nm, 1 nm to 20 nm, 1 nm to 15 nm, 1 nm to 10 nm, 1 nm to 5 nm, or 1 nm to 3 nm.

[0126] In some embodiments, the second channel segment 404 and the fourth channel segment 408 each include a first channel blocking material, the first channel segment 402, the third channel segment 406, and the fifth channel segment 410 each include a second channel blocking material, and the first channel blocking material is different from the second channel blocking material. In some embodiments, the first channel segment 402, the second channel segment 404, and the third channel segment 408 include the same channel blocking material, the second channel segment 404 and the fourth channel segment 408 have a first doping concentration, the first channel segment 402, the third channel segment 406, and the fifth channel segment 410 have a second doping concentration, and the first doping concentration is at least one order of magnitude, at least 2 orders of magnitude, at least 5 orders of magnitude, at least 10 orders of magnitude, or at least 20 orders of magnitude higher than the second doping concentration.

[0127] In some embodiments, the first channel segment 402, the third channel segment 406, and the fifth channel segment 410 include a third channel blocking material, and the third channel blocking material is different from the first channel blocking material and the second channel blocking material. In some embodiments, the first channel segment 402, the third channel segment 406, and the fifth channel segment 410 include the channel blocking dopant of the second channel segment 404 and / or the fourth channel segment 408, the first channel segment 402, the third channel segment 406, and the fifth channel segment 402 are channel blocking dopants of a third doping concentration, and the third doping concentration is different from the first doping concentration and the second doping concentration.

[0128] In some embodiments, the second channel segment 404 and the fourth channel segment 408 have a first energy barrier height, the first channel segment 402, the third channel segment 406, and the fifth channel segment 410 have a second energy barrier height, and the first energy barrier height is at least 1 time, at least 2 times, or at least 3 times higher than the second energy barrier height. In some embodiments, the first channel segment 402, the third channel segment 406, and the fifth channel segment 410 each have a third energy barrier height, and the first energy barrier height is at least 1 time, at least 2 times, or at least 3 times higher than the third energy barrier height. In some embodiments, the second energy barrier height is at least 1 time, at least 2 times, or at least 3 times higher than the third energy barrier height.

[0129] Figures 5A to 5B Illustrates one example of the FinFET device 500. Figure 5A Illustrates a cross-sectional schematic view of the FinFET device 500 along a first horizontal direction. Figure 5B Illustrates Figure 5A A perspective view of the fin structure 102 of the illustrated FinFET device 500. The FinFET device 500 is a similar variant of the FinFET device 400.

[0130] In the illustrated example, the fin structure 102 includes a segmented channel region 103. The segmented channel region 103 includes at least five channel segments (i.e., a first channel segment 502, a second channel segment 504, a third channel segment 506, a fourth channel segment 508, and a fifth channel segment 510), and the at least five channel segments are sequentially arranged in a first horizontal direction. The second channel segment 504 and the fourth channel segment 508 are separated by the third channel segment 506.

[0131] In some embodiments, the second channel segment 504 includes a first channel blocking material, the fourth channel segment 508 includes a second channel blocking material, and the first channel blocking material is different from the second channel blocking material. In some embodiments, the second channel segment 504 and the fourth channel segment 508 include the same channel blocking dopant, the second channel segment 504 has a first doping concentration, the fourth channel segment 508 has a second doping concentration, and the first doping concentration is different from the second doping concentration.

[0132] In some embodiments, the second channel segment 504 has a first energy barrier height, the fourth channel segment 508 has a second energy barrier height, and the first energy barrier height is at least 1 order of magnitude, at least 2 orders of magnitude, at least 3 orders of magnitude, at least 4 orders of magnitude, or at least 5 orders of magnitude higher than the second energy barrier height.

[0133] In some embodiments, the first channel segment 502, the third channel segment 506, and the fifth channel segment 510 have a third energy barrier height, and the first energy barrier height is at least 1 time, at least 2 times, or at least 3 times higher than the second energy barrier height.

[0134] Figures 6A to 6B Illustrates one example of the FinFET device 600. Figure 6A Illustrates a cross-sectional schematic view of the FinFET device 600 along the first horizontal direction. Figure 6B Illustrates Figure 6A A perspective view of the fin structure 102 of the illustrated FinFET device 600. The FinFET device 600 is a similar variant of the FinFET device 500.

[0135] In the illustrated example, the fin structure 102 includes a segmented channel region 103. The segmented channel region 103 includes at least four channel segments (i.e., the first channel segment 602, the second channel segment 604, the third channel segment 606, and the fourth channel segment 608), and the at least four channel segments are sequentially arranged in the first horizontal direction. The second channel segment 604 and the third channel segment 606 are directly connected and spaced apart from the S / D regions 104 and 106.

[0136] In some embodiments, the second channel segment 604 includes a first channel blocking material, the third channel segment 606 includes a second channel blocking material, and the first channel blocking material is different from the second channel blocking material. In some embodiments, the second channel segment 604 and the third channel segment 606 include the same channel blocking dopant, the second channel segment 604 has a first doping concentration, the third channel segment 606 has a second doping concentration, and the first doping concentration is different from the second doping concentration.

[0137] In some embodiments, the second channel segment 604 has a first energy barrier height, the third channel segment 606 has a second energy barrier height, and the first energy barrier height is at least 1 order of magnitude, at least 2 orders of magnitude, at least 3 orders of magnitude, at least 4 orders of magnitude, or at least 5 orders of magnitude higher than the second energy barrier height.

[0138] In some embodiments, the first channel segment 602 and the fourth channel segment 608 have a third energy barrier height, and the first energy barrier height is at least 1 time, at least 2 times, or at least 3 times higher than the second energy barrier height.

[0139] It should be noted that the foregoing Figures 2A to 6BThe described examples are intended to be illustrative only, and other variations and modifications of the segmented channel region 103 are also within the scope of the present disclosure. For example, the segmented channel region 103 may include more than 5 channel segments, and may also include more than 3 different channel-blocking materials or more than 3 different doping concentrations of channel-blocking dopants. In other embodiments, the location and arrangement of the channel segments including the channel-blocking materials in the segmented channel region 103 may also vary.

[0140] It is understandable that although the above Figures 2A to 6B Only a single FinFET device is shown, and multiple similar FinFET devices can be arranged on a single wafer or on the same chip. For example, a complementary metal oxide semiconductor (CMOS) device includes both an n-FET device and a p-FET device. Both the n-FET device and the p-FET device can be manufactured using the process described below. In one embodiment, the work function of the gate of the n-FET device is closer to the conduction band edge of the FinFET device, and the work function of the gate of the p-FET device is closer to the valence band edge of the FinFET device.

[0141] Figure 7 An exemplary schematic diagram of an energy band diagram 700 of a FinFET device 400 according to some embodiments is depicted. In the illustrated example, due to punch-through leakage, when the FinFET device is in the “off” state (i.e., when the FinFET device 400 is not started to operate, or when the voltage across the FinFET device 400 is lower than the threshold voltage (Vt) without the channel blocking material), carriers (electrons or holes) may also flow from one of the S / D regions 104 / 106 to the other of the S / D regions 106 / 104 through the segmented channel region 103. However, since both the second channel region 404 and the fourth channel region 408 include channel blocking materials / dopants, two energy barriers are generated along the carrier flow path in the second channel region 404 and the fourth channel region 408, respectively. Due to the two energy barriers, the punch-through leakage can be significantly reduced or minimized in the “off” state of the FinFET device 400. It should be noted that the corresponding to the FinFET device 400 Figure 7 The energy band profiles of are intended to be illustrative only, and other energy band profiles corresponding to other exemplary FinFET devices within the scope of the present disclosure are possible.

[0142] Exemplary Manufacturing Flowchart

[0143] Figure 8 A flow chart of an exemplary method 800 for fabricating a semiconductor device 900 is depicted in accordance with some embodiments. Figures 9A to 9F Depicted is the use of some embodimentsFigure 8 Perspective or cross-sectional schematic views of exemplary semiconductor devices 900 at various stages fabricated by the method 800 shown. Figures 9A to 9E Is a perspective view. Figure 9F Is a cross-sectional view along the Figure 9E Line X-X' of. Figures 9G to 9H Is a cross-sectional perspective view along the Figure 9E Line Y-Y' of. It should be noted that variations of the FinFET device (e.g., FinFET devices 100, 200, 300, 400, 500, 600) and other possible variations and modifications can also be fabricated using the method 800 or any of its methods.

[0144] As Figure 8 Shown, the method 800 can include steps 802, 804, 806, and 808. Additional steps can be performed. Additionally, it should be understood that Figure 8 The order of the various steps of

[0145] is only illustrative, and thus, different orders can be used in other embodiments, and these different step orders are also within the scope of the embodiments of the present disclosure.

[0146] In Figure 9A the example shown, a mandrel layer 902 is formed on the substrate 101. The mandrel layer 902 can be formed by depositing a base semiconductor material (e.g., Si) on the substrate 101 using an appropriate deposition technique, where the appropriate deposition technique is, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or spin coating.

[0147] Multiple continuous channel segments can be formed by an epitaxial growth process, an implantation process, or a combination thereof. As one example of the epitaxial growth process, the mandrel layer formed on the substrate is patterned and etched to form at least one trench extending along the first horizontal direction. The number of trenches can vary according to the expected number of continuous channel segments. In some embodiments, one trench is formed. In some embodiments, two or more trenches are formed, and the two or more trenches are spaced apart parallel to each other.

[0148] As an example of a patterning and etching process for forming trenches in a mandrel layer, a hard mask layer is deposited on the top surface of the mandrel layer. The hard mask can include silicon oxide or silicon nitride. Subsequently, a photoresist layer is disposed on the top surface of the hard mask layer. Then, the photoresist layer is exposed through a patterning mask containing the desired pattern. Next, the developed photoresist layer is developed to selectively remove the exposed or unexposed regions of the photoresist layer, depending on whether a positive or negative photoresist is used. Using the developed photoresist as a mask, a selective etching process is performed to transfer the pattern into the hard mask layer. The hard mask material in the regions not protected by the photoresist is removed by etching, and the desired trenches are created according to the desired pattern.

[0149] In Figure 9B the example shown, two trenches 904 and 906 are formed respectively, and the two trenches 904 and 906 extend along the Y direction. The two trenches 904 and 906 are spaced apart from each other in parallel by a portion of the mandrel layer 902 disposed between the two trenches 904 and 906. The two trenches 904 and 906 respectively correspond to two consecutive channel segments to be generated (as Figure 9C shown).

[0150] After forming the trenches 904 and 906, an epitaxial growth process is performed using a suitable deposition technique to form a continuous epitaxial layer or crystal layer in the trenches 904 and 906 formed in the mandrel layer 902. The epitaxial layer or crystal layer formed in the trenches 904 and 906 includes a channel blocking material as described above. Suitable deposition techniques include, for example, CVD, metal-organic CVD (MOCVD), PVD, hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), and molecular beam epitaxy (MBE).

[0151] In Figure 9C the example shown, two continuous epitaxial layers are grown respectively in the trenches 904 and 906 to form continuous channel segments 914 and 918. The continuous channel segments 914 and 918 extend in the Y direction. In some embodiments, the continuous channel segments 914 and 918 include the same channel blocking material (e.g., SiGe, SiO2, etc.). In some embodiments, the epitaxial layers of the continuous channel segments 914 and 918 respectively include two different channel blocking materials (e.g., the continuous epitaxial layer of the continuous channel segment 914 includes SiGe, while the continuous epitaxial layer of the continuous channel segment 918 includes SiO2). The dimensions of the channel segments 914 and 918 in the X direction can be 1 nm to 30 nm respectively.

[0152] Alternatively, multiple consecutive channel segments can be formed by an implantation process to introduce channel-blocking dopants into selected regions of the mandrel layer corresponding to the desired consecutive channel segments, without the need to generate trenches in the mandrel layer. As one example, a patterned mask is disposed on the mandrel layer to expose the desired regions of the mandrel layer (i.e., the regions corresponding to the desired consecutive channel segments). An ion implantation process is performed to introduce the desired channel-blocking dopants into the exposed regions of the mandrel layer. Ions are accelerated and introduced into the exposed regions of the mandrel layer, and the exposed regions of the mandrel layer are doped. The operating parameters of the implantation process (e.g., energy, dose, diffusion temperature, diffusion time, etc.) can be controlled to achieve the desired doping concentration of the channel-blocking dopants. In some embodiments, the implantation doping energy is from 0.7 eV to 54 eV. In some embodiments, the dose of the implantation process is 10 2 to 10 20 atoms / cm 3 . In some embodiments, the diffusion temperature is from -150 °C to 800 °C. In some embodiments, the diffusion time is from 5 seconds to 5 hours. In Figure 9C the example shown, the consecutive channel segments 914 and 918 can be formed by an ion implantation process, and the consecutive channel segments 914 and 918 each include channel-blocking dopants. In some embodiments, two different channel-blocking dopants can be introduced into corresponding regions of the mandrel layer 902, respectively, to form the consecutive channel segments 914 and 918. It should be noted that other doping techniques other than ion implantation can also be used to form the consecutive channel segments 914 and 918.

[0153] Step 804, along the first horizontal direction, form consecutive S / D regions in the mandrel layer. The corresponding regions of the mandrel layer can be re-doped by using an ion implantation process or other suitable doping techniques to form consecutive S / D regions. In some embodiments, an n-type dopant (e.g., As, P, or Sb) is doped into the n-type S / D region of an n-type FinFET, while a p-type dopant (e.g., B or In) is doped into the p-type S / D region. The doping concentration of the consecutive S / D regions can be 10 19 to 10 21 atoms / cm 3 . It should be noted that the S / D regions can be formed before or after the fin structure is formed. The consecutive S / D regions can also be formed before or after the gate structure described later is formed.

[0154] In Figure 9DIn the example shown, two consecutive S / D regions 922 and 924 are formed, and the two consecutive S / D regions 922 and 924 extend continuously along the Y direction. The two consecutive S / D regions 922 and 924 can be formed on opposite sides of consecutive channel segments 914 / 918 along the X direction, such that the consecutive channel segments 914 / 918 are disposed between the two consecutive S / D regions 922 and 924. The two consecutive S / D regions 922 and 924 correspondingly define a consecutive channel region 903 located between the two consecutive S / D regions 922 and 924. In addition, five consecutive channel segments 912, 914, 916, 918, and 920 are sequentially formed in the consecutive channel region 903. The consecutive channel segments 912, 914, 916, 918, and 920 all extend continuously in the Y direction. The consecutive channel segment 914 is disposed between two consecutive channel segments 912 and 916, and the consecutive channel segment 918 is disposed between two consecutive channel segments 916 and 920.

[0155] In some embodiments, an additional ion implantation process can be performed before or after forming the two S / D regions 922 and 924 to introduce one or more channel blocking dopants into one or more of the consecutive channel segments 912, 914, 916, 918, and 920. For example, the consecutive channel segments 912, 916, and 920 can be doped with channel blocking dopants that are the same as or different from the channel blocking materials / dopants included in the consecutive channel segments 914 and / or 918.

[0156] In some embodiments, an ion implantation process is performed to introduce channel blocking dopants into each of the consecutive channel segments 912, 914, 916, 918, and 920. The operating parameters of the ion implantation process can be controlled to have different doping concentrations of the channel blocking dopants across the consecutive channel segments 912, 914, 916, 918, and 920 in the X direction. In some embodiments, one or more patterned masks can be used in the ion implantation process to achieve different doping concentrations, and a doping profile across the entire consecutive channel region 903 can be achieved.

[0157] Step 806, in a second horizontal direction perpendicular to the first horizontal direction, form at least one fin structure on the substrate. In Figures 9D to 9E and Figures 9F to 9G In the example shown, the mandrel layer 902 is patterned and etched to form three fin structures 102a, 102b, and 102c (collectively referred to as fin structures 102). Each fin structure 102 extends along the X direction (perpendicular to the Y direction). In the patterning and etching process, a portion of the mandrel layer 902 located on both sides of the fin structures 102 or between every two adjacent fin structures 102 is removed. The plurality of fin structures 102 are arranged parallel to and aligned with each other along the Y direction. As Figure 9EAs shown, each fin structure 102 includes a segmented channel region 103, and the segmented channel region 103 further includes five channel segments 402, 404, 406, 408, and 410. The channel region 103 of each fin structure 102 corresponds to Figure 9D the continuous channel region 903, and the five channel segments 402, 404, 406, 408, and 410 respectively correspond to Figure 9D the continuous channel segments 912, 914, 916, 918, and 920. A plurality of fin structures 102 can be used to form a single FinFET device, or alternatively, to form separate FinFET devices in subsequent steps. It should be noted that the number of fin structures 102 formed on the substrate 101 can vary according to design requirements.

[0158] Step 808, form a continuous gate structure extending along a first horizontal direction and dispose the gate structure on the channel segments of the fin structures. In some embodiments, a continuous gate dielectric layer is formed on the channel segments, a continuous gate metal layer is formed on the continuous gate dielectric layer, and continuous gate spacers are formed along both sides of the continuous gate metal layer. In Figure 9G the example shown, a continuous gate dielectric layer 934 is formed and disposed on the fin structures 102a, 102b, and 102c, and the continuous gate dielectric layer 934 covers the channel region 103 of each fin structure 102. A continuous gate metal layer 932 is formed and disposed on the continuous gate dielectric layer 934 to form a continuous gate structure 930. In some embodiments, continuous gate spacers (not shown) are further formed along both sides of the continuous gate metal layer 932. Accordingly, FinFET devices 400a, 400b, and 400c (collectively referred to as FinFET devices 400) are formed. It should be noted that the number of FinFET devices 400 can vary according to the number of fin structures 102 formed in step 806. In some embodiments, the semiconductor device 900 can include a plurality of FinFET devices 400. In some embodiments, the plurality of FinFET devices 400 are electrically isolated from each other (i.e., electrically isolated by performing a gate cutting process to cut the continuous gate structure 930), and the plurality of FinFET devices 400 are included in different semiconductor devices in the active region on the substrate 101. One or more shallow trench isolation (STI) structures (not shown) are formed to isolate adjacent FinFET devices formed on the substrate 101 of the semiconductor device 900 (i.e., between two adjacent fin structures 102).

[0159] In some embodiments, the S / D regions of each fin structure may be formed after forming the continuous gate structure. For example, a continuous gate spacer may be formed, and through the continuous gate spacer as a patterning mask, an ion implantation process may be further performed to dope the exposed regions under the patterning mask to form the S / D regions corresponding to each fin structure.

[0160] Various other components may be formed during the fabrication of the aforementioned FinFET device 400 and semiconductor device 900. These components include, but are not limited to, gate metal contacts, S / D electrodes, silicide contacts, etc. These components may be formed by one or more suitable semiconductor manufacturing processes known in the art.

[0161] Summary

[0162] According to some embodiments of the present disclosure, a field effect transistor (FET) device with a heterogeneous / segmented channel region is provided. In one example, a fin field effect transistor (FinFET) device includes a substrate, a fin structure disposed on the substrate and extending in a horizontal direction, a segmented channel region formed in the fin structure and extending in the horizontal direction, two source / drain (S / D) regions formed in the fin structure and separated by the segmented channel region, and a gate structure formed on the fin structure and surrounding the segmented channel region. The segmented channel region further includes a plurality of channel segments sequentially disposed in the segmented channel region and extending in the horizontal direction, and the plurality of channel segments include a first channel segment and a second channel segment. The first channel segment includes a first channel blocking material and has a first energy barrier, and when the fin field effect transistor device is not in operation, the first energy barrier of the carrier flow path between the two source / drain regions is at least 0.1 electron volts. In some embodiments, the segmented channel region includes a base semiconductor material having a first work function, the first channel blocking material has a second work function, and the second work function is at least 0.1 electron volts higher than the first work function. In some embodiments, the base semiconductor material is Si, and the first channel blocking material is selected from SiGe, SiO2, Ga2O3, TiO2, InP, GaAs, GaP, CdSe, TaON, WO3, ZrO2, ZnS, SiC, SrTiO3, or a combination thereof. In some embodiments, the first channel blocking material is SiGe, and the first channel segment has a Ge weight percentage concentration of 5% to 40%. In some embodiments, the first energy barrier of the first channel segment is 0.1 to 1.0 electron volts. In some embodiments, the first channel blocking material is an epitaxial growth layer formed in the first channel segment. In some embodiments, the first channel blocking material is a channel blocking dopant distributed in the first channel segment, and the doping concentration of the channel blocking dopant is 10 18 atoms / cm 3 to 10 20 atoms / cm3 . In some embodiments, the segmented channel region has a channel length of 5 nm to 50 nm in the horizontal direction, and the first channel segment and the second channel segment have a segmentation length of 1 nm to 30 nm in the horizontal direction. In some embodiments, the second channel segment includes a second channel blocking material, and the second channel segment has a second energy barrier in the carrier flow path between the two source / drain regions, and the first energy barrier is at least 1 time higher than the second energy barrier. In some embodiments, the first channel blocking material is a first channel blocking dopant having a first doping concentration in the first channel segment, the second channel blocking material is a second channel blocking dopant having a second doping concentration in the second channel segment, and the first doping concentration is at least one order of magnitude higher than the second doping concentration. In some embodiments, the first channel segment is connected to one of the two source / drain regions. In some embodiments, the first channel segment is not connected to the two source / drain regions. In some embodiments, the first channel segment is connected to the second channel segment. In some embodiments, the first channel segment is not connected to the second channel segment. In some embodiments, the channel segment includes a third channel segment, and the first channel segment is located between the second channel segment and the third channel segment.

[0163] In another example, a fin field-effect transistor (FinFET) device includes a substrate, a fin structure disposed on the substrate and extending in the horizontal direction, a segmented channel region formed in the fin structure and extending in the horizontal direction, two source / drain (S / D) regions formed in the fin structure and separated by the segmented channel region, and a gate structure formed on the fin structure and surrounding the segmented channel region. The segmented channel region further includes a first channel segment, a second channel segment, a third channel segment, a fourth channel segment, and a fifth channel segment sequentially arranged in the horizontal direction. The second channel segment is located between the first channel segment and the third channel segment, and the fourth channel segment is located between the third channel segment and the fifth channel segment. The second channel segment includes a first channel blocking material and has a first energy barrier, and the fourth channel segment includes a second channel blocking material and has a second energy barrier. When the fin field-effect transistor device is not activated, the first energy barrier and the second energy barrier in the carrier flow path between the two source / drain regions are at least 0.1 electron volts. In some embodiments, the first channel blocking material is the same as the second channel blocking material, and the first energy barrier is substantially equal to the second energy barrier. In some embodiments, the first channel blocking material is different from the second channel blocking material, and the first energy barrier is at least 1 time higher than the second energy barrier.

[0164] According to some embodiments of the present disclosure, a method of manufacturing a FET device is provided. In one example, a method includes forming at least one continuous channel segment in a mandrel layer disposed on a substrate. The at least one continuous channel segment extends in a first horizontal direction and includes a channel blocking material. The method further includes forming two continuous S / D regions in the mandrel layer. The two continuous S / D regions extend along the first horizontal direction, the at least one continuous channel segment is located between the two continuous S / D regions, and the at least one continuous channel segment is not connected to at least one of the two continuous S / D regions. The method further includes forming at least one fin structure in the mandrel layer. The at least one fin structure extends in a second horizontal direction perpendicular to the first horizontal direction, and further includes two S / D regions respectively corresponding to the two continuous S / D regions, and a channel region located between the two S / D regions. The channel region includes a channel segment corresponding to the at least one continuous channel segment. The method further includes forming a gate structure in the first horizontal direction. The gate structure is disposed on the at least one fin structure and surrounds the channel region of the at least one fin structure. The channel segment has an energy barrier, and when the FinFET device is not activated, the energy barrier in the carrier flow path between the two S / D regions is at least 0.1 electron volts (eV). In some embodiments, forming the at least one continuous channel segment includes the steps of: forming a trench extending along the first horizontal direction in the mandrel layer; and growing an epitaxial layer of the channel blocking material in the trench.

[0165] According to some embodiments of the present disclosure, a fin field effect transistor device is provided. The fin field effect transistor device includes a substrate, a fin structure, shallow trench isolation, two source / drain regions, a channel region, and a gate structure. The fin structure is disposed on the substrate and extends along a horizontal direction. The shallow trench isolation is disposed in the substrate and is located on both sides of the fin structure. The two source / drain regions are disposed in at least one fin structure. The channel region is disposed in the fin structure and is located between the two source / drain regions, and the channel region includes a channel segment. The gate structure is disposed on the fin structure and surrounds the channel region of the fin structure. The channel segment has an energy barrier, and when the fin field effect transistor device is not activated, the energy barrier of the carrier flow path between the two source / drain regions is at least 0.1 electron volts. In some embodiments, the fin field effect transistor device further includes an epitaxial layer disposed in the channel segment.

[0166] The present disclosure outlines various embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made by those skilled in the art without departing from the spirit and scope of the present disclosure.

Claims

1. A fin field effect transistor device, characterized in that, Comprising a substrate; a fin structure disposed on the substrate, wherein the fin structure extends along a horizontal direction; a segmented channel region formed in the fin structure and extending along the horizontal direction; two source / drain regions formed in the fin structure and separated by the segmented channel region; and a gate structure formed on the fin structure and surrounding the segmented channel region, wherein the segmented channel region includes a plurality of channel segments sequentially disposed in the segmented channel region and extending along the horizontal direction, and the plurality of channel segments include a first channel segment and a second channel segment, wherein the first channel segment has a first energy barrier, and when the fin field-effect transistor device is not activated, the first energy barrier of the carrier flow path between the two source / drain regions is at least 0.1 electron volts.

2. The fin field effect transistor device according to claim 1, characterized in that, wherein the segmented channel region includes a base semiconductor layer having a first work function, the first channel segment has a second work function, and the second work function is at least 0.1 electron volts higher than the first work function.

3. The fin field effect transistor device according to claim 2, wherein, wherein the segmented channel region has a channel length of 5 nm to 50 nm in the horizontal direction, and the first channel segment and the second channel segment have a segmented length of 1 nm to 30 nm in the horizontal direction.

4. The fin field effect transistor device according to claim 1, wherein wherein the first channel segment includes an epitaxial growth layer.

5. The fin field effect transistor device according to claim 1, wherein, wherein the first channel segment is connected to one of the two source / drain regions.

6. The fin field effect transistor device according to claim 1, characterized in that, wherein the first channel segment is connected to the second channel segment.

7. The fin field effect transistor device according to claim 1, wherein wherein the plurality of channel segments includes a third channel segment, and the first channel segment is located between the second channel segment and the third channel segment.

8. A fin field effect transistor device, characterized in that, Comprising: a substrate; a fin structure disposed on the substrate, and the fin structure extends along a horizontal direction; a segmented channel region formed in the fin structure and extending along the horizontal direction; two source / drain regions formed in the fin structure and separated by the segmented channel region; and a gate structure formed on the fin structure and surrounding the segmented channel region, wherein the segmented channel region includes a first channel segment, a second channel segment, a third channel segment, a fourth channel segment, and a fifth channel segment sequentially disposed along the horizontal direction, the second channel segment is located between the first channel segment and the third channel segment, and the fourth channel segment is located between the third channel segment and the fifth channel segment, wherein the second channel segment has a first energy barrier, and the fourth channel segment has a second energy barrier, wherein when the fin field-effect transistor device is not activated, the first energy barrier and the second energy barrier of the carrier flow path between the two source / drain regions are at least 0.1 electron volts.

9. A fin field effect transistor device, characterized in that, Comprising: a substrate; a fin structure disposed on the substrate and extending along a horizontal direction; a shallow trench isolation disposed in the substrate and located on opposite sides of the fin structure; two source / drain regions disposed in the fin structure; a channel region disposed in the fin structure and located between the two source / drain regions, and the channel region includes a channel segment; and a gate structure disposed on the fin structure and surrounding the channel region of the fin structure; Wherein, the channel section has an energy barrier, and when the fin field effect transistor device is not activated, the energy barrier of the carrier flow path between the two source / drain regions is at least 0.1 electron volts.

10. The fin field effect transistor device according to claim 9, wherein Further comprising: An epitaxial layer disposed in the channel section.

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