Video processing equipment

Abstract

The utility model provides video processing equipment, and relates to the technical field of display control. The video processing equipment can effectively solve the problem that the performance of switching equipment is limited due to the fact that required resources exceed resources which can be provided by the FPGA. The video processing equipment is used for being connected with display equipment; the video processing equipment comprises at least one input module, a central processing unit (CPU) and a graphics processing unit (GPU), each input module is coupled with the CPU through a first high-speed serial computer expansion bus standard PCIe bus, and the CPU is coupled with the GPU through a second PCIe bus. Wherein the input module is used for receiving a first video signal and inputting the first video signal to the CPU through the first PCIe bus; the CPU is used for outputting the first video signal to the GPU through the second PCIe bus; the GPU is used for processing the first video signal to obtain a second video signal and outputting the second video signal, and the display device is used for displaying the second video signal.

Description

Technical Field

[0001] This application relates to the field of display control technology, and in particular, to a video processing device. Background Art

[0002] In the field of light-emitting diode (LED) displays, devices for processing, splicing, and switching lossless videos have always used field-programmable gate arrays (FPGAs) as the processing core. However, with the popularization of 4K and 8K videos, the bandwidth has increased exponentially, and at the same time, the number of input sources has also become larger. For switching devices designed with FPGAs as the processing core, since the hardware resources of FPGAs (such as logic units, lookup tables, and digital signal processors) are limited, when the switching device processes complex video information, if the required resources exceed the resources that the FPGA can provide, it will lead to the problem of limited performance of the switching device. Summary of the Utility Model

[0003] Embodiments of this application provide a video processing device, which can effectively improve the problem of limited performance of the switching device caused by the required resources exceeding the resources that the FPGA can provide.

[0004] To achieve the above object, the embodiments of this application adopt the following technical solutions:

[0005] On the one hand, this application provides a video processing device, which is used to connect to a display device, and an external device is used to display the video signal processed by the video processing device. The video processing device includes: at least one input module, a central processing unit (CPU), and a graphics processing unit (GPU); each input module is coupled to the CPU through a first Peripheral Component Interconnect Express (PCIe) bus, and the CPU is coupled to the GPU through a second PCIe bus.

[0006] Among them, the input module is used to receive a first video signal and input the first video signal to the CPU through the first PCIe bus; the CPU is used to output the first video signal to the GPU through the second PCIe bus; the GPU is used to process the first video signal to obtain a second video signal and output the second video signal, and the display device is used to display the second video signal.

[0007] It should be noted that in the embodiments of this application, the video processing device can be a video processor, a video switcher, a device integrating video processing and control, and a video splicer.

[0008] With the video processing device provided above, a GPU with stronger processing performance is used to replace the traditional FPGA-based processing module, so as to better process video signals and avoid the problem of limited performance of the video processing device caused by the required resources exceeding those provided by the FPGA. And in the embodiments of the present application, in order to make better use of the performance of the GPU, the PCIe bus is used as a communication bridge, and then the video signal can be sent to the GPU through the PCIe bus, thereby effectively improving the processing performance of the video processing device.

[0009] In an alternative embodiment, the video processing device further includes: at least one output module, the output module is coupled to the CPU, and the target output module is configured to receive the second video signal, convert the format of the second video signal, and output the second video signal.

[0010] It can be understood that since the number of interfaces of the GPU is small and cannot meet the link requirements of multi-channel input-video processing-multi-channel output, an output module can be used to expand the output interface. Similarly, the input module is an expansion of the input interface to meet the multi-link requirements.

[0011] In an alternative embodiment, the output module is a video output module; the video output module is coupled to the CPU through a third PCIe bus, and the target video output module is configured to receive the second video signal, convert the second video signal with PCIe format into a second video signal with non-PCIe format, and output the second video signal with non-PCIe format.

[0012] It should be noted that multiple video output modules can be coupled to the CPU through the third PCIe bus, and the CPU can select a target video output module from the multiple video output modules as the video output module for outputting the second video signal.

[0013] In view of this, the target video output module can convert the second video signal in PCIe format into a second video signal in non-PCIe format, such as opt or video, and output the second video signal to the sending card at the backend.

[0014] In an alternative embodiment, the output module is a network output module; the network output module is coupled to the CPU through a fourth PCIe bus, and the target network output module is configured to convert the second video signal with PCIe format into a second video signal with network format, and output the second video signal with network format.

[0015] It should be noted that multiple video output modules can be coupled to the CPU via the fourth PCIe bus. The CPU can select a target network output module from among the multiple video output modules as the video output module for outputting the second video signal.

[0016] In view of this, the target network output module can directly convert the second video signal of PCIe into a second video signal in network format, and output the second video signal to the backend LED screen by the target network output module without conversion and transmission by the sending card.

[0017] In an alternative embodiment, the video processing device further includes: a storage module. The storage module is coupled to the CPU via a communication bus and is used for storing the first video signal and / or the second video signal; or, the storage module is coupled to the input module via a communication bus.

[0018] Optionally, the memory can exist independently of the GPU, that is, the memory can be an external memory of the GPU. It can also be integrated with the GPU.

[0019] In an alternative embodiment, the input module is an input board; the video processing device further includes: a switching backplane. Multiple PCIe interface slots are provided on the switching backplane; the CPU is disposed on the switching backplane and is coupled to the multiple PCIe interface slots; the input board is coupled to the first PCIe interface slot among the multiple PCIe interface slots of the switching backplane via a first PCIe interface; the GPU is coupled to the second PCIe interface slot among the multiple PCIe interface slots of the switching backplane via a second PCIe interface.

[0020] Wherein, the input board is used for inputting the first video signal to the CPU via the first PCIe interface; the CPU is used for outputting the first video signal to the GPU; the GPU is used for processing the first video signal to obtain a second video signal and outputting the second video signal.

[0021] In view of this, this architecture corresponds to the traditional plug-in switcher, replacing the original FPGA-based processing module with a GPU, and the PCIe interconnection itself can also replace the basic CP to achieve the function of high-speed matrix switching. The expansion of the input only requires designing a corresponding input board, and any type of video signal can be connected to the video processing device.

[0022] That is to say, the input board can convert video signals in HDMI, DP, and SDI formats into video signals in PCIe format. The input board is coupled to the first PCIe interface slot of the switching backplane through the first PCIe interface. Furthermore, the mutual transmission of signals between the GPU and the capture card can be realized through the driver and the upper-layer software. After video processing in the GPU, the second video signal can be output through the output interface of the GPU, greatly improving the video processing performance.

[0023] In an alternative embodiment, the video processing device further includes: at least one output module, and the output module is an output board; the output board is coupled to the third PCIe interface slot among the multiple PCIe interface slots of the switching backplane through the third PCIe interface. The output board is configured to receive the second video signal, convert the format of the second video signal, and output the second video signal.

[0024] In view of this, since the output board is coupled to the third PCIe interface slot of the switching backplane through the third PCIe interface, the GPU can output the second video signal to the output board through the PCIe line. The output board converts the format of the second video signal and outputs the second video signal to the outside. That is to say, the second video signal can also be extended and output through the PCIe slot.

[0025] In an alternative embodiment, the output board includes a third PCIe interface, a second conversion chip, and a video output interface connected in sequence; the third PCIe interface is configured to receive the second video signal in PCIe format; the second conversion chip is configured to convert the format of the second video signal in PCIe format to obtain the second video signal in a non-PCIe format; the video output interface is configured to output the second video signal in a non-PCIe format.

[0026] In an alternative embodiment, the video output interface includes at least one of the following interfaces: High-Definition Multimedia Interface HDMI, DisplayPort DP, Serial Digital Interface SDI, Optical Fiber Interface OPT, Network Device Interface NDI, ST2110 interface.

[0027] For example, the second conversion chip converts the second video signal in PCIe format into a second video signal in optical fiber format and outputs the second video signal to the sending card at the backend through the optical fiber interface OPT.

[0028] In an alternative embodiment, the output board includes a third PCIe interface, a second conversion chip, and a network output interface connected in sequence; the third PCIe interface is used to receive a second video signal in PCIe format; the second conversion chip is used to perform format conversion on the second video signal in PCIe format to obtain the second video signal in network format; the network output interface is used to output the second video signal in network format.

[0029] Specifically, the second conversion chip converts the second video signal in PCIe format into the second video signal in network format, and outputs the second video signal in network format to the LED screen at the backend through the network output interface.

[0030] In an alternative embodiment, the input board includes a video interface, a first conversion chip, and a first PCIe interface connected in sequence; the video interface is used to receive a first video signal; the first conversion chip is used to perform PCIe format conversion on the first video signal; the first PCIe interface is used to output the first video signal to the CPU.

[0031] Optionally, the video interface includes at least one of the following interfaces: High-Definition Multimedia Interface (HDMI), DisplayPort (DP), and Serial Digital Interface (SDI).

[0032] For example, when the HDMI video interface receives a video source, the first conversion chip can convert the video source into a first video signal in PCIe format and output the first video signal to the CPU through the first PCIe interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1a It is an architecture diagram of a video processing provided by an embodiment of the present application;

[0034] Figure 1b It is another architecture diagram of a video processing provided by an embodiment of the present application;

[0035] Figure 1c It is another architecture diagram of a video processing provided by an embodiment of the present application;

[0036] Figure 1d It is another architecture diagram of a video processing provided by an embodiment of the present application;

[0037] Figure 2a It is another architecture diagram of a video processing provided by an embodiment of the present application;

[0038] Figure 2b It is an architecture diagram of an input board provided by an embodiment of the present application;

[0039] Figure 2cAn architecture diagram of an output board card provided by an embodiment of the present application;

[0040] Figure 2d Another architecture diagram of an output board card provided by an embodiment of the present application;

[0041] Figure 3 Another architecture diagram of video processing provided by an embodiment of the present application;

[0042] Figure 4 A flowchart of a video signal processing method provided by an embodiment of the present application. Detailed implementation manners

[0043] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings in the embodiments of the present application. Among them, in the description of the present application, unless otherwise specified, "at least one" means one or more, and "a plurality" means two or more than two. In addition, in order to facilitate a clear description of the technical solutions in the embodiments of the present application, in the embodiments of the present application, terms such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. Those skilled in the art can understand that the terms "first", "second", etc. do not limit the quantity and execution order, and the terms "first", "second", etc. do not necessarily limit to be different.

[0044] In the field of light emitting diode (LED) displays, the processing, splicing, and switching devices for lossless videos have always used field programmable gate array (FPGA) as the processing core. However, with the popularization of 4K and 8K videos, the bandwidth has increased exponentially, and at the same time, the number of input sources has become larger. For a switching device designed with FPGA as the processing core, such as a single-card switcher, the number of input sources is fixed, and generally one or two FPGAs are responsible for video processing. Therefore, the input interface capability cannot be expanded, and at the same time, the video processing capability cannot be expanded. If an upgrade is needed, a major modification is required from the entire hardware to the software.

[0045] To avoid the above problems, the switcher devices have gradually transitioned from single cards to plug-in card matrices. Currently, most plug-in card matrix switchers are designed based on mother-daughter cards. The input sources can usually be changed and expanded through different daughter cards. Multiple sources need to use a cross point (CP) matrix for multi-channel switching. The center is still a large-scale FPGA responsible for video processing, and the output is also designed in the form of daughter cards.

[0046] The above-mentioned plug-in matrix switch can basically cope with part of the pressure on FPGA resources and bandwidth caused by the increase in the number of input sources. However, since the processing core is still the FPGA, the specification of the core FPGA becomes larger and larger, and it is impossible to achieve a balance between performance and cost. Summing up, the traditional architecture has the following three potential hazards: 1. Using the FPGA as the processing core results in limited video processing performance, and inexpensive FPGAs cannot support double data rate synchronous dynamic random access memory (DDR SDRAM) with ultra-high bandwidth, which is doomed to greatly reduce the processing performance of high resolutions. 2. Traditional plug-in cards rely on powerful CP performance, generate a lot of heat and are expensive. 3. All functions rely on underlying hardware implementation, and if different models or different manufacturers' FPGAs are replaced, there is also a risk of function transplantation, resulting in slow product updates.

[0047] That is to say, since the hardware resources of the FPGA (such as logic units, look-up tables, and digital signal processors) are limited, when the switching device processes complex video information, if the required resources exceed the resources that the FPGA can provide, it will lead to the problem of limited performance of the switching device.

[0048] To improve the above problems, the embodiments of the present application provide a video processing device, which includes: at least one input module, a central processing unit (CPU), and a graphics processing unit (GPU); each input module is coupled to the CPU through a first Peripheral Component Interconnect Express (PCIe) bus, and the CPU is coupled to the GPU through a second PCIe bus.

[0049] Among them, the input module is used to receive the first video signal and input the first video signal to the CPU through the first PCIe bus. The CPU is used to output the first video signal to the GPU through the second PCIe bus. The GPU is used to process the first video signal to obtain a second video signal and output the second video signal.

[0050] Through the above-provided video processing device, a GPU with stronger processing performance is used to replace the traditional FPGA-based processing module, so as to better process video signals and avoid the problem of limited performance of the video processing device caused by the required resources exceeding the resources that the FPGA can provide. And in order to make better use of the performance of the GPU in the embodiments of the present application, the PCIe bus is used as a communication bridge, and then the video signal can be sent to the GPU through the PCIe bus, thereby effectively improving the processing performance of the video processing device.

[0051] Figure 1a This is an architecture diagram for video processing provided by an embodiment of the present application. As Figure 1a shown, in this architecture diagram, it includes a video processing device and a display device 180. The video processing device is used to connect to the display device 180, and the display device 180 is used to display a second video signal.

[0052] It should be noted that this display device can be an LCD screen or an LED screen.

[0053] This video processing device includes: at least one input module 110, a central processing unit CPU 120, and a graphics processing unit GPU 130.

[0054] In some embodiments, each input module 110 is coupled to the CPU 120 through a first Peripheral Component Interconnect Express (PCIe) bus 160, and the CPU 120 is coupled to the GPU 130 through a second PCIe bus 170.

[0055] It can be understood that using the PCIe interconnection solution as an alternative can not only effectively reduce the dependence on expensive CPUs, but also its versatility and flexibility significantly reduce the complexity of hardware design and power consumption pressure. Optimizing the system architecture through the PCIe interconnection strategy improves the overall performance while also reducing the development and maintenance costs.

[0056] Among them, the input module 110 is used to receive a first video signal and input the first video signal to the CPU 120 through the first PCIe bus 160. It should be noted that each output module can receive at least one path of the first video signal, that is, it can also receive multiple paths of the first video signal.

[0057] In some embodiments, the CPU 120 is used to output the first video signal to the GPU 130 through the second PCIe bus 170. Exemplarily, the CPU 120 can adopt an x86 architecture processor of Intel or AMD. Among them, the CPU 120, as the core control unit, can not only run various software and drivers, but also control and allocate PCIe resources.

[0058] In some embodiments, the GPU 130 can be used to process the first video signal to obtain a second video signal and output the second video signal. In one embodiment, the GPU 130 can output the second video signal to the output module 140 through the CPU 120. In another embodiment, the GPU 130 can directly output the second video signal through its own output interface.

[0059] It can be understood that in the embodiments of the present application, the GPU 130 is used to replace the processing module with an FPGA as the core. With its excellent video processing capabilities and large memory bandwidth, the GPU 130 has shown overwhelming advantages in the field of video processing compared to traditional FPGA technologies. It can process complex video tasks more efficiently and achieve more delicate and smooth visual effects.

[0060] At the same time, due to the fixedness and standardization of the GPU 130 hardware architecture, the logic of video rendering and processing is mainly implemented through software. This design not only improves the flexibility of functions but also enables more rapid function iteration, keeping pace with the development of technology. Meanwhile, the software-based implementation method also makes problem troubleshooting more direct and efficient, allowing users or technicians to locate and solve potential technical problems more quickly.

[0061] Optionally, the video processing device further includes: at least one output module 140. The output module 140 is coupled to the CPU 120.

[0062] In some embodiments, when there are multiple output modules 140, the target output module among the multiple output modules is used to receive the second video signal output by the GPU, perform format conversion on the second video signal, and output the second video signal after format conversion. Exemplarily, as shown in Figure 1a The output module 140 can output the second video signal to the display device 180.

[0063] It can be understood that the CPU can also control and allocate PCIe resources to enable data interaction between the GPU 130 and the output module 140.

[0064] Among them, as shown in Figure 1b The output module 140 can be a video output module 210. Exemplarily, if the output module 140 is a video output module 210, the external device display device 180 may include a sending card 220 and may be an LED screen 230. The video output module 210 can be coupled to the CPU 120 through a third PCIe bus 240 and connected to the LED screen 230 through the sending card 220. Among them, the target video output module among the multiple video output modules 210 is used to receive the second video signal, convert the second video signal with a PCIe format into a second video signal with a non-PCIe format, such as video transmission formats such as HDMI and DVI, and output the second video signal with the non-PCIe format to the sending card 220.

[0065] Another example, as shown in Figure 1cAs shown, when the output module 140 is the video output module 210, the display device 180 can be the LCD screen 250. The video output module 210 can be connected to the LCD screen 250 to output a second video signal in a non-PCIe format to the LCD screen 250.

[0066] It should be noted that, as Figure 1d shown, the output module 140 can also be the network output module 310. When the output module 140 is the network output module 310, the display device 180 can be the LED screen 230, and the network output module 310 can directly output the second video signal to the LED screen 230.

[0067] In another example, if the output module 140 is the network output module 310, the network output module 310 can be coupled to the CPU 120 through the fourth PCIe bus 320. Among them, the target network output module among the multiple network output modules 310 is used to convert the second video signal with a PCIe format into a second video signal with a network format and output the second video signal.

[0068] It should be noted that the video processing device provided in the embodiments of the present application can be a video processor, a video switcher, a video processing and control integrated device, and a video splicer.

[0069] Optionally, the video processing device further includes: a storage module 150, and the storage module 150 is coupled to the CPU 120 through a communication bus

[0070] In some embodiments, the storage module 150 can be a memory. The memory can be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM), or other optical disc storage (including compressed optical discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), a magnetic disk storage medium, or other magnetic storage devices, or any other medium that can be used to include or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto.

[0071] In a possible design, the memory can exist independently of the CPU 120, that is, the memory can be an external memory of the CPU 120. At this time, the memory can be connected to the CPU 120 through a communication bus, used to store execution instructions or application program codes, and controlled by the CPU 120 to execute, so as to implement the video signal processing method provided in the following embodiments of the present application. In another possible design, the memory can also be integrated with the GPU 130, that is, the memory can be an internal memory of the GPU 130. For example, the memory is a cache, which can be used to temporarily store some data and instruction information, etc. If the CPU 120 needs to use the instruction or data, it can directly call from the memory, avoiding repeated accesses, reducing the waiting time of the CPU 120, and thus improving the processing efficiency of the video signal.

[0072] The video processing device provided in the embodiments of the present application uses the GPU 130 as the core for video processing, making its replacement more rapid. The functions that used to require multiple devices to cooperate can now be integrated into a single product, achieving comprehensive integration and optimization of functions, and significantly reducing the overall cost, bringing a more efficient, more economical, and more convenient solution to users.

[0073] Figure 2a It is an architecture diagram of another video processing provided in the embodiments of the present application. In this architecture diagram, it includes a video processing device and a display device 180. The video processing device is used to connect to the display device 180, and the display device 180 is used to display a second video signal.

[0074] It should be noted that the display device can be an LCD screen or an LED screen. As Figure 2a shown, the video processing device includes: a switching backplane 410, at least one input board 500, a CPU 120, and a GPU 130.

[0075] Among them, a plurality of PCIe interface slots are provided on the switching backplane.

[0076] In some embodiments, the CPU 120 is disposed on the switching backplane 410 and is coupled to a plurality of PCIe interface slots of the switching backplane 410. The CPU 120 is used to output a first video signal to the GPU 130.

[0077] In another scenario, in combination with Figure 2a , since the input board 500 has been coupled to the first PCIe interface slot 430 of the switching backplane 410 through the first PCIe interface 420, the communication between the input board 500 and the GPU 130 can be realized through the software installed on the CPU 120.

[0078] In some embodiments, the GPU 130 is coupled to the second PCIe interface card slot 470 in the multiple PCIe interface card slots of the switch backplane 410 through the second PCIe interface 460. The GPU 130 is configured to process the first video signal to obtain a second video signal and output the second video signal.

[0079] Optionally, the GPU 130 can be an independent graphics card. Generally, high - end and mid - range graphics cards are equipped with high - speed LPDDR5 video memory, which can greatly increase the video processing bandwidth.

[0080] It can be understood that since the GPU 130 is coupled to the second PCIe interface card slot 470 of the switch backplane 410 through the second PCIe interface 460, only the GPU 130 graphics card can be replaced during the subsequent product upgrade and replacement. At the same time, if more video sources need to be supported, only the switch backplane needs to be replaced.

[0081] It should be noted that Figure 2a is a video processing device form with a PCIe connection architecture. The hardware core is the switch backplane 410 including the GPU 130, CPU 120, and DDR memory, which can be understood as a personal computer (personal host). For the convenience of product update and iteration, the CPU 120 can be upgraded, but attention needs to be paid to the compatibility between the CPU 120 and the switch backplane 410.

[0082] It can be understood that the processing methods of the above - mentioned CPU 120 and GPU 130 are the architectures of current media servers. Various open - source and self - developed software can run on the CPU 120. Then, while using the GPU 130 for video processing, by adding peripherals such as the input module 110 and output module 140 (PCIe output card), it can be expanded to the functions of a media server and a video processing device, and even carry a sending function, that is, the video processing device can complete all the work of the LED display link.

[0083] It should be noted that the embodiments of the present application can select a switch backplane with multiple PCIe slots to ensure sufficient expansion ability. The number and version of PCIe slots (such as PCIe 3.0, PCIe 4.0, or higher) will directly affect the scalability and performance of the system.

[0084] In the case where specific requirements cannot be met by commercially available switch motherboards, a customized switch backplane can be considered. The customized switch backplane can design the number, layout, and other interfaces of PCIe slots according to specific requirements to achieve the best performance matching and scalability. Or an off - the - shelf motherboard can be purchased. There are many high - performance x86 - architecture motherboards available on the market, which usually have multiple PCIe slots and rich interfaces.

[0085] It is understandable that since the number of interfaces of GPU 130 is small and cannot meet the multi-channel input-video processing link requirements, the input module 110 can be used as an extension of the input interface to meet the multi-link requirements.

[0086] In some embodiments, a plurality of input boards 500 are provided to meet the requirements of multi-channel input. The input board 500 is coupled to a first PCIe interface card slot 430 of a plurality of PCIe interface card slots of a switching backplane through a first PCIe interface 420, and the input board can be used to input a first video signal to the CPU 120 through the first PCIe interface 420.

[0087] For example, Figure 2b As shown, the input board 500 can be understood as a PCIe acquisition card. The input board 500 can include a video interface 510, a first conversion chip 520 and a first PCIe interface 420 connected in sequence. Among them, the video interface 510 can be used to receive a first video signal; the first conversion chip 520 is used to convert the first video signal into a PCIe format; and the first PCIe interface 420 is used to output the first video signal to the CPU 120.

[0088] In one scenario, by inserting the input board 500 (PCIe acquisition card) into the first PCIe interface card slot 430 of the switch baseboard, all video signals can be received and converted into first video signals in PCIe format.

[0089] Optionally, the first conversion chip 520 can be implemented by an FPGA. The efficient operation of the input board 500, in addition to relying on the powerful processing power of the FPGA on the card, is also inseparable from the collaborative work of efficient drivers. As a key underlying software component, the PCIe driver of the input board 500 has a function similar to that of the universal serial bus (USB) driver, which is designed to accurately control the data flow between the input board 500 and the GPU 130 and the memory to ensure the efficiency and stability of data interaction. Through the PCIe driver, the optimal configuration of resources can be achieved, further improving the overall performance.

[0090] It should be noted that the above mentioned input board 500 module 110 meets the link requirements of multiple inputs. Accordingly, since the number of interfaces of GPU 130 is small and cannot meet the link requirements of multiple outputs, the output module 140 board 600 can be used to expand the output interface.

[0091] Optionally, the video processing device further includes: at least one output board 600 .

[0092] In some embodiments, a plurality of output boards 600 are provided to meet the requirements of multi-channel output. Among them, the output board 600 can be coupled to the third PCIe interface slot 450 in a plurality of PCIe interface slots of the switching backplane 410 through the third PCIe interface 440. The output board 600 is used to receive the second video signal, convert the format of the second video signal, and output the second video signal.

[0093] An example is as Figure 2c shown. The output board 600 may include a third PCIe interface 440, a second conversion chip 620, and a video output interface 630 that are connected in sequence. Among them, the third PCIe interface 440 is used to receive the second video signal with PCIe format; the second conversion chip 620 is used to convert the format of the second video signal with PCIe format to obtain a non-PCIe format; the video output interface 630 is used to output the second video signal with non-PCIe format.

[0094] It should be noted that the video output interface 630 can be connected to the LED screen through a sending card and output the second video signal with non-PCIe format to the sending card. The video output interface 630 can also be connected to the LCD screen and output the second video signal with non-PCIe format to the LCD screen.

[0095] In some embodiments, the video output interface 630 includes at least one of the following interfaces: High-Definition Multimedia Interface HDMI, DisplayPort DP, Serial Digital Interface SDI, Optical Fiber Interface OPT, Network Device Interface NDI, ST2110 interface.

[0096] Another example is as Figure 2d shown. The output board 600 includes a third PCIe interface 440, a second conversion chip 620, and a network output interface 640 that are connected in sequence. Among them, the third PCIe interface 440 is used to receive the second video signal with PCIe format; the second conversion chip 620 is used to convert the format of the second video signal with PCIe format to obtain the second video signal with network format; the network output interface 640 is used to output the second video signal with network format.

[0097] It should be noted that the network output interface 640 can be connected to the LED screen and output the second video signal with network format to the LED screen.

[0098] Optionally, the second conversion chip 620 can be implemented by an FPGA.

[0099] Optionally, the video processing device further includes: a memory 700.

[0100] In some embodiments, the memory 700 is coupled to the CPU via a communication bus or coupled to the input module via a communication bus. In a possible design, the memory 700 can exist independently of the CPU 120 and the GPU 130, that is, the memory 700 can be an external memory 700 for the CPU 120 and the GPU 130. At this time, the memory 700 can be connected to the CPU 120 and the GPU 130 via a communication bus, used to store execution instructions or application program codes, and controlled by the CPU 120 to execute, so as to implement the video signal processing method provided in the following embodiments of the present application. In another possible design, the memory 700 can also be integrated with the GPU 130, that is, the memory 700 can be an internal memory 700 of the GPU 130. For example, this memory 700 is a cache, which can be used to temporarily store some data and instruction information, etc. If the CPU 120 needs to use this instruction or data, it can directly call it from the memory 700, avoiding repeated accesses, reducing the waiting time of the CPU 120, and thus improving the processing efficiency of video signals.

[0101] It can be understood that in the embodiments of the present application, replacing the existing high-end motherboard with the CPU 120 can facilitate product iteration more conveniently. The processing method of CPU 120 + GPU 130 is the current architecture of the media server. Various open-source and self-developed software can run on the CPU 120. However, once the GPU 130 is used for video processing and peripheral devices such as PCIe capture cards and PCIe output cards are added, it can be fully expanded into the role of a media server + video processing device, and even carry the sending function, and one device can complete all the work of the LED display link.

[0102] Figure 3 Another architecture diagram of video processing provided by the embodiments of the present application is as Figure 3 shown. The video processing device includes: a switching backplane 410, at least one input board 500, a CPU 120, a GPU 130, a storage module 150, and at least one output board 600.

[0103] The following combines Figure 3 , and introduces the overall processing flow of the video processing device. The input module can be an input board 500 with an FPGA as the core. The input board 500 can convert video signals in HDMI, DP, SDI, OPT (optical fiber), NDI, and ST2110 formats into video signals in PCIe format. The corresponding video information (the first video signal) can enter the storage module 150 of the video processing device through the first PCIe interface 420, or directly interact with the GPU 130 for data.

[0104] Furthermore, the GPU 130 processes the first video signal (layer aliasing, windowing, scaling, rotation, image quality adjustment, etc.) to obtain a second video signal, which can be output by the GPU 130 to the sending card at the backend. The GPU 130 can also output the second video signal to the output board 600 through the CPU 120 and the third PCIe interface 440. Furthermore, the second video signal is converted into various video interface signals through the FPGA on the output board 600, including but not limited to HDMI, DP, SDI, OPT (optical fiber), NDI, and ST2110, that is, the output board 600 outputs the second video signal to the display device 180 at the backend.

[0105] In summary, the video processing device using the GPU 130 provided in the embodiments of the present application significantly shortens the hardware R & D cycle. Its core advantages lie in the flexibility and expandability of functions, and most of these functions are controlled through an advanced software interface, making the user experience brand new. And the video processing device can be understood as a personal computer, with the Windows system familiar to users pre-installed on the host. After connecting to the public network, users can easily achieve remote control, greatly improving the operation convenience and flexibility.

[0106] At the same time, thanks to the maturity and wide application of the GPU 130 rendering technology, as well as the support of rich open-source resources, the video processing device can easily implement a variety of advanced video effects, including but not limited to matte keying, border shadow, cut & fill, BKG (background replacement), creating unlimited creative space for users. In addition, through the way of software paid upgrade, users can unlock more advanced functions and enjoy a continuously optimized user experience, because the function iteration speed of software-driven is much faster than that of traditional hardware upgrade. When encountering problems, users can quickly obtain technical support through the remote connection function, and problem troubleshooting becomes efficient and fast.

[0107] For the complex scenario of cascading multiple devices for use, the video processing device cleverly uses the synchronization interface of the graphics card to implement the genlock function, ensuring high-precision synchronization between multiple devices, simplifying the synchronization problem in large-scale video production and live broadcast, and providing unprecedented flexibility and reliability for professional users.

[0108] Figure 4 It is a flowchart of a video signal processing method provided in the embodiments of the present application. This method is implemented by Figure 1a the video processing device shown, or by Figure 2a the video processing device shown. Whether it is Figure 1a the video processing device shown or Figure 2a the video processing device shown, both include at least one input module, a GPU, and a CPU. As Figure 4As shown, the video signal processing method may include:

[0109] S401. The input module receives a first video signal.

[0110] Specifically, the first video signal may be a video signal having HDMI, DP, SDI, OPT (optical fiber), NDI, and ST2110 formats.

[0111] In some embodiments, as shown in combination with Figure 1a shown, when the input module receives the first video signal, it may convert the first video signal in the above non-PCIe format into a first video signal in PCIe format.

[0112] In still other embodiments, as shown in combination with Figure 2a shown, when the input module receives the first video signal, it may convert the first video signal in the above non-PCIe format into a first video signal in PCIe format.

[0113] S402. The input module sends the first video signal to the CPU via a first PCIe bus. Correspondingly, the CPU receives the first video signal.

[0114] In some embodiments, the input module sends the first video signal in PCIe format to the CPU via a first PCIe bus, and the first video signal may be stored in the storage module. Alternatively, the input module sends the first video signal to a switching backplane provided with the CPU via a first PCIe interface, and the first video signal may enter the storage module via a communication bus.

[0115] It should be noted that the above first video signal may not only be stored in the storage module but also directly stored in the video memory of the GPU.

[0116] S403. The CPU outputs the first video signal to the GPU. Correspondingly, the GPU receives the first video signal.

[0117] In some embodiments, as shown in combination with Figure 1a shown, when the first video signal is stored in the storage module, the CPU may schedule the first video signal in the storage module to the GPU.

[0118] In still other embodiments, as shown in combination with Figure 2a shown, when the first video signal is stored in the storage module, the CPU may send a first control instruction to the GPU, instructing the GPU to obtain the first video signal in the storage module and process the first video signal.

[0119] Alternatively, when the first video signal is stored in the GPU video memory, the CPU can send a second control instruction to the GPU, and the second control instruction is used to instruct the GPU to process the first video signal in the video memory.

[0120] S404. The GPU processes the first video signal to obtain a second video signal and outputs the second video signal.

[0121] In some embodiments, the processing of the first video signal by the GPU includes at least one of the following: layer aliasing, windowing, scaling, rotation, and image quality adjustment.

[0122] It should be noted that the above GPU outputs the second video signal, which can specifically be any one of the following two situations.

[0123] Situation (1). The GPU outputs the second video signal to the outside. The output interface of the GPU can include an HDMI interface and a DP interface.

[0124] In one scenario, the GPU performs video rendering and processing on the first video signal to obtain a second video signal. The GPU can output the second video signal to an external sending card through an HDMI interface or a DP interface, and then the external sending card converts the second video signal into a second video signal with a network format and inputs it to the LED screen.

[0125] It should be noted that the number of output interfaces of the GPU is small and may not be able to meet the link requirements of multi-channel input-video processing-multi-channel output. Therefore, the output interface can be expanded through an output module.

[0126] Situation (2). The GPU receives the control instruction from the CPU and outputs the second video signal to the output module. The output module can be a video output module and / or a network output module.

[0127] In one scenario, as Figure 1b shown, the GPU can output the second video signal with a PCIe format to the video output module through the CPU, and the video output module converts the second video signal with a PCIe format into a second video signal in a non-PCIe format (other form) and outputs it to an external sending card. The sending card converts the second video signal in a non-PCIe format into a second video signal with a network format and outputs it to the LED screen. For example, it is converted into fiber optic output, multi-channel HDMI / DP / SDI output, NDI output, and ST2110 interface output.

[0128] It should be noted that in the LED display field, the source distance from the intermediate device and the large screen is very far. Therefore, fiber optic transmission has become an essential solution at present, which can take into account the advantages of lossless high image quality and long-distance transmission.

[0129] In another scenario, such as Figure 1d shown, the GPU can output a second video signal in PCIe format to the network output module through the CPU. The network output module converts the second video signal in PCIe format into a second video signal in network format and outputs it to the LED screen.

[0130] In another scenario, combined with Figure 2a shown, since the output module is coupled to the third PCIe interface slot of the switch backplane through the third PCIe interface, the GPU can output the second video signal to the output module through the PCIe line. The output module converts the format of the second video signal and outputs the second video signal to the outside.

[0131] It can be understood that if the output module is a video output module, the output module outputs the second video signal to the external sending card. If the output module is a network output module, the output module directly outputs the second video signal in network format to the external LED screen.

[0132] In summary, the video processing method driven by the GPU as the core has completely revolutionized the limitations of the traditional FPGA solution, realized a leapfrog improvement in the processing capacity of the video processing device, and greatly enhanced the processing performance of video switching.

[0133] Through the description of the above embodiments, those skilled in the art can clearly understand that for the convenience and simplicity of description, only the above division of each functional module is used as an example. In actual applications, the above functions can be allocated to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

[0134] In several embodiments provided in the present application, it should be understood that the disclosed device / equipment and method can be implemented in other ways. For example, the device / equipment embodiments described above are only illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point, the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in electrical, mechanical or other forms.

[0135] The unit described as a separation component may or may not be physically separated. The component displayed as a unit may be a single physical unit or multiple physical units, that is, it may be located in one place or may be distributed to multiple different places. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0136] In addition, each functional unit in various embodiments of the present application may be integrated into a processing unit, may exist physically separately for each unit, or two or more units may be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0137] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on such an understanding, the technical solution of the embodiments of the present application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to enable a device (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the methods in various embodiments of the present application. The aforementioned storage medium includes: USB flash drives, mobile hard disks, read only memory (ROM), random access memory (RAM), magnetic disks, or optical discs and other various media that can store program codes.

[0138] The above content is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A video processing device, characterized in that, The video processing device is used to connect to a display device; The video processing device includes: at least one input module, a central processing unit (CPU), and a graphics processing unit (GPU); each of the input modules is coupled to the CPU via a first Peripheral Component Interconnect Express (PCIe) bus, and the CPU is coupled to the GPU via a second PCIe bus; Wherein, the input module is configured to receive a first video signal and input the first video signal to the CPU via the first PCIe bus; The CPU is configured to output the first video signal to the GPU via the second PCIe bus; The GPU is configured to process the first video signal to obtain a second video signal and output the second video signal, and the display device is configured to display the second video signal.

2. The video processing device according to claim 1, wherein The video processing device further includes: At least one output module, the output module is coupled to the CPU, and in the case where there are multiple output modules, a target output module among the multiple output modules is configured to receive the second video signal, perform format conversion on the second video signal, and output the second video signal.

3. The video processing device according to claim 2, wherein, The output module is a video output module; The video output module is coupled to the CPU via a third PCIe bus, and a target video output module among the multiple video output modules is configured to receive the second video signal, convert the second video signal with a PCIe format into the second video signal with a non-PCIe format, and output the second video signal with a non-PCIe format.

4. The video processing device according to claim 2, characterized in that, The output module is a network output module; The network output module is coupled to the CPU via a fourth PCIe bus, and the target network output module is configured to convert the second video signal with a PCIe format into the second video signal with a network format and output the second video signal with a network format.

5. The video processing device according to claim 1, characterized in that, The video processing device further includes: A storage module, the storage module is coupled to the CPU via a communication bus and is configured to store the first video signal and / or the second video signal; or, The storage module is coupled to the input module via a communication bus.

6. The video processing device according to claim 1, wherein The input module is an input board; The video processing device further includes: a switching backplane, and a plurality of PCIe interface slots are provided on the switching backplane; The CPU is disposed on the switching backplane, and the CPU is coupled to the plurality of PCIe interface slots; The input board is coupled to a first PCIe interface slot among the plurality of PCIe interface slots of the switching backplane via a first PCIe interface; The GPU is coupled to a second PCIe interface slot among the plurality of PCIe interface slots of the switching backplane via a second PCIe interface; Wherein, the input board is configured to input the first video signal to the CPU via the first PCIe interface; The CPU is configured to output the first video signal to the GPU; The GPU is configured to process the first video signal to obtain a second video signal and output the second video signal.

7. The video processing device according to claim 6, characterized in that, The video processing device further includes: at least one output module, and the output module is an output board. The output board is coupled to a third PCIe interface slot among the multiple PCIe interface slots of the switching backplane through a third PCIe interface. The output board is configured to receive the second video signal, perform format conversion on the second video signal, and output the second video signal.

8. The video processing device according to claim 7, wherein The output board includes a third PCIe interface, a second conversion chip, and a video output interface that are connected in sequence. The third PCIe interface is configured to receive the second video signal in PCIe format. The second conversion chip is configured to perform format conversion on the second video signal in PCIe format to obtain the second video signal in a non-PCIe format. The video output interface is configured to output the second video signal in a non-PCIe format.

9. The video processing device according to claim 8, wherein The video output interface includes at least one of the following interfaces: High-Definition Multimedia Interface (HDMI), DisplayPort (DP), Serial Digital Interface (SDI), Optical Fiber Interface (OPT), Network Device Interface (NDI), and ST2110 interface.

10. The video processing device according to claim 7, characterized in that, The output board includes a third PCIe interface, a second conversion chip, and a network output interface that are connected in sequence. The third PCIe interface is configured to receive the second video signal in PCIe format. The second conversion chip is configured to perform format conversion on the second video signal in PCIe format to obtain the second video signal in a network format. The network output interface is configured to output the second video signal in a network format.

11. The video processing device according to any one of claims 6 to 10, characterized in that, The input board includes a video interface, a first conversion chip, and the first PCIe interface that are connected in sequence. The video interface is configured to receive the first video signal. The first conversion chip is configured to perform PCIe format conversion on the first video signal. The first PCIe interface is configured to output the first video signal to the CPU.

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