Double-channel CPU (central processing unit) server mainboard

Abstract

The utility model relates to a double-channel CPU (central processing unit) server mainboard. The double-channel CPU server mainboard comprises two SW6432 CPUs, a memory slot, two GENZ 4C + connectors, two Riser cards, a PCIE switch chip, a PCIE to USB (Universal Serial Bus) chip, a USB HUB, a BMC (Baseboard Management Controller) card interface, two solid state disks, two OCP (Open Configuration Protocol) connectors and a CPLD (Complex Programmable Logic Device), and the first SW6432 CPU (CPU0) and the second SW6432 CPU (CPU1) are electrically connected with each other through a DLI (Digital Light Interface) high-speed direct connection port. According to the double-channel CPU server mainboard, a domestic processor SW6432 double-channel CPU design is adopted to complete the server mainboard scheme, and the design guide and standard requirements of an open and unified universal server under the OCSP specification are met.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic computers, in particular to a dual-CPU server motherboard. Background Art

[0002] At present, 2U dual-way servers have become important infrastructure for enterprises and data centers due to their high performance, scalability and reliability. However, due to the lack of industry specifications and insufficient communication channels among manufacturers, each server manufacturer's similar server solutions are incompatible with each other, and each has its own dedicated motherboards, chassis, expansion cards, etc. This will undoubtedly bring many problems: one is the high cost of server research and development; the other is the repeated investment and waste caused by the incompatibility of each component. The servers under the OCSP (Open Common Server Platform) specification are designed to create an optimized, open and unified general server design guide and standard, while ensuring sufficient differentiation and customization requirements can be achieved while following this standard. At present, OCSP specification server products based on the IA architecture (Intel Architecture) can be seen everywhere on the market.

[0003] The CPUs of the Shenwei platform can process multiple threads simultaneously and play an important role in the fields of artificial intelligence, big data, etc.

[0004] At present, there is an urgent need to design a dual-CPU server motherboard based on the Shenwei platform according to the OCSP specification to ensure information security and trustworthiness. Summary of the Invention

[0005] Therefore, the purpose of the utility model is to provide a dual-CPU server motherboard, which uses the domestic processor SW6432 to design a dual-CPU server motherboard based on the OCSP specification.

[0006] To achieve the above object, the present utility model provides a dual-way CPU server motherboard, comprising: two SW6432 CPUs, memory slots, two GENZ 4C+ connectors, two Riser cards, a PCIE switch chip, a PCIE-to-USB chip, a USB HUB, a BMC card interface, two solid-state drives, two OCP connectors, and a CPLD; the first SW6432 CPU and the second SW6432 CPU are electrically connected through a DLI high-speed direct connection interface; the memory slots are electrically connected to the first SW6432 CPU or the second SW6432 CPU; the CPLD is electrically connected to the first SW6432 CPU; the first SW6432 CPU is electrically connected to the PCIE switch chip, and the PCIE switch chip is electrically connected to the PCIE-to-USB chip, the first solid-state drive, and the second solid-state drive, and the PCIE-to-USB chip is electrically connected to the USB HUB; the first SW6432 CPU is electrically connected to the first GENZ 4C+ connector, the first Riser card is arranged on the first GENZ 4C+ connector, and the first Riser card is electrically connected to the MCIO connector electrically connected to the first SW6432 CPU through a cable; the second SW6432 CPU is electrically connected to the second GENZ 4C+ connector, the second Riser card is arranged on the second GENZ 4C+ connector, and the second Riser card is electrically connected to the MCIO connector electrically connected to the second SW6432 CPU through a cable; the first OCP connector is electrically connected to the second SW6432 CPU, and the second OCP connector is electrically connected to the Slimline connector; the BMC card interface is electrically connected to the first SW6432 CPU, the CPLD, the PCIE switch chip, and the PCIE-to-USB chip.

[0007] Among them, the number of the memory slots is thirty-two, and the first SW6432 CPU and the second SW6432 CPU are respectively electrically connected to sixteen memory slots.

[0008] Among them, the CPLD is EF3L90CG400B.

[0009] Among them, the PCIE switch chip is ASM2824.

[0010] Among them, the PCIE-to-USB chip is VL805.

[0011] Among them, the USB HUB is ASM1074.

[0012] Among them, the size of the server motherboard is the OCSP standard L shape: 427mm X 380mm.

[0013] Among them, the BMC card interface is electrically connected to a BMC card based on the DC-SCM2.0 interface of the OCP standard.

[0014] Among them, the first OCP connector and / or the second OCP connector are electrically connected to a server network card based on the OCP3.0 standard.

[0015] Among them, the USB HUB is electrically connected to four USB interfaces.

[0016] In summary, the dual-CPU server motherboard of the present utility model adopts a domestic processor SW6432 dual-CPU design to complete the server motherboard solution, meeting the design guidelines and standard requirements of open and unified general servers under the OCSP specification. Description of the Drawings

[0017] The following, in conjunction with the drawings, through a detailed description of the specific embodiments of the present utility model, will make the technical solutions and other beneficial effects of the present utility model obvious. In the drawings

[0018] Figure 1 is a circuit block diagram of a preferred embodiment of a dual-CPU server motherboard of the present utility model. Detailed Description of the Embodiments

[0019] Refer to Figure 1 , which is a circuit block diagram of a preferred embodiment of a dual-CPU server motherboard of the present utility model. In this preferred embodiment, the dual-CPU server motherboard of the present utility model includes: two SW6432 CPUs, CPU0 and CPU1, multiple memory slots, two GENZ 4C+ connectors, two Riser cards, a PCIE switch chip, a PCIE-to-USB chip, a USB HUB, a BMC card interface, two solid-state drives, M.2 NVMe SSD0 and M.2 NVMe SSD1, two OCP connectors, OCP0 and OCP1, and a CPLD. The present utility model proposes a server motherboard solution based on the OCSP specification, adopting a domestic processor architecture Shenwei 6432 dual-CPU interconnection design, meeting the design guidelines and standard requirements of open and unified general servers under the OCSP specification. The motherboard size adopts a standard L shape: 427mm X 380mm design. The maximum memory capacity can support 4096GB. In terms of PCIE expansion ports, it supports 8 PCIE4.0 X8 MCIO PCIE device expansion connectors, can support 12 U.2 NVME solid-state drives, and support 24 2.5 SATA / SAS HDD / SSD hard drives.

[0020] CPU0 and CPU1 are electrically connected through a DLI high-speed direct connection interface; in this preferred embodiment, the number of memory slots is thirty-two, and CPU0 and CPU1 are respectively electrically connected to sixteen memory slots. The dual-way SW6432CPUs of CPU0 and CPU1 respectively carry 16 memory slots through the DDR4 memory control bus, and can connect 32 UDIMM, RDIMM, and LRDIMM DDR4 memory modules. The maximum capacity can support 4096GB, greatly improving the server performance. A dual-processor direct connection system is formed through the DLI high-speed direct connection interface, and the two-way peak bandwidth of the full-chip direct connection interface can reach 189GB / s, supporting automatic link training.

[0021] In this preferred embodiment, CPU0 is electrically connected to the first GENZ 4C+ connector, the first Riser card is installed on the first GENZ 4C+ connector, and the first Riser card is electrically connected to the MCIO connector electrically connected to CPU0 via a cable; CPU1 is electrically connected to the second GENZ 4C+ connector, the second Riser card is installed on the second GENZ 4C+ connector, and the second Riser card is electrically connected to the MCIO connector electrically connected to CPU1 via a cable.

[0022] Thus, in terms of the PCIE expansion port, the motherboard can support 8 PCIE4.0 X8 MCIO PCIE device expansion connectors, with strong PCIE expansion capabilities, fully meeting the needs of users. In this preferred embodiment, in terms of PCIE expansion and RIESER cards, 2 GENZ 4C+ connectors are integrated on the motherboard, and 2 Riser cards can be connected. A group of PCIE4.0X8 signals are connected inside the motherboard, and then 2-way X8 signals are connected to the Riser card through the MCIO X8 CABLE line, so that each Riser card supports 3 PCIE X8 slots or supports 1 X8 and 1 X16 slot. The X8 slot is connected to the 8X signal, and the X16 slot is connected to the 16X signal, supporting 6 standard PCIe4.0 expansion slots, thus supporting various RAID cards, IA inference cards, GPU display cards, network cards and other PCIe expansion cards, further improving the I / O performance and meeting the customer's needs for large-capacity data storage, data analysis, data processing, and AI inference cards.

[0023] The CPLD is electrically connected to CPU0; in this preferred embodiment, the CPLD can be EF3L90CG400B. Using the domestic CPLD EF3L90CG400B to communicate with CPU0 and BMC through the I2C and LPC buses can realize a server motherboard design solution with control functions such as timing control, power management, temperature control, fan control, level conversion, hot-swap control, and power indicator lights.

[0024] In this preferred embodiment, the CPU0 is electrically connected to the PCIE switch chip, the PCIE switch chip is electrically connected to the PCIE-to-USB chip, the first solid-state drive SSD0, and the second solid-state drive SSD1, and the PCIE-to-USB chip is electrically connected to the USB HUB; OCP0 is electrically connected to CPU1 to obtain PCIE signals, and OCP1 is electrically connected to the Slimline connector to obtain PCIE signals from other interfaces on the motherboard through the Slimline. The PCIE switch chip can specifically be ASM2824; the PCIE-to-USB chip can specifically be VL805; the USB HUB can specifically be ASM1074.

[0025] In this preferred embodiment, in terms of interface design, a group of PCIE X8 signals are branched out from the CPU0 and connected to the PCIE switch ASM2824, which can expand downward into two groups of PCIE X1, two groups of PCIE X4. One group of PCIE X1 is used to connect the BMC card, and one group is used to connect the PCIE-to-USB device VL805 and expand four USB3.0 interfaces through the USB HUB ASM1074. The two groups of PCIE x4 can be used to connect 2 NVME SSD system disks, meeting the application requirements of the server for system hard disks, USB devices, and BMC. The rear ports of this product expand the OCP0 and OCP1 connectors of the PCIE X8 bus, which can support the connection of a new generation of multi-functional and high-performance OCP3.0 standard server network cards, improving network performance and the convenient hot-plug function.

[0026] The BMC card interface is electrically connected to the CPU0, CPLD, PCIE switch chip, and PCIE-to-USB chip, so that it can support the BMC card interface to be electrically connected to the BMC card based on the OCP standard DC-SCM2.0 interface, and the design of the BMC card based on the OCP standard DC-SCM2.0 interface can be realized, improving the security and stability of the data center.

[0027] In summary, the dual-CPU server motherboard of the present utility model adopts the domestic processor SW6432 dual-CPU design to complete the server motherboard solution, meeting the design guidelines and standard requirements of the open and unified general server under the OCSP specification.

[0028] As described above, for those of ordinary skill in the art, various corresponding changes and deformations can be made according to the technical solution and technical concept of the present utility model, and all these changes and deformations should fall within the protection scope of the appended claims of the present utility model.

Claims

1. A dual-channel CPU server motherboard, characterized in that, Including: Two SW6432 CPUs, memory slots, two GENZ 4C+ connectors, two Riser cards, a PCIE switch chip, a PCIE-to-USB chip, a USB HUB, a BMC card interface, two solid-state drives, two OCP connectors, and a CPLD; The first SW6432 CPU (CPU0) and the second SW6432 CPU (CPU1) are electrically connected through a DLI high-speed direct connection interface; The memory slots are electrically connected to the first SW6432 CPU (CPU0) or the second SW6432 CPU (CPU1); The CPLD is electrically connected to the first SW6432 CPU (CPU0); The first SW6432 CPU (CPU0) is electrically connected to the PCIE switch chip, and the PCIE switch chip is electrically connected to the PCIE-to-USB chip, the first solid-state drive (SSD0), and the second solid-state drive (SSD1), and the PCIE-to-USB chip is electrically connected to the USB HUB; The first SW6432 CPU (CPU0) is electrically connected to the first GENZ 4C+ connector, the first Riser card is provided on the first GENZ 4C+ connector, and the first Riser card is electrically connected to the MCIO connector electrically connected to the first SW6432 CPU (CPU0) via a cable; The second SW6432 CPU (CPU1) is electrically connected to the second GENZ 4C+ connector, the second Riser card is provided on the second GENZ 4C+ connector, and the second Riser card is electrically connected to the MCIO connector electrically connected to the second SW6432 CPU (CPU1) via a cable; The first OCP connector (OCP0) is electrically connected to the second SW6432 CPU (CPU1), and the second OCP connector (OCP1) is electrically connected to the Slimline connector; The BMC card interface is electrically connected to the first SW6432 CPU (CPU0), the CPLD, the PCIE switch chip, and the PCIE-to-USB chip.

2. The dual-CPU server motherboard according to claim 1, characterized in that The number of the memory slots is thirty-two, and the first SW6432 CPU (CPU0) and the second SW6432 CPU (CPU1) are respectively electrically connected to sixteen memory slots.

3. The dual-CPU server motherboard according to claim 1, characterized in that, The CPLD is EF3L90CG400B.

4. The dual-CPU server motherboard according to claim 1, wherein The PCIE switch chip is ASM2824.

5. The dual-CPU server motherboard according to claim 1, wherein The PCIE-to-USB chip is VL805.

6. The dual-CPU server motherboard according to claim 1, wherein The USB HUB is ASM1074.

7. The dual-CPU server motherboard according to claim 1, wherein The size of the server motherboard is in the OCSP standard L shape: 427mm X 380mm.

8. The dual-CPU server motherboard according to claim 1, wherein The BMC card interface is electrically connected to a BMC card based on the OCP standard DC-SCM2.0 interface.

9. The dual-CPU server motherboard according to claim 1, wherein, The first OCP connector (OCP0) and / or the second OCP connector (OCP1) is electrically connected to a server network card based on the OCP3.0 standard.

10. The dual-CPU server motherboard according to claim 1, wherein, The USB HUB is electrically connected to four USB interfaces.

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