Heterojunction cell and photovoltaic module

Abstract

The utility model provides a heterojunction cell and a photovoltaic assembly. The heterojunction cell comprises a substrate; the first transparent conductive layer is positioned on the light incident surface of the substrate; the first electrode is positioned on one side, far away from the substrate, of the first transparent conductive layer; the second transparent conductive layer is positioned on the backlight surface of the substrate; and the second electrode is positioned on one side, far away from the substrate, of the second transparent conductive layer. Wherein the first transparent conductive layer is configured to be an indium-free film layer at least in a partial region; and the second transparent conductive layer is configured to be an indium-free film layer at least in a partial region. Therefore, the indium content in the transparent conductive layer is reduced, and the cost of the HJT battery is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of solar cells, in particular to a heterojunction cell and a photovoltaic module. Background Art

[0002] Solar cells, a new energy technology, are experiencing an unprecedented development trend. Crystalline silicon solar cells have dominated the photovoltaic industry with a market share of more than 90%. With such a huge volume and broad market prospects, crystalline silicon solar cells are also developing continuously. Crystalline silicon solar cell technology has evolved from the traditional low-complexity full-area aluminum back surface field (Al-BSF) to the passivated emitter and back contact (PERC) structure. However, PERC cells still have local metal and silicon contacts, resulting in a low open circuit voltage. Today, crystalline silicon solar cells with carrier-selective passivated contacts (TOPCon cells, HJT (heterojunction) cells) are currently the most promising choice for achieving high conversion efficiency. The highest laboratory efficiency of HJT cells has reached 26.81%, which has certain efficiency advantages over TOPCon cells.

[0003] Due to the poor lateral conductivity of doped amorphous / microcrystalline / nanocrystalline silicon, HJT cells require a transparent conductive oxide layer (TCO) to assist lateral conductivity. The most commonly used transparent conductive oxide is tin oxide-doped indium oxide (ITO). Because it contains indium and its scarcity makes it more expensive, the key issue is to develop indium-reduced HJT cells and reduce their costs.

[0004] Therefore, how to reduce the cost of HJT batteries is a technical problem that needs to be urgently solved by technicians in this field. Utility Model Content

[0005] In order to solve the above problems, the utility model inventor found the cause of the problem through research and development and formed a solution.

[0006] In a first aspect, the utility model provides a HJT battery, the HJT battery comprising:

[0007] substrate;

[0008] A first transparent conductive layer, located on the light incident surface of the substrate; wherein the first transparent conductive layer is configured such that at least a portion of the first transparent conductive layer is an indium-free film layer;

[0009] A first electrode, located on a side of the first transparent conductive layer away from the substrate;

[0010] A second transparent conductive layer is located on the backlight side of the substrate; wherein the second transparent conductive layer is configured to be an indium-free film layer in at least a part of its area;

[0011] The second electrode is located on the side of the second transparent conductive layer away from the substrate.

[0012] Furthermore, in the above-mentioned HJT cell, the first transparent conductive layer and / or the second transparent conductive layer include an indium-free film layer and an indium-containing film layer;

[0013] The indium-free film layer includes at least one layer of zinc oxide-doped film layer;

[0014] The indium-containing film layer includes at least one layer of indium oxide-doped film layer.

[0015] Furthermore, in the above-mentioned HJT cell, the indium-free film layer is located between the indium-containing film layer and the substrate.

[0016] Furthermore, in the above-mentioned HJT cell, the indium-free film layer is arranged on the same layer as the indium-containing film layer, and the indium-free film layer and the indium-containing film layer are alternately arranged.

[0017] Furthermore, in the above-mentioned HJT cell, the first electrode and / or the second electrode are located on the side of the indium-containing film layer away from the substrate.

[0018] Furthermore, in the above-mentioned HJT cell, the indium-containing film layer includes a first indium-containing film layer in the region where the first electrode and / or the second electrode are located, and a second indium-containing film layer outside the region where the first electrode and / or the second electrode are located;

[0019] The concentration of indium-containing substrate in the first indium-containing film layer is greater than the concentration of indium-containing substrate in the second indium-containing film layer; and / or, the carrier mobility of the indium-containing substrate in the first indium-containing film layer is greater than the carrier mobility of the indium-containing substrate in the second indium-containing film layer.

[0020] Furthermore, in the above-mentioned HJT cell, the projection of the first electrode and / or the second electrode on the first indium-containing film layer is located on the side of the first indium-containing film layer facing away from the substrate.

[0021] Furthermore, the above-mentioned HJT cell further includes:

[0022] A first intrinsic amorphous silicon layer and a first doped amorphous silicon layer grown successively in the direction perpendicular to the light incident surface of the substrate and from the inside to the outside; the first doped amorphous silicon layer is a single-layer structure composed of one of hydrogenated amorphous, hydrogenated nanocrystalline, and hydrogenated microcrystalline, or a stacked structure composed of several of them, and the crystallization rate and effective doping concentration of the stacked structure increase successively from the substrate to the direction of the first electrode;

[0023] A second intrinsic amorphous silicon layer and a second doped amorphous silicon layer that are sequentially grown in a direction perpendicular to the backlight surface of the substrate and from the inside to the outside; the second doped amorphous silicon layer is a single-layer structure composed of one of hydrogenated amorphous, hydrogenated nanocrystalline, and hydrogenated microcrystalline, or a stacked structure composed of several of them, and the crystallization rate and effective doping concentration of the stacked structure increase sequentially from the substrate to the second electrode direction.

[0024] Further, the above-mentioned HJT cell further includes:

[0025] An antireflection layer located on the side of the second electrode away from the substrate, and the antireflection layer is a stacked structure formed by magnesium fluoride, titanium oxide, and magnesium fluoride.

[0026] In a second aspect, the present invention provides a photovoltaic module, and the photovoltaic module includes the HJT cell described in any one of the above.

[0027] One or more of the above technical solutions of the present invention have at least one or more of the following beneficial effects:

[0028] When implementing the technical solution of the present invention, when forming the first transparent conductive layer and the second transparent conductive layer on both sides of the substrate, an indium-free film layer is used as the transparent conductive layer in at least some regions, so that the indium content in the transparent conductive layer is reduced, thereby reducing the cost of the HJT cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Referring to the accompanying drawings, the disclosure of the present invention will become easier to understand. It is easy for those skilled in the art to understand that: these drawings are only for illustrative purposes and are not intended to limit the protection scope of the present invention. In addition, the reference numerals in the drawings are used to represent different components, where:

[0030] Figure 1 is a schematic structural diagram of an HJT cell according to the present invention;

[0031] Figure 2 is another schematic structural diagram of an HJT cell according to the present invention;

[0032] Figure 3 is still another schematic structural diagram of an HJT cell according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] To make the above objects, features, and advantages of the present utility model more obvious and understandable, the following will describe the specific embodiments of the present utility model in detail with reference to the accompanying drawings. Many specific details are set forth in the following description to facilitate a full understanding of the present utility model. However, the present utility model can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the present utility model. Therefore, the present utility model is not limited by the specific embodiments disclosed below.

[0034] In the description of the present utility model, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second", etc. may explicitly or implicitly include at least one of such features. In addition, in the present utility model, unless otherwise clearly specified and limited, the terms "connected", "coupled", etc. should be understood in a broad sense. For example, they can be directly connected or indirectly connected through an intermediate medium, and can be the internal connection or the interaction relationship between two elements, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0035] In the description of the present utility model, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present utility model.

[0036] In the present utility model, unless otherwise clearly specified and limited, the first feature being "on" or "under" the second feature can be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over", and "on top of" the second feature can be that the first feature is directly above or obliquely above the second feature, or simply indicates that the first feature has a higher horizontal height than the second feature. The first feature being "below", "beneath", and "underneath" the second feature can be that the first feature is directly below or obliquely below the second feature, or simply indicates that the first feature has a lower horizontal height than the second feature.

[0037] Due to the poor lateral conductivity of doped amorphous / microcrystalline / nanocrystalline silicon in HJT cells, a transparent conductive oxide layer (TCO) is required to assist in lateral conduction. Currently, the commonly used transparent conductive oxide is indium tin oxide (ITO), which contains indium. Due to the scarcity of indium, its price is relatively high. Therefore, developing indium-reduced HJT cells and reducing their cost is the key issue.

[0038] Therefore, to solve the above technical problems, the present utility model provides the following technical solutions:

[0039] Due to the poor lateral conductivity of doped amorphous / microcrystalline / nanocrystalline silicon in HJT cells, a transparent conductive oxide layer (TCO) is required to assist in lateral conduction. Currently, the commonly used transparent conductive oxide is indium tin oxide (ITO), which contains indium. Due to the scarcity of indium, its price is relatively high. Therefore, developing indium-reduced HJT cells and reducing their cost is the key issue.

[0040] Figure 1 is a schematic structural diagram of an HJT cell according to the present utility model. Refer to Figure 1 The HJT cell includes a substrate 1, a first transparent conductive layer 2, a first electrode 3, a second transparent conductive layer 4, and a second electrode 5.

[0041] In a specific implementation process, the substrate 1 can be an N-type substrate 1, which has a light-incident surface and a backlight surface. The first transparent conductive layer 2 and the first electrode 3 are arranged in sequence from the inside out perpendicular to the light-incident surface of the substrate 1. The first transparent conductive layer 2 and the first electrode 3 are arranged in sequence from the inside out perpendicular to the backlight surface of the substrate 1. Here, from the inside out means from the substrate 1 towards the two sides of the cell.

[0042] In a specific implementation process, at least part of the regions of the first transparent conductive layer 2 and the second transparent conductive layer 4 are configured as indium-free film layers a. Here, at least part of the regions being indium-free film layers a means that the entire first transparent conductive layer 2 and the second transparent conductive layer 4 are composed of indium-free film layers a, or they can be jointly composed of indium-free film layers a and indium-containing film layers b. In this way, the indium content in the two transparent conductive layers is reduced, thereby reducing the cost of the HJT cell. Figure 1 Taking the case where the entire first transparent conductive layer 2 and the second transparent conductive layer 4 are composed of indium-free film layers a as an example for explanation. For the indium-free film layer a, it can be one layer or a stack of multiple film layers, and this embodiment does not make specific restrictions.

[0043] Those skilled in the art can understand that the HJT cell further includes: a first intrinsic amorphous silicon layer 6 and a first doped amorphous silicon layer 7 that are sequentially grown in a direction perpendicular to the light incident surface of the substrate 1 and from the inside to the outside; the first doped amorphous silicon layer 7 is a single-layer structure composed of one of hydrogenated amorphous, hydrogenated nanocrystalline, and hydrogenated microcrystalline, or a stacked structure composed of several of them. The crystallization rate and effective doping concentration of the stacked structure increase sequentially from the substrate 1 to the first electrode 3. A second intrinsic amorphous silicon layer 8 and a second doped amorphous silicon layer 9 that are sequentially grown in a direction perpendicular to the backlight surface of the substrate 1 and from the inside to the outside; the second doped amorphous silicon layer 9 is a single-layer structure composed of one of hydrogenated amorphous, hydrogenated nanocrystalline, and hydrogenated microcrystalline, or a stacked structure composed of several of them. The crystallization rate and effective doping concentration of the stacked structure increase sequentially from the substrate 1 to the second electrode 5.

[0044] Figure 1 The preparation process flow of the shown HJT cell is as follows:

[0045] Step 1: Perform a pre-cleaning treatment on the substrate 1, then texture the surface to form a uniformly sized textured surface, then pass through RCA-1 and RCA-2 to clean the organic matter and metal ions on the textured surface, then smooth the surface pyramids, and finally remove the surface oxide layer with hydrofluoric acid.

[0046] Step 2: Use PECVD / HWCVD to sequentially deposit the first intrinsic amorphous silicon layer 6 and the second intrinsic amorphous silicon layer 8 on both sides of the substrate 1. The first intrinsic amorphous silicon layer 6 and the second intrinsic amorphous silicon layer 8 can be single-layer or stacked structures. The deposition order of the two is not specifically limited in this embodiment.

[0047] Step 3: Subsequently, use PECVD / HWCVD to deposit the first doped amorphous silicon layer 7 (microcrystalline carbon oxide silicon μc-SiCxOy:H) and the second doped amorphous silicon layer 9 (microcrystalline carbon oxide silicon μc-SiCxOy:H) again. The first doped amorphous silicon layer 7 and the second doped amorphous silicon layer 9 can also be single-layer or stacked structures. The first doped amorphous silicon layer 7 can be n (phosphorus-doped) type or P (boron-doped) type, and the second doped amorphous silicon layer 9 can be P (boron-doped) type or n (phosphorus-doped) type doping. The doping types of the first doped amorphous silicon layer 7 and the second doped amorphous silicon layer 9 are opposite. The deposition order of the two is not specifically limited in this embodiment.

[0048] Step 4: Then use RPD to deposit the first transparent conductive layer 2 and the second transparent conductive layer 4 based on tin oxide on both sides at low temperature, that is, the two transparent conductive layers are indium-free film layers a, which can be single-layer or multi-layer structures.

[0049] Among them, the indium-free film layer a can be deposited based on SnO₂. When using the RPD method for coating, the main process gas is argon, and appropriate hydrogen and oxygen flow rates are introduced into the RPD chamber to improve the material properties of the SnO₂ film layer. An appropriate hydrogen ratio can increase the contribution of grain boundary scattering to carrier transport and can also perform hydrogen passivation on the defects at the interface of the thin film material. At the same time, this patent uses the water generated by the reaction of hydrogen and oxygen as the source of water vapor, which increases the stability of the process. Specifically, when depositing the first transparent conductive layer 2 and the second transparent conductive layer 4, the proportion of the hydrogen process gas introduced is 0.5%-5%, preferably 0.8%-1.8%. The proportion of oxygen introduced is 10%-50%, preferably 30%-40%.

[0050] Step 5: Prepare the first electrode 3 and the second electrode 5 by screen printing / laser transfer / copper electroplating.

[0051] Step 6: Dry and cure the first electrode 3 and the second electrode 5 under the optimized conditions.

[0052] Among them, the curing conditions are 120-215°C, 5-60 minutes, and in this embodiment, they are 180-210°C, 20-30 minutes.

[0053] In a specific implementation process, taking the indium-free film layer a using SnO₂ as an example, it can be seen from Tables 1 to 3 that when depositing the indium-free film layer a of SnO₂, after using the optimized argon, hydrogen, and oxygen ratios and annealing, the carrier mobility can reach 33 cm² / V·S, which can meet the performance of the transparent conductive layer.

[0054] Among them, Table 1 shows the relevant data of each parameter after the deposition of the SnO₂ indium-free film layer a under different oxygen ratios.

[0055] Table 1

[0056]

[0057] Table 2 shows the relevant data of each parameter after the deposition of the SnO₂ indium-free film layer a under different oxygen ratios and annealing for 20 minutes.

[0058] Table 2

[0059]

[0060] Table 3 shows the relevant data of each parameter after the deposition of the SnO₂ indium-free film layer a under different oxygen ratios and annealing for 45 minutes.

[0061] Table 3

[0062]

[0063] Figure 2Another structural schematic diagram of the HJT cell according to the present utility model is shown in Figure 2 and in combination with Figure 1 , the main difference between this HJT cell and the Figure 1 embodiment shown is that both the first transparent conductive layer 2 and the second transparent conductive layer 4 include an indium-free film layer a and an indium-containing film layer b. Among them, the indium-free film layer a includes at least one layer of zinc oxide-doped film layer; the indium-containing film layer b includes at least one layer of indium oxide-doped film layer. The indium-free film layer a is located between the indium-containing film layer b and the substrate 1. That is to say, the upper and lower stacked structure composed of the indium-free film layer a and the indium-containing film layer b serves as the first transparent conductive layer 2 or the second transparent conductive layer 4.

[0064] Figure 2 The preparation process flow of the HJT cell shown in

[0065] is as follows: Step 11, pre-clean the substrate 1, then texture the surface to form a uniformly sized textured surface, then pass through RCA-1 and RCA-2 to clean the organic matter and metal ions on the textured surface, then round the surface pyramids, and finally remove the surface oxide layer with hydrofluoric acid.

[0066] Step 12, use PECVD / HWCVD to sequentially deposit the first intrinsic amorphous silicon layer 6 and the second intrinsic amorphous silicon layer 8 on both sides of the substrate 1. The first intrinsic amorphous silicon layer 6 and the second intrinsic amorphous silicon layer 8 can be single-layer or stacked structures. The deposition sequence of the two is not specifically limited in this embodiment.

[0067] Step 13, then use PECVD / HWCVD to deposit the first doped amorphous silicon layer 7 (microcrystalline carbon oxide silicon μc-SiCxOy:H) and the second doped amorphous silicon layer 9 (microcrystalline carbon oxide silicon μc-SiCxOy:H). The first doped amorphous silicon layer 7 and the second doped amorphous silicon layer 9 can also be single-layer or stacked structures. The first doped amorphous silicon layer 7 can be n (phosphorus-doped) type or P (boron-doped) type, and the second doped amorphous silicon layer 9 can be P (boron-doped) type or n (phosphorus-doped) type doping. As long as the doping types of the first doped amorphous silicon layer 7 and the second doped amorphous silicon layer 9 are opposite. The deposition sequence of the two is not specifically limited in this embodiment.

[0068] Step 14, then use RPD to deposit an indium-free film layer a based on tin oxide on both sides at low temperature. This indium-free film layer a can be a single-layer or multi-layer structure.

[0069] Step 15, then use a PVD device to prepare an indium-containing film layer b on the indium-free film layer a based on tin oxide on the front and back. This indium-containing film layer b can be a single-layer or multi-layer structure.

[0070] Among them, the indium-free film layer a in step 14 and the indium-containing film layer b in step 15 together constitute the transparent conductive layer. When depositing the indium-free film layer a and the indium-containing film layer b, the deposition can be carried out according to the above gas ratio, which will not be elaborated here.

[0071] Step 16: Prepare the first electrode 3 and the second electrode 5 by screen printing / laser transfer / copper electroplating.

[0072] Step 17: Dry and cure the first electrode 3 and the second electrode 5 according to the optimized conditions.

[0073] Figure 3 It is another structural schematic diagram of the HJT battery according to the present invention. Refer to Figure 3 and in combination with Figure 2 , the difference between this HJT battery and the Figure 2 illustrated embodiment is mainly that the indium-free film layer a and the indium-containing film layer b are alternately arranged in the same layer instead of being stacked one above the other.

[0074] In a specific implementation process, in order to enable the HJT battery to have better conductivity, the first electrode 3 and / or the second electrode 5 is arranged on the side of the indium-containing film layer b away from the substrate 1 and is in contact with the indium-containing film layer b. In this way, while reducing indium, the performance of the HJT battery can be ensured as much as possible.

[0075] In a specific implementation process, as Figure 3 shown, the indium-containing film layer b may include a first indium-containing film layer b11 and a second indium-containing film layer b22. Among them, the first indium-containing film layer b1 is the film layer in the area where the first electrode 3 and / or the second electrode 5 is located, and the second indium-containing film layer b2 is the film layer outside the area where the first electrode 3 and / or the second electrode 5 is located.

[0076] In order to further reduce indium, on the premise that the concentration of the indium-containing substrate in the first indium-containing film layer b1 meets the electrical conductivity requirements, the concentration of the indium-containing substrate in the second indium-containing film layer b2 can be reduced. That is to say, the concentration of the indium-containing substrate in the first indium-containing film layer b1 is greater than the concentration of the indium-containing substrate in the second indium-containing film layer b2. And / or, the indium-containing substrate in the first indium-containing film layer b1 is selected from materials with a high carrier mobility, while the indium-containing substrate in the second indium-containing film layer b2 is selected from materials with a low carrier mobility. That is to say, the carrier mobility of the indium-containing substrate in the first indium-containing film layer b1 is greater than the carrier mobility of the indium-containing substrate in the second indium-containing film layer b2. For example, the indium-containing substrate in the second indium-containing film layer b2 can be ITO, while the indium-containing substrate in the first indium-containing film layer can be indium oxide doped with tungsten, cerium, molybdenum, zirconium, titanium, hafnium, zinc, manganese, etc. This can not only take into account the work function matching to reduce the matching between the N-side microcrystalline layer or amorphous layer and the transparent conductive layer, but also reduce the contact resistance between the transparent conductive layer and the electrode, which can improve the fill factor of the battery and increase the conversion efficiency of the battery in terms of battery performance. At the same time, this transparent conductive layer structure can also take into account a certain cost reduction and has a certain economy.

[0077] In a specific implementation process, the projection of the first electrode 3 and / or the second electrode 5 on the first indium-containing film layer b1 is located on the side of the first indium-containing film layer b1 facing away from the substrate 1. That is to say, the width of the first electrode 3 and / or the second electrode 5 is smaller than the width of the first indium-containing film layer b1.

[0078] In a specific implementation process, as Figure 3 shown, the HJT battery may further include an antireflection layer on the side of the second electrode 5 away from the substrate 1, and the antireflection layer is a stacked structure formed by magnesium fluoride, titanium oxide, and magnesium fluoride.

[0079] Figure 3 The preparation process flow of the HJT battery shown is as follows:

[0080] Step 21: Perform a pre-cleaning treatment on the substrate 1, then texture the surface to form a uniformly sized textured surface, then pass through RCA-1 and RCA-2 to clean the organic matter and metal ions on the textured surface, then smooth the structure of the surface pyramid, and finally remove the surface oxide layer with hydrofluoric acid.

[0081] Step 22: Use PECVD / HWCVD to sequentially deposit the first intrinsic amorphous silicon layer 6 and the second intrinsic amorphous silicon layer 8 on both sides of the substrate 1, where the first intrinsic amorphous silicon layer 6 and the second intrinsic amorphous silicon layer 8 can be single-layer or stacked structures. The deposition order of the two is not specifically limited in this embodiment.

[0082] Step 23: Subsequently, use PECVD / HWCVD to redeposit the first doped amorphous silicon layer 7 (microcrystalline silicon carbon oxide μc-SiCxOy:H) and the second doped amorphous silicon layer 9 (microcrystalline silicon carbon oxide μc-SiCxOy:H). The first doped amorphous silicon layer 7 and the second doped amorphous silicon layer 9 can also be single-layer or stacked structures. The first doped amorphous silicon layer 7 can be n (phosphorus-doped) type or P (boron-doped) type, and the second doped amorphous silicon layer 9 can be P (boron-doped) type or n (phosphorus-doped) type doping. It is only necessary that the doping types of the first doped amorphous silicon layer 7 and the second doped amorphous silicon layer 9 are opposite. The deposition sequence of the two is not specifically limited in this embodiment.

[0083] Step 24: Then, use RPD and a patterned mask plate to sequentially deposit a doped indium film layer b based on indium oxide as the main material (including but not limited to tungsten, cerium, silver, zirconium, titanium, hafnium, zinc, manganese-doped indium oxide) on the front and back at low temperature. The patterned doped indium film layer b can be a single-layer structure or a stacked structure. Then, use RPD and another patterned mask plate to deposit an indium-free film layer a on the front and back, such as indium tin oxide film or doped indium tin oxide film (the doping materials are not limited to tantalum, antimony, niobium, tungsten, silver, zirconium, titanium, zinc, manganese, etc.). Among them, the width of the doped indium film layer b based on indium oxide as the main material is not less than the width of the metal gate line (electrode).

[0084] Among them, when depositing the indium-free film layer a and the doped indium film layer b, the deposition can be carried out according to the above gas ratio, which will not be elaborated here.

[0085] Step 25: Then, prepare the first electrode 3 and the second electrode 5 by screen printing / stencil printing / laser transfer / copper electroplating.

[0086] Step 26: Then, use an evaporation device and a patterned mask plate that can cover the main grid to deposit a magnesium fluoride / titanium oxide / magnesium fluoride three-layer "sandwich" structure anti-reflection film on the back of the mixed transparent conductive layer.

[0087] Step 27: Finally, perform the light injection operation on the HJT battery.

[0088] Furthermore, the present utility model also provides a photovoltaic module, which includes the HJT battery of the above embodiment.

[0089] So far, the technical solution of the present utility model has been described in combination with the preferred embodiments shown in the drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present utility model is obviously not limited to these specific embodiments. Without departing from the principle of the present utility model, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the protection scope of the present utility model.

Claims

1. A heterojunction battery, characterized in that, Comprising: A substrate; A first transparent conductive layer located on the light incident surface of the substrate; wherein, at least part of the first transparent conductive layer is configured as an indium-free film layer; A first electrode located on the side of the first transparent conductive layer away from the substrate; A second transparent conductive layer located on the backlight surface of the substrate; wherein, at least part of the second transparent conductive layer is configured as an indium-free film layer; A second electrode located on the side of the second transparent conductive layer away from the substrate; Wherein, the first transparent conductive layer and / or the second transparent conductive layer only includes an indium-free film layer; or, The first transparent conductive layer and / or the second transparent conductive layer includes the indium-free film layer and an indium-containing film layer, and the indium-free film layer and the indium-containing film layer are arranged in the same layer.

2. The heterojunction cell according to claim 1, wherein The indium-free film layer includes at least one layer of indium-doped zinc oxide film layer; The indium-containing film layer includes at least one layer of indium-doped indium oxide film layer.

3. The heterojunction battery according to claim 2, characterized in that, The indium-free film layer and the indium-containing film layer are arranged alternately.

4. The heterojunction cell according to claim 3, wherein The first electrode and / or the second electrode is located on the side of the indium-containing film layer away from the substrate.

5. The heterojunction battery according to claim 4, characterized in that, The indium-containing film layer includes a first indium-containing film layer in the region where the first electrode and / or the second electrode is located, and a second indium-containing film layer outside the region where the first electrode and / or the second electrode is located; The concentration of indium-containing substrate in the first indium-containing film layer is greater than the concentration of indium-containing substrate in the second indium-containing film layer; and / or, the carrier mobility of the indium-containing substrate in the first indium-containing film layer is greater than the carrier mobility of the indium-containing substrate in the second indium-containing film layer.

6. The heterojunction battery according to claim 4, wherein, The projection of the first electrode and / or the second electrode on the first indium-containing film layer is located in the side of the first indium-containing film layer facing away from the substrate.

7. The heterojunction battery according to any one of claims 1 to 6, characterized in that, Further comprising: A first intrinsic amorphous silicon layer and a first doped amorphous silicon layer grown in sequence in a direction perpendicular to the light incident surface of the substrate and from inside to outside; the first doped amorphous silicon layer is a single-layer structure composed of one of hydrogenated amorphous, hydrogenated nanocrystalline, and hydrogenated microcrystalline, or a stacked structure composed of several of them, and the crystallization rate and effective doping concentration of the stacked structure increase in sequence from the substrate to the first electrode direction; A second intrinsic amorphous silicon layer and a second doped amorphous silicon layer grown in sequence in a direction perpendicular to the backlight surface of the substrate and from inside to outside; the second doped amorphous silicon layer is a single-layer structure composed of one of hydrogenated amorphous, hydrogenated nanocrystalline, and hydrogenated microcrystalline, or a stacked structure composed of several of them, and the crystallization rate and effective doping concentration of the stacked structure increase in sequence from the substrate to the second electrode direction.

8. The heterojunction battery according to claim 7, characterized in that, Further comprising: An antireflection layer located on the side of the second electrode away from the substrate, and the antireflection layer is a stacked structure formed by magnesium fluoride, titanium oxide, and magnesium fluoride.

9. A photovoltaic module, characterized in that, Comprising the heterojunction cell according to any one of claims 1 to 8.

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