Digital-analog hybrid chip function test system
Through the combination of analog test units and digital signal generation units, high voltage, high current and digital timing signals are provided, which solves the cost of existing digital-to-analog hybrid test systems and realizes high-precision and low-cost chip functional testing.
Patent Information
- Application Number
- CN202421347723.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-13
- Publication Date
- 2025-07-22
- Estimated Expiration
- 2034-06-13
AI Technical Summary
The existing digital-to-analog hybrid testing system is expensive, resulting in increased chip functional testing costs.
Using a combination of analog test unit, digital signal generation unit and analog switch unit, high voltage and high current testing conditions are provided through the analog test unit, and digital timing signals are output through the digital signal generation unit to realize digital-analog hybrid chip functional testing.
High-precision chip functional testing is achieved while reducing testing costs.
Smart Images
Figure CN223139768U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of chip testing, and in particular, to a functional testing system for a digital-analog hybrid chip. Background Art
[0002] Chip functional testing is an important part of chip testing, mainly verifying whether the chip has implemented the specified functions according to the design specifications to ensure the normal function and stable performance of the chip. Chip functional testing includes testing the input-output function, timing, level characteristics, functional logic, etc. of the chip.
[0003] Currently, existing digital-analog hybrid testing systems can implement chip functional testing. However, the existing digital-analog hybrid testing systems are expensive, which will lead to an increase in the cost of chip functional testing. Summary of the Invention
[0004] In order to help solve the problem that the existing digital-analog hybrid testing system is expensive, resulting in an increase in the cost of chip functional testing, a functional testing system for a digital-analog hybrid chip provided by the present application adopts the following technical solutions: It includes an analog testing unit, a digital signal generation unit, an analog switch unit, and a unit under test;
[0005] The analog testing unit is used to provide a level signal and a test signal to test the unit under test;
[0006] The digital signal generation unit is connected to the analog testing unit, and is used to receive the level signal and output a digital timing signal, a control signal, and a 5V voltage;
[0007] The analog switch unit is connected to the digital signal generation unit, and is used to receive the control signal and the 5V voltage, and control the on-off between the digital signal generation unit and the unit under test according to the control signal;
[0008] The unit under test is connected to the analog switch unit and the analog testing unit, and is used to receive the test signal and the digital timing signal, and perform tests according to the digital timing signal and the test signal.
[0009] Through the above technical solutions, the analog testing unit can provide test conditions with high voltage and large current, and the test accuracy is relatively high. However, it is difficult for the analog testing unit to provide a digital timing signal. Through the digital signal generation unit, a digital timing signal is output according to the voltage signal provided by the analog testing unit, so that the problem of difficult to provide a digital timing signal can be solved. Chip functional testing is realized in the form of digital-analog combination. Compared with the existing digital-analog hybrid testing system, the test cost can be reduced as much as possible, and at the same time, high-precision testing of chip functions can be realized.
[0010] In a specific feasible implementation, the control signal includes on and off;
[0011] When the control signal is on, the digital signal generating unit is connected to the unit under test, and the digital timing signal is transmitted to the unit under test;
[0012] When the control signal is off, the digital signal generating unit is disconnected from the unit under test, and the digital timing signal is not transmitted to the unit under test.
[0013] In a specific feasible implementation, the analog test unit is an analog test system, and the model of the analog test system is STS8200.
[0014] In a specific feasible implementation, the digital signal generating unit is an FPGA development board, and the model of the FPGA development board is ATK-DF7010 / 7020P.
[0015] In a specific feasible implementation, the interfaces BUSY1 and BUSY2 of the FPGA development board receive the level signal, and the interface IN outputs the control signal;
[0016] The 5V interface of the FPGA development board outputs 5V voltage, and the interface GND provides ground;
[0017] The interfaces CH1, CH2, CH3, and CH4 of the FPGA development board output the digital timing signal.
[0018] In a specific feasible implementation, the digital timing signal includes a first digital timing signal, a second digital timing signal, a third digital timing signal, and a fourth digital timing signal, and the analog switch unit includes analog switches SW1, SW2, SW3, and SW4;
[0019] The first digital timing signal, the second digital timing signal, the third digital timing signal, and the fourth digital timing signal are respectively controlled by the analog switches SW1, SW2, SW3, and SW4.
[0020] In a specific feasible implementation, the pin 6 of the analog switch SW1 receives the control signal, the pin 5 receives the 5V voltage, the pin 4 receives the first digital timing signal, the pin 2 is grounded, and the pin 1 outputs the first digital timing signal;
[0021] The pin 6 of the analog switch SW2 receives the control signal, the pin 5 receives the 5V voltage, the pin 4 receives the second digital timing signal, the pin 2 is grounded, and the pin 1 outputs the second digital timing signal;
[0022] Pin 6 of the analog switch SW3 receives the control signal, pin 5 receives the 5V voltage, pin 4 receives the third digital timing signal, pin 2 is grounded, and pin 1 outputs the third digital timing signal;
[0023] Pin 6 of the analog switch SW4 receives the control signal, pin 5 receives the 5V voltage, pin 4 receives the fourth digital timing signal, pin 2 is grounded, and pin 1 outputs the fourth digital timing signal.
[0024] In a specific feasible implementation, the models of the analog switch SW1, the analog switch SW2, the analog switch SW3, and the analog switch SW4 are all RS2057XH.
[0025] In a specific feasible implementation, the unit under test is the chip under test IC.
[0026] In a specific feasible implementation, the digital timing signal includes a first digital timing signal, a second digital timing signal, a third digital timing signal, and a fourth digital timing signal;
[0027] Pin 1 of the chip under test IC is connected to the power supply VDD and is connected to the analog test unit, and pin 8 is grounded;
[0028] Pin 3 and pin 6 of the chip under test IC are respectively connected to the analog test unit;
[0029] Pin 2 of the chip under test IC receives the first digital timing signal and the test signal; pin 4 of the chip under test IC receives the second digital timing signal and the test signal; pin 5 of the chip under test IC receives the third digital timing signal and the test signal; pin 7 of the chip under test IC receives the fourth digital timing signal and the test signal.
[0030] In summary, the present application has the following beneficial technical effects:
[0031] The analog test unit can provide test conditions of high voltage and large current, and the test accuracy is relatively high. However, it is difficult for the analog test unit to provide digital timing signals; through the digital signal generation unit, digital timing signals are output according to the voltage signals provided by the analog test unit, so that the problem of difficult to provide digital timing signals can be solved, and the chip function test is realized in the form of combining digital and analog. Compared with the existing digital-analog hybrid test system, the test cost can be reduced as much as possible, and the high-precision test of the chip function can be realized at the same time. Description of the Drawings
[0032] Figure 1It is the circuit diagram of the digital - analog hybrid chip function test system in the embodiment of the present application;
[0033] Figure 2 It is the schematic diagram of the test process of the digital - analog hybrid chip function test system in the embodiment of the present application.
[0034] Reference numerals: 100, analog test unit; 200, digital signal generation unit; 300, analog switch unit; 400, unit under test. Detailed implementation manners
[0035] The following will further describe the present application in detail Figure 1 with reference to the accompanying drawings.
[0036] The embodiment of the present application discloses a digital - analog hybrid chip function test system. By using this chip function test system, a digital - analog hybrid test method can be realized. Chip function test is an important part of chip testing, mainly to verify whether the chip has implemented the specified functions according to the design specifications to ensure the normal function and stable performance of the chip. Chip function test includes testing the input - output function, timing, level characteristics, functional logic, etc. of the chip.
[0037] Currently, the existing test systems include pure - digital test systems, pure - analog test systems, and digital - analog hybrid test systems. However, the pure - digital test system has relatively low test accuracy for current and voltage, and cannot provide test conditions of high voltage and large current; although the pure - analog test system can provide test conditions of high voltage and large current and has relatively high test accuracy, its ability to provide digital timing for digital - analog chips is relatively weak; the digital - analog hybrid test system can realize chip function test, but the existing digital - analog hybrid test systems are expensive, which will increase the cost of chip function test. In order to help improve the accuracy of chip function test and reduce the test cost, the present application provides a digital - analog hybrid chip function test system.
[0038] Referring to Figure 1 , the digital - analog hybrid chip function test system includes:
[0039] An analog test unit 100, a digital signal generation unit 200, an analog switch unit 300, and a unit under test 400; the analog test unit 100 is used to provide a level signal and a test signal to test the unit under test 400. The analog test unit 100 is an analog test system, and the model of the analog test system is STS8200. The digital signal generation unit 200 is connected to the analog test unit 100 and is used to receive the level signal and output a digital timing signal, a control signal, and a 5V voltage; the analog switch unit 300 is connected to the digital signal generation unit 200 and is used to receive the control signal and the 5V voltage, and control the on / off between the digital signal generation unit 200 and the unit under test 400 according to the control signal; the unit under test 400 is connected to the analog switch unit 300 and the analog test unit 100 and is used to receive the test signal and the digital timing signal and perform tests according to the digital timing signal and the test signal; wherein, the control signal includes on and off. When the control signal is on, the digital signal generation unit 200 is connected to the unit under test 400, and the digital timing signal is transmitted to the unit under test 400; when the control signal is off, the digital signal generation unit 200 is disconnected from the unit under test 400, and the digital timing signal is not transmitted to the unit under test 400.
[0040] The digital signal generation unit 200 is an FPGA development board, and its model is ATK-DF7010 / 7020P. The interface BUSY1 and interface BUSY2 of the FPGA development board receive the level signal, and the interface IN outputs the control signal; the 5V interface of the FPGA development board outputs a 5V voltage, and the interface GND provides a ground; the interfaces CH1, CH2, CH3, and CH4 of the FPGA development board output the digital timing signal.
[0041] The digital timing signal includes a first digital timing signal, a second digital timing signal, a third digital timing signal, and a fourth digital timing signal. The analog switch unit 300 includes an analog switch SW1, an analog switch SW2, an analog switch SW3, and an analog switch SW4; the first digital timing signal, the second digital timing signal, the third digital timing signal, and the fourth digital timing signal are respectively controlled by the analog switch SW1, the analog switch SW2, the analog switch SW3, and the analog switch SW4; the models of the analog switch SW1, the analog switch SW2, the analog switch SW3, and the analog switch SW4 are all RS2057XH.
[0042] Pin 6 of analog switch SW1 receives a control signal, pin 5 receives a 5V voltage, pin 4 receives a first digital timing signal, pin 2 is grounded, and pin 1 outputs a first digital timing signal; pin 6 of analog switch SW2 receives a control signal, pin 5 receives a 5V voltage, pin 4 receives a second digital timing signal, pin 2 is grounded, and pin 1 outputs a second digital timing signal; pin 6 of analog switch SW3 receives a control signal, pin 5 receives a 5V voltage, pin 4 receives a third digital timing signal, pin 2 is grounded, and pin 1 outputs a third digital timing signal; pin 6 of analog switch SW4 receives a control signal, pin 5 receives a 5V voltage, pin 4 receives a fourth digital timing signal, pin 2 is grounded, and pin 1 outputs a fourth digital timing signal.
[0043] The unit under test 400 is the chip under test IC; pin 1 of the chip under test IC is connected to the power supply VDD and is also connected to the analog test unit, and pin 8 is grounded; pin 3 and pin 6 of the chip under test IC are respectively connected to the analog test unit; pin 2 of the chip under test IC receives a first digital timing signal and a test signal; pin 4 of the chip under test IC receives a second digital timing signal and a test signal; pin 5 of the chip under test IC receives a third digital timing signal and a test signal; pin 7 of the chip under test IC receives a fourth digital timing signal and a test signal.
[0044] The implementation principle of the embodiments of this application is as follows:
[0045] The test system in the embodiments of this application uses an analog test system STS8200. The digital signal generation unit is an FPGA digital signal generation module, which can also be understood as an FPGA development board, and its model is ATK-DF7010 / 7020P. Combining Figure 1 and Figure 2 , the analog test system provides high and low level signals for the BUSY1 and BUSY2 pins of the FPGA digital signal generation module. There are a total of four different signals, namely 00, 01, 10, and 11.
[0046] When the BUSY1 and BUSY2 ports of the FPGA digital signal generation module receive high and low levels, the opening and closing states of the analog switch are controlled through the IN port. When a high level is given to the IN port, the analog switch closes, and the chip under test IC is connected to the FPGA digital signal generation module. The FPGA digital signal generation module provides different digital timing signals to the chip under test IC according to the different signals received.
[0047] After the FPGA digital signal generation module finishes providing digital timing signals to the chip under test IC, the test system will provide test conditions such as high voltage or large current to the chip under test IC for high-precision chip function testing to achieve digital-analog hybrid chip function testing.
[0048] This specific embodiment is only an interpretation of the present invention and is not a limitation thereof. After reading this specification, those skilled in the art may make modifications to this embodiment that do not contribute creatively as needed, but as long as they are within the scope of the claims of the present invention, they are protected by the patent law.
Claims
1. A digital-analog hybrid chip function test system, characterized in that: It includes an analog test unit, a digital signal generation unit, an analog switch unit, and a unit under test; The analog test unit is used to provide a level signal and a test signal to test the unit under test; The digital signal generation unit is connected to the analog test unit and is used to receive the level signal and output a digital timing signal, a control signal, and a 5V voltage; The analog switch unit is connected to the digital signal generation unit and is used to receive the control signal and the 5V voltage, and control the connection and disconnection between the digital signal generation unit and the unit under test according to the control signal; The unit under test is connected to the analog switch unit and the analog test unit and is used to receive the test signal and the digital timing signal and perform tests according to the digital timing signal and the test signal.
2. The digital-analog hybrid chip function test system according to claim 1, wherein: The control signal includes on and off; When the control signal is on, the digital signal generation unit is connected to the unit under test, and the digital timing signal is transmitted to the unit under test; When the control signal is off, the digital signal generation unit is disconnected from the unit under test, and the digital timing signal is not transmitted to the unit under test.
3. The digital-analog hybrid chip function test system according to claim 1, wherein: The analog test unit is an analog test system, and the model of the analog test system is STS8200.
4. The digital-analog hybrid chip function test system according to claim 1, wherein: The digital signal generation unit is an FPGA development board, and the model of the FPGA development board is ATK-DF7010 / 7020P.
5. The digital-analog hybrid chip function test system according to claim 4, wherein: The interface BUSY1 and interface BUSY2 of the FPGA development board receive the level signal, and the interface IN outputs the control signal; The 5V interface of the FPGA development board outputs a 5V voltage, and the interface GND provides a ground; The interfaces CH1, CH2, CH3, and CH4 of the FPGA development board output the digital timing signal.
6. The digital-analog hybrid chip function test system according to claim 1, wherein: The digital timing signal includes a first digital timing signal, a second digital timing signal, a third digital timing signal, and a fourth digital timing signal, and the analog switch unit includes analog switches SW1, SW2, SW3, and SW4; The first digital timing signal, the second digital timing signal, the third digital timing signal, and the fourth digital timing signal are respectively controlled by the analog switches SW1, SW2, SW3, and SW4.
7. The digital-analog hybrid chip function test system according to claim 6, wherein: Pin 6 of the analog switch SW1 receives the control signal, pin 5 receives the 5V voltage, pin 4 receives the first digital timing signal, pin 2 is grounded, and pin 1 outputs the first digital timing signal; Pin 6 of the analog switch SW2 receives the control signal, pin 5 receives the 5V voltage, pin 4 receives the second digital timing signal, pin 2 is grounded, and pin 1 outputs the second digital timing signal; Pin 6 of the analog switch SW3 receives the control signal, pin 5 receives the 5V voltage, pin 4 receives the third digital timing signal, pin 2 is grounded, and pin 1 outputs the third digital timing signal; Pin 6 of the analog switch SW4 receives the control signal, pin 5 receives the 5V voltage, pin 4 receives the fourth digital timing signal, pin 2 is grounded, and pin 1 outputs the fourth digital timing signal.
8. The digital-analog hybrid chip function test system according to claim 6, wherein: The models of the analog switch SW1, the analog switch SW2, the analog switch SW3, and the analog switch SW4 are all RS2057XH.
9. The digital-analog hybrid chip function test system according to claim 1, wherein: The unit under test is the chip under test IC.
10. The digital-analog hybrid chip function test system according to claim 9, characterized in that: The digital timing signal includes a first digital timing signal, a second digital timing signal, a third digital timing signal, and a fourth digital timing signal; Pin 1 of the chip under test IC is connected to the power supply VDD and is connected to the analog test unit, and pin 8 is grounded; Pin 3 and pin 6 of the chip under test IC are respectively connected to the analog test unit; Pin 2 of the chip under test IC receives the first digital timing signal and the test signal; pin 4 of the chip under test IC receives the second digital timing signal and the test signal; pin 5 of the chip under test IC receives the third digital timing signal and the test signal; pin 7 of the chip under test IC receives the fourth digital timing signal and the test signal.