Apparatus for controlling sleep mode of system

Abstract

The utility model discloses a device for controlling a sleep mode of a system, comprising a control unit which is coupled to a first group of peripherals of the system and a second group of peripherals different from the first group of peripherals; the power supply module is coupled between the control unit and the second group of peripherals, the control unit is configured to control the power supply module to supply power to the second group of peripherals, and the power supply module is further configured to enter a first low-power-consumption mode by controlling the second group of peripherals, and the power supply module is configured to supply power to the second group of peripherals by controlling the second group of peripherals to enter a second low-power-consumption mode by controlling the second group of peripherals. And enabling the first group of peripherals and the system to enter a second low power consumption mode and a sleep mode respectively. According to the device for controlling the sleep mode of the system, the system can still enter the S0I3 mode under the condition that the system has PCIe peripheral equipment which does not support D3hot or D3cold, so that the device has shorter recovery delay and better user experience.

Description

Technical Field

[0001] The present utility model generally relates to system power management technology, and more specifically, to a device for controlling the sleep mode of a system. Background Art

[0002] Currently commercially available laptop computers generally support two sleep modes, namely, S3 mode (Suspend to RAM) and S0I3 mode. In S3 mode, the system continues to power the memory to ensure data is not lost, while other peripherals (such as hard disks, screens, WiFi, Bluetooth, etc.) are in a powered-off state. When the system wakes up from S3 mode, all peripherals need to be powered on again and initialized, and then the instructions stored in the memory before entering the sleep mode are continued to be executed. Since waking up from S3 mode requires powering on and initializing all peripherals, the recovery time is relatively long. To shorten the system's recovery latency, recent laptop computers also support S0I3 mode. In this mode, the CPU and all peripherals enter a low-power mode instead of being completely powered off, so the S0I3 mode has a shorter recovery latency. However, the prerequisite for a laptop computer to enter S0I3 mode is that all PCIe peripherals connected to the PCIe slots in its CPU can enter the low-power mode defined by PCIe, namely D3hot or D3cold. Whether the PCIe peripheral enters D3hot or D3cold, the PCIe link will enter a low-power link state. That is to say, the prerequisite for the system to enter S0I3 mode is that all PCIe links can enter the low-power link state.

[0003] However, for some old PCIe peripherals, they do not support D3hot or D3cold, which will cause their PCIe links not to enter the low-power link state, resulting in the system being unable to enter S0I3 mode and only being able to enter S3 mode. For example, assume that a laptop computer's PCIe slot is connected to 10 PCIe peripherals and 9 of them support D3hot or D3cold, but as long as one PCIe peripheral does not support D3hot or D3cold, it will also cause the system not to be able to enter S0I3 mode but only S3 mode when entering the sleep mode, and thus the system has a long recovery latency.

[0004] Therefore, a device for controlling the sleep mode of a system is needed, which can enable the system to still enter S0I3 mode when there are PCIe peripherals that do not support D3hot or D3cold in the system for various reasons (such as cost savings), so as to have a shorter recovery latency and a better user experience. Summary of the Utility Model

[0005] According to an embodiment of the present invention, a device for controlling the sleep mode of a system is provided, including: a control unit, the control unit being coupled to a first set of peripherals of the system and a second set of peripherals different from the first set of peripherals; and a power supply module, the power supply module being coupled between the control unit and the second set of peripherals, the control unit being configured to control the power supply module to supply power to the second set of peripherals, characterized in that the control unit is further configured to make the first set of peripherals and the system enter a second low-power mode and a sleep mode respectively by controlling the second set of peripherals to enter a first low-power mode.

[0006] In some embodiments, the first set of peripherals and the second set of peripherals include PCIe peripherals.

[0007] In some embodiments, the first set of peripherals includes PCIe peripherals that support D3hot or D3cold modes defined based on PCIe, and the second set of peripherals includes PCIe peripherals that do not support D3hot or D3cold modes defined based on PCIe.

[0008] In some embodiments, the sleep mode includes the S0I3 mode.

[0009] In some embodiments, the first set of peripherals entering the second low-power mode includes the first set of peripherals entering the D3hot or D3cold mode, and the second set of peripherals entering the first low-power mode includes turning off the power supply module to stop supplying power to the second set of peripherals.

[0010] In some embodiments, the control unit is further configured to control the first set of peripherals to resume normal operation from the D3hot or D3cold mode, the second set of peripherals to resume normal power supply operation, and the system to wake up from the S0I3 mode.

[0011] In some embodiments, the control unit includes a determination unit, the determination unit being configured to determine whether the PCIe links corresponding to the first set of peripherals and the second set of peripherals enter a low-power link state.

[0012] In some embodiments, when the second set of peripherals includes multiple peripherals, the power supply module includes multiple sub-power supply modules, and each of the multiple peripherals is coupled to one of the multiple sub-power supply modules.

[0013] In some embodiments, the system includes any one of a notebook, a desktop computer, a netbook, a vehicle-mounted system, and a set-top box.

[0014] In some embodiments, the first set of peripheral devices and the second set of peripheral devices each include one or more of a graphics card, a network card, a sound card, a memory card, an acceleration card, and Bluetooth. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings are incorporated herein and form a part of the specification, illustrating embodiments of the present invention and, together with the specification, further serving to explain the principles of the present invention and enabling those skilled in the relevant art to make and use the present invention.

[0016] Figure 1 FIG. shows a schematic diagram of a device for controlling the sleep mode of a laptop computer according to an embodiment of the present invention; and

[0017] Figure 2 FIG. shows a schematic diagram of a device for controlling the sleep mode of a laptop computer according to another embodiment of the present invention.

[0018] The embodiments will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0019] The subject matter described herein will now be discussed with reference to example embodiments. It should be understood that the discussion of these embodiments is only to enable those skilled in the art to better understand and thus implement the subject matter described herein, and is not a limitation on the scope of protection, applicability, or examples set forth in the claims. Changes may be made to the functions and arrangements of the elements discussed without departing from the scope of protection of the content of this specification. Each example may omit, substitute, or add various processes or components as needed. Additionally, the features described relative to some examples may be combined in other examples.

[0020] It should be noted that the mention of "an embodiment", "embodiments", "some embodiments", etc. in the specification means that the described embodiments may include specific features, structures, or characteristics, but not necessarily every embodiment includes such specific features, structures, or characteristics. Moreover, such wording does not necessarily refer to the same embodiment. Additionally, when combining specific features, structures, or characteristics with an embodiment, implementing such features, structures, or characteristics in combination with other embodiments, whether explicitly or implicitly described, should be within the knowledge scope of those skilled in the relevant art.

[0021] The embodiments herein may be described with reference to the accompanying drawings. Unless explicitly stated, the dimensions of the drawings are intended to simplify the examples rather than describe relative dimensions. For example, unless otherwise indicated, the various lengths / widths / heights of the elements in the drawings may not be drawn to scale.

[0022] Embodiments of a device for controlling the sleep mode of a system according to the present invention will now be described with reference to the accompanying drawings.

[0023] Figure 1 FIG. 2 shows a schematic diagram of a device 100 for controlling the sleep mode of a notebook computer according to an embodiment of the present invention. As Figure 1 shown, the device 100 includes a control unit 101 and a voltage regulator 102, and an S3 logic unit 103 is integrated on the control unit 101. The S3 logic unit 103 is coupled to the voltage regulator 102 via a first pin (e.g., the SLP S3 pin), and the voltage regulator 102 is coupled to each of (e.g.) three PCIe peripherals 104-1, 104-2, and 104-3 connected through a PCIe slot in the notebook computer CPU. As Figure 1 shown, the S3 logic unit 103 is further configured to be coupled to each of the three PCIe peripherals 104-1, 104-2, and 104-3 via a second pin (e.g., the PlatformResetPin pin). In Figure 1 the embodiment shown, the control unit 101 may be implemented as the CPU of the notebook computer. In some embodiments, the control unit 101 may also be implemented as a part of the CPU of the notebook computer or a component separate from the notebook computer CPU.

[0024] As Figure 1 shown, only three PCIe peripherals 104-1, 104-2, and 104-3 are shown as examples, but the number of PCIe peripherals is not limited thereto. In some embodiments, the three PCIe peripherals 104-1, 104-2, and 104-3 may be, for example, any one of a graphics card, a network card, a sound card, a memory card, an acceleration card, and Bluetooth, but the present invention is not limited thereto. In Figure 1 the embodiment shown, the peripheral 104-2 does not support D3hot or D3cold. In this case, when the notebook computer enters the sleep mode, the control unit 101 (e.g., the CPU of the notebook computer) will not be able to enter the S0I3 mode but only the S3 mode, resulting in a longer recovery delay and thus a poor user experience.

[0025] In Figure 1In the illustrated embodiment, when the laptop enters the sleep mode, its operating system runs the suspend code for all peripherals and triggers the S3 mode, causing the control unit 101 to enter the S3 mode. In this case, the control unit 101 first activates the PlatformResetPin pin, and in response to the activation of the PlatformResetPin pin, the peripherals 104-1, 104-2, and 104-3 enter the reset state. Next, the control unit 101 activates the SLP S3 pin, and in response to the activation of the SLP S3 pin, the voltage regulator 102 shuts down and stops powering the peripherals 104-1, 104-2, and 104-3.

[0026] In Figure 1 the illustrated embodiment, when the laptop is awakened, the control unit 101 first deactivates the SLP S3 pin, and in response to the deactivation of the SLP S3 pin, the voltage regulator 102 turns on to start powering the peripherals 104-1, 104-2, and 104-3. Next, the control unit 101 deactivates the PlatformResetPin pin, and in response to the deactivation of the PlatformResetPin pin, the PCIe link is reset and the drivers of the peripherals 104-1, 104-2, and 104-3 call the recovery code to initialize the peripherals 104-1, 104-2, and 104-3, thereby restoring the various functions of the peripherals 104-1, 104-2, and 104-3.

[0027] In Figure 1 the illustrated embodiment, when one or more peripherals of the laptop do not support D3hot or D3cold, the system cannot enter the S0I3 mode with a faster recovery latency and can only enter the S3 mode with a longer recovery latency.

[0028] Figure 2 The schematic diagram of a device 200 for controlling the sleep mode of a laptop according to another embodiment of the present invention is shown. As Figure 2 shown, the device 200 includes a control unit 201 and a voltage regulator 202, and an S0I3 logic unit 203 is integrated on the control unit 201. As Figure 2 shown, the control unit 201 is coupled to the PCIe peripherals 204-1 and 204-3 connected through the PCIe slot in the laptop CPU, coupled to the voltage regulator 202 via (for example) the GPIO-A pin, and directly coupled to the PCIe peripheral 204-2 via (for example) the GPIO-B pin. As Figure 2As shown, voltage regulator 202 is coupled to PCIe peripheral 204-2. That is to say, voltage regulator 202 is only coupled between control unit 201 and peripheral 204-2.

[0029] In Figure 2 the embodiment shown, control unit 201 can be implemented as the CPU of a laptop. In some embodiments, control unit 201 can also be implemented as part of the CPU of a laptop or a component separate from the laptop CPU.

[0030] As Figure 1 shown in Figure 2 only three PCIe peripherals 204-1, 204-2, and 204-3 are shown as examples. In some embodiments, the three PCIe peripherals 204-1, 204-2, and 204-3 can be, for example, any one of a graphics card, a network card, a sound card, a memory card, an acceleration card, and Bluetooth, but the present invention is not limited thereto. However, different from Figure 1 that shown in

[0031] As Figure 1 shown in Figure 2 the embodiment shown, peripheral 204-2 does not support D3hot or D3cold. But different from Figure 1 that shown in

[0032] In Figure 2 the embodiment shown, when the laptop triggers the sleep mode, its operating system first runs the suspend code of all peripherals and the PCIe links of PCIe peripherals 204-1 and 204-3 enter the low-power link state. Next, control unit 201 activates pin GPIO-B, and in response to the activation of pin GPIO-B, peripheral 204-2 enters the reset state. Next, control unit 201 deactivates pin GPIO-A, and in response to the deactivation of pin GPIO-A, voltage regulator 202 turns off and stops powering peripheral 204-2. In this case, control unit 201 will "drop" the PCIe link of peripheral 204-2. At this time, S0I3 logic unit 203 determines that the PCIe links of all peripherals of the laptop (for example, peripherals 204-1 and 204-3) have entered the low-power link state, thereby causing the operating system of the laptop to enter the S0I3 mode.

[0033] InFigure 2 In the illustrated embodiment, when the laptop is awakened, the operating system runs the recovery code for PCIe peripherals 204-1 and 204-3, and the PCIe links of PCIe peripherals 204-1 and 204-3 exit the low-power mode and enter the normal operating link mode. Next, the control unit 201 activates the pin GPIO-A, and in response to the activation of the pin GPIO-A, the voltage regulator 202 is turned on to start powering the peripheral 204-2. Next, the control unit 201 deactivates the pin GPIO-B, and in response to the deactivation of the pin GPIO-B, the PCIe link of the peripheral 204-2 is reset and the driver of the peripheral 204-2 calls the recovery code to initialize the peripheral 204-2, thereby restoring various functions of the peripheral 204-2.

[0034] In Figure 2 In the illustrated embodiment, although one or more peripherals of the laptop (e.g., peripheral 204-2) do not support D3hot or D3cold, by providing a separate voltage regulator for the peripheral, when the system triggers the sleep mode, the voltage regulator is controlled to cut off the power supply to the peripheral. At this time, although the PCIe link corresponding to the peripheral does not enter the low-power link state, its PCIe link will be "discarded". In this case, the system will default that the peripheral that does not support D3hot or D3cold does not exist, and thus the system will not prevent the entry into the S0I3 mode. When the system wakes up from the sleep mode, the voltage regulator is controlled to supply power to the peripheral. Since only the peripheral that does not support D3hot or D3cold needs to be reset and initialized, the recovery delay of the system is greatly shortened.

[0035] For example, assume that all peripherals of the system support D3hot or D3cold, then the system can enter the S0I3 mode, and it may only take 500 milliseconds to wake up the system. For cost-saving considerations, assume that one peripheral of the system (e.g., Bluetooth) does not support D3hot or D3cold, then the system can only enter the S3 mode, and when waking up the system, all peripherals need to be powered on and initialized again, which may take 5 seconds. Using Figure 2 the device shown in the embodiment, the remaining peripherals except the peripheral that does not support D3hot or D3cold (e.g., Bluetooth) still only need 500 milliseconds to recover from the S0I3 mode and only the Bluetooth peripheral may take 2 seconds to recover from the S3 mode. In this way, the wake-up of the entire system will take 2 seconds. Although the 2-second recovery delay is still relatively long compared to the 500 milliseconds for all peripherals to recover from the S0I3 mode, it has greatly shortened the recovery delay of the system compared to the 5 seconds required to recover from the S3 mode, especially when the Bluetooth may not be immediately used at the initial stage when the system is awakened.

[0036] In Figure 2 the illustrated embodiment, only the peripheral device 204-2 does not support D3hot or D3cold. Those skilled in the art should understand that Figure 2 the illustrated embodiment is illustrative. For various reasons such as cost savings and system compatibility, among the PCIe peripheral devices connected to the PCIe external slot of a laptop computer, there may be one or more PCIe peripheral devices that do not support D3hot or D3cold. In the case where multiple peripheral devices do not support D3hot or D3cold, each of the multiple PCIe peripheral devices can be coupled to a voltage regulator, or multiple voltage regulators can be respectively coupled to each of the multiple PCIe peripheral devices.

[0037] In Figure 2 the illustrated embodiment, the laptop computer is merely an exemplary system. Those skilled in the art should understand that the device for controlling the sleep mode according to the present invention can be used in various systems. For example, in some embodiments, the system may include any one of a laptop, a desktop computer, a netbook, a vehicle-mounted system, a set-top box, and the like.

[0038] The device for controlling the sleep mode of the system according to the present invention controls the PCIe peripheral device that does not support D3hot or D3cold to enter a low-power state (for example, power off) by providing a separate voltage regulator to the PCIe peripheral device that does not support D3hot or D3cold, so that the system "drops" the PCIe link of the PCIe peripheral device that does not support D3hot or D3cold, thereby still being able to enter the S0I3 mode, and further improving the system recovery latency and the user experience.

[0039] It should be noted that not all units in the above-mentioned devices are necessary, and some units can be ignored according to actual needs. The device structures described in the above-mentioned embodiments can be physical structures or logical structures, that is, some units may be implemented by the same physical entity, or some units may be implemented by multiple physical entities, or some components in multiple independent devices may be jointly implemented.

[0040] The control unit has been described in connection with various devices and operations. The control unit can be implemented using electronic hardware, computer software, or any combination thereof. Whether the control unit is implemented as hardware or software will depend on the particular application and the overall design constraints imposed on the system. By way of example, the control unit, any part of the control unit, or any combination of the control unit given in this disclosure can be implemented as a microprocessor, a microcontroller, a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gate logic, discrete hardware circuitry, and other suitable processing components configured to perform the various functions described in this disclosure. The functions of the control unit, any part of the control unit, or any combination of the control unit given in this disclosure can also be implemented as software executed by a microprocessor, a microcontroller, a DSP, or other suitable platforms.

[0041] The foregoing description of the present invention has been provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present invention will be readily apparent to those skilled in the art, and the general principles defined by the present invention may be applied to other variations without departing from the scope of the present invention. Thus, the present invention is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device for controlling the sleep mode of a system, comprising: A control unit, the control unit being coupled to a first set of peripherals of the system and a second set of peripherals different from the first set of peripherals; And A power supply module, the power supply module being coupled between the control unit and the second set of peripherals, the control unit being configured to control the power supply module to supply power to the second set of peripherals, Characterized in that the control unit is further configured to make the first set of peripherals and the system enter a second low-power mode and a sleep mode respectively by controlling the second set of peripherals to enter a first low-power mode.

2. The device according to claim 1, characterized in that The first set of peripherals and the second set of peripherals include PCIe peripherals.

3. The device according to claim 2, characterized in that, The first set of peripherals includes PCIe peripherals that support D3hot or D3cold modes defined based on PCIe, and the second set of peripherals includes PCIe peripherals that do not support D3hot or D3cold modes defined based on PCIe.

4. The device according to claim 3, characterized in that, The sleep mode includes the S0I3 mode.

5. The device according to claim 4, characterized in that, The first set of peripherals entering the second low-power mode includes the first set of peripherals entering the D3hot or D3cold mode, and the second set of peripherals entering the first low-power mode includes turning off the power supply module to stop supplying power to the second set of peripherals.

6. The device according to claim 5, characterized in that, The control unit is further configured to control the first set of peripherals to resume normal operation from the D3hot or D3cold mode, the second set of peripherals to resume normal power supply operation, and the system to wake up from the S0I3 mode.

7. The device according to claim 4, characterized in that, The control unit includes a determination unit, the determination unit being configured to determine whether the PCIe links corresponding to the first set of peripherals and the second set of peripherals enter a low-power link state.

8. The device according to claim 1, characterized in that When the second set of peripherals includes multiple peripherals, the power supply module includes multiple sub-power supply modules, and each of the multiple peripherals is coupled to one of the multiple sub-power supply modules.

9. The device according to claim 1, wherein The system includes any one of a notebook, a desktop computer, a netbook, a vehicle-mounted system, and a set-top box.

10. The device according to claim 9, characterized in that, The first set of peripherals and the second set of peripherals respectively include one or more of a graphics card, a network card, a sound card, a memory card, an acceleration card, and Bluetooth.

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