Memory device

Abstract

A memory device comprises a memory array, a plurality of access word lines and a first tracking word line. The memory array comprises a plurality of bit units configured on a plurality of rows and a plurality of columns. A plurality of access word lines extend along a lateral direction. The plurality of rows respectively correspond to a plurality of access word lines. The first trace word line extends along a lateral direction and has a first portion and a second portion. The first part extends to the middle from the edge of the memory array, and the second part extends to the edge from the middle of the memory array. A first portion of the first trace word line includes at least two first conductive lines disposed respectively across a first combination of the plurality of metallization layers, and a second portion of the first trace word line includes at least two second conductive lines disposed respectively across a second combination of the plurality of metallization layers. The first combination is different from the second combination.

Description

Technical Field

[0001] This disclosure document relates to a memory device, particularly to a memory device having a trace schedule circuit. Background Art

[0002] In the pursuit of continuous progress in semiconductor technology, the development of advanced technology nodes has become imperative. Among these nodes, one aspect that requires high attention is the delay trace schedule adopted in the design of Static Random Access Memory (SRAM). Utility Model Content

[0003] This disclosure document provides a memory device, including a memory array, a plurality of access word lines, and a first trace word line. The memory array includes a plurality of bit cells arranged on a plurality of rows and a plurality of columns. The plurality of access word lines extend along a lateral direction. The plurality of rows respectively correspond to the plurality of access word lines. The first trace word line extends along the lateral direction and has a first part and a second part. The first part extends from an edge of the memory array to a middle of the memory array, and the second part extends from the middle of the memory array to the edge of the memory array. The first part of the first trace word line includes at least two first conductors, and the at least two first conductors are respectively disposed across a first combination of a plurality of metallization layers. The second part of the first trace word line includes at least two second conductors, and the at least two second conductors are respectively disposed across a second combination of a plurality of metallization layers. The first combination is different from the second combination.

[0004] This disclosure document provides a memory device, including a plurality of access word lines and a first trace word line. The plurality of access word lines extend along a lateral direction and respectively correspond to a plurality of rows of a memory array. The first trace word line extends along the lateral direction and has a first part and a second part. A plurality of even access word lines among the plurality of access word lines each include two first conductors, and the two first conductors are respectively disposed across a first combination of a plurality of metallization layers. A plurality of odd access word lines among the plurality of access word lines each include two second conductors, and the two second conductors are respectively disposed across a second combination of a plurality of metallization layers. The first part of the first trace word line includes two third conductors, and the two third conductors are respectively disposed across a first combination of a plurality of metallization layers. The second part of the first trace word line includes two fourth conductors, and the two fourth conductors are respectively disposed across a second combination of a plurality of metallization layers. The first combination is different from the second combination.

[0005] The present disclosure provides a memory device, comprising: a memory array disposed along a main surface of a substrate and including a plurality of bit cells disposed on a plurality of rows and a plurality of columns; a plurality of access word lines extending along a lateral direction and respectively coupled to the plurality of rows, wherein a plurality of even access word lines among the plurality of access word lines each include two first conductors respectively disposed across a first combination of a plurality of metallization layers disposed above the main surface, and a plurality of odd access word lines among the plurality of access word lines each include two second conductors respectively disposed across a second combination of the plurality of metallization layers; and a trace word line extending along the lateral direction and having a first portion and a second portion. The first portion of the trace word line includes two third conductors respectively disposed across the first combination of the plurality of metallization layers. The second portion of the trace word line includes two fourth conductors respectively disposed across the second combination of the plurality of metallization layers. The first combination is different from the second combination. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of embodiments of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 FIG. shows a schematic diagram of a system including a trace scheduling circuit in accordance with some embodiments;

[0008] Figure 2 FIG. shows a cross-sectional view of an exemplary trace scheduling circuit shown in Figure 1 in accordance with some embodiments;

[0009] Figure 3 FIG. shows a schematic diagram of a system including a trace scheduling circuit in accordance with some embodiments;

[0010] Figure 4 FIG. shows a schematic diagram of a system including a trace scheduling circuit in accordance with some embodiments;

[0011] Figure 5 FIG. shows a schematic diagram of a trace scheduling circuit shown in Figure 1 in accordance with some embodiments;

[0012] Figure 6 FIG. shows a schematic diagram of a system including a trace scheduling circuit in accordance with some embodiments;

[0013] Figure 7 FIG. shows a schematic diagram of a trace scheduling circuit shown in Figure 6 in accordance with some embodiments;

[0014] Figure 8 Illustrates a cross-sectional view of an example trace schedule circuit as shown in Figure 1 ;

[0015] Figure 9 Illustrates a cross-sectional view of an example trace schedule circuit as shown in Figure 1 ;

[0016] Figure 10 Illustrates a schematic diagram of a trace schedule circuit as shown in some embodiments; and Figure 1

[0017] Figure 11 Illustrates a flowchart of an example method for manufacturing a trace schedule circuit as shown in some embodiments. Figure 1

[0018]

Symbol Description

[0019] 100: System

[0020] 102: Memory array

[0021] 103: Trace unit

[0022] 104: Bit cell

[0023] 106: Access character line (WL) / row

[0024] 108: Access bit line (BL) / column

[0025] 110: Trace schedule circuit / first trace character line

[0026] 110a, 110b: Trace character line / first conductor

[0027] 112: First part / first half of trace character line

[0028] 112a: First metallization layer / first half

[0029] 112b: Third metallization layer / first half

[0030] 114: Second part / second half of trace character line

[0031] 114a: First metallization layer / second half

[0032] 114b: Fifth metallization layer / second half

[0033] 120: Inverter

[0034] 200: Cross-sectional view of trace schedule circuit ​​

[0035] 300: System

[0036] 310: Tracking Plan Circuit / First Tracking Character Line

[0037] 312: First Part / First Half of Tracking Character Line

[0038] 314: Second Part / Second Half of Tracking Character Line

[0039] 400: System

[0040] 410: Tracking Plan Circuit / First Tracking Character Line

[0041] 412: First Part / First Half of Tracking Character Line

[0042] 414: Second Part / Second Half of Tracking Character Line

[0043] 502: Address Decoder / First Character Line Decoder

[0044] 504: Address Decoder / Second Character Line Decoder

[0045] 506: Address Decoder / Third Character Line Decoder

[0046] 510: First Tracking Character Line

[0047] 520: Second Tracking Character Line

[0048] 530: Third Tracking Character Line

[0049] 600: System

[0050] 610: Tracking Plan Circuit / First Tracking Bit Line

[0051] 702: Address Decoder / First Bit Line Decoder

[0052] 704: Address Decoder / Second Bit Line Decoder

[0053] 710: First Tracking Character Line

[0054] 720: Second Tracking Character Line

[0055] 800: Cross - sectional View of Tracking Plan Circuit

[0056] 802,804: Tracking Plan Circuit

[0057] 810a~810d: Via Structure

[0058] 900: Cross - sectional View of Tracking Plan Circuit

[0059] 902,904: Tracking Plan Circuit

[0060] 910a to 910d: Metal-2 (M2) / Metal-4 (M4) islands

[0061] 1002, 1004: First tracking character lines

[0062] 1006, 1008: First tracking character lines

[0063] 1100: Method

[0064] 1102, 1104: Operations

[0065] 1106: Operation

[0066] A[0], A[5]: Signals

[0067] AB[0], AB[5]: Signals

[0068] BL[0]: Bit line

[0069] Cc, Cg: Capacitance value / capacitance level

[0070] C M2 , C M4 : Capacitance value / capacitance level

[0071] C VIA : Capacitance value / capacitance level

[0072] M0: Metal-0

[0073] M1: Metal-1

[0074] M2: Metal-2

[0075] M3: Metal-3

[0076] M4: Metal-4

[0077] M5: Metal-5

[0078] SAEN: Signal

[0079] TRKBL: Tracking bit line

[0080] TRKBLEN: Signal

[0081] TRKSELB: Signal

[0082] TRKSEL: Signal

[0083] TRKWLEN: Signal

[0084] TRKWL: Tracking character line

[0085] VDD: Signal / Voltage

[0086] VIA1 - VIA4: Through - hole structure

[0087] VSS: Voltage

[0088] WL[0], WL[1]: Word line

[0089] WL

[31] , WL

[32] : Word line

[0090] WL

[62] , WL

[63] : Word line

[0091] X, Y: Direction Detailed implementation manners

[0092] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure document. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. In addition, embodiments of this disclosure document may repeat element symbols and / or letters in each example. This repetition is for the purposes of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0093] In addition, for ease of description, spatial relative terms (such as "beneath", "below", "lower", "above", "upper", and the like) may be used herein to describe the relationship of one element or feature shown in the figures to another element (or elements) or feature (or features). In addition to the orientation depicted in the figures, spatial relative terms are intended to encompass different orientations of the elements during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and thus the spatial relative descriptors used herein may be interpreted similarly.

[0094] A particular challenge faced by Static Random Access Memory (SRAM) is the large resistance encountered in the word line (WL) due to the use of wide input / output (I / O) interfaces. To address this issue, a dual word line scheme that combines metal-1 (M1) and metal-3 (M3) in parallel is implemented. This configuration helps mitigate the impact of high word line resistance, thereby ensuring reliable and efficient operation. However, in advanced technology nodes, the reduced height of the SRAM bit cells results in a smaller word line pitch, which in turn creates new problems. The traditional dual word line scheme cannot be directly applied to each word line pitch, and the method needs to be modified. Therefore, the SRAM array needs to separate multiple word lines into even word lines and odd word lines. When the even word lines use M1 and M3, the odd word lines can also use M1 and metal-5 (M5). At the same time, this difference in the word line configuration creates a deviation in the original delay tracking scheme, which in turn affects the accuracy of process variation handling. Using even / odd word lines may cause the original delay tracking scheme to be unable to accurately track the resistive-capacitive (RC) delay of each word line. For example, a delay tracking scheme using M1 and M3 word lines cannot accurately track the RC delay of M1 and M5 word lines.

[0095] To address these challenges, an improved SRAM delay tracking scheme is necessary. This scheme can take into account the particularities of advanced technology nodes, such as the dual WL method, the need for separate WLs, and the impact of process variations. By developing a refined delay tracking scheme, enhanced performance and robustness can be achieved in SRAM design at advanced technology nodes that go beyond typical process nodes used in the industry.

[0096] Figure 1 FIG. shows a schematic diagram of a system 100 including a tracking scheme circuit 110 according to some embodiments. The system 100 may include a memory array 102, a plurality of access word lines (WLs) 106, a plurality of access bit lines (BLs) 108, a first tracking word line 110, and a plurality of inverters 120. The memory array 102 may be a Static Random Access Memory (SRAM). The memory array 102 may include a plurality of bit cells 104 configured on a plurality of rows and a plurality of columns. The plurality of rows may be respectively operably corresponding to the plurality of access word lines 106. The plurality of columns may be respectively operably corresponding to the plurality of access bit lines 108. Although Figure 1 not explicitly shown in the figure, the components of the plurality of bit cells 104 may be operably (e.g., electrically) coupled to each other and to an input / output (I / O) circuit and / or a control circuit (both not shown in Figure 1In Figure 1 In the illustrated example, although for clarity, multiple components are illustrated as separate blocks, in some other embodiments, some or all of the components illustrated in Figure 1 may be integrated together. For example, the memory array 102 may include a plurality of inverters 120.

[0097] A subset of the bit cells 104 may be commandeered or repurposed for latency tracking and may be referred to as tracking cells 103. Various numbers of tracking cells 103 may be used, including one tracking cell. In an exemplary embodiment, the tracking cells 103 do not operate like the symbolic bit cells in terms of storing data and supporting read / write operations. Instead, the various bit lines used for addressing cells in the case of symbolic bit cells are commandeered for other purposes.

[0098] A plurality of access word lines 106 may extend along a lateral direction (e.g., the Y direction). The plurality of access word lines 106 may be used to select and activate specific rows of SRAM cells 104 within the memory array 102. When a specific row is selected by activating the corresponding word line, the specific row allows read or write operations to be performed on the cells in that row. Activation of the word line enables data transfer between the memory cell and the bit line.

[0099] A plurality of access bit lines 108 may extend along a vertical direction (e.g., the X direction). The plurality of access bit lines 108 may be responsible for transferring data to and from the SRAM cells 104. The bit lines may be organized in pairs (e.g., a bit line and a bit line bar), where each pair is associated with a specific column of SRAM cells. During a read operation, the data stored in the selected cell is transferred to the corresponding bit line pair, and the information can then be retrieved. During a write operation, the data to be stored is applied to the appropriate bit line pair, thereby facilitating programming of the target memory cell.

[0100] A first tracking word line 110 may also extend along the lateral direction. The first tracking word line 110 may be used to track the propagation time present on the access word lines 106. The first tracking word line 110 may have a first portion 112 extending from an edge of the memory array 102 to the middle of the memory array 102 and a second portion 114 extending from the middle of the memory array 102 to the edge of the memory array 102. The first portion 112 of the first tracking word line 110 may include at least two first conductors disposed respectively across a first combination of multiple metallization layers (e.g., M1 + M3). The second portion 114 of the first tracking word line 110 may include at least two second conductors disposed respectively across a second combination of multiple metallization layers (e.g., M1 + M5). The first combination is different from the second combination.

[0101] By using different combinations of metallization layers for the first half (i.e., the first half trace character line 112) and the second half (i.e., the second half trace character line 114) of the first trace character line 110, the first trace character line 110 can reduce the variation of the macro data output delay (Tcd). The first trace character line 110 can be compatible / applied to various advanced SRAM processes. The detailed implementation method of the first trace character line 110 will be Figure 2 described in

[0102] In some embodiments, the first half trace character line 112 can use M1 and M3, and the second half trace character line 114 can use M1 and M5. As shown in Table 1, when considering the parasitic resistance (assumed to be "R") and capacitance value (assumed to be "C") formed by the character lines formed by metal 1 and metal 3 (i.e., M1+M3) and the character lines formed by metal 1 and metal 5 (i.e., M1+M5), it can be inferred that the RC delay associated with each character line is equal to R*C.

[0103]

[0104] Table 1

[0105] In Table 2, assuming that the parasitic resistance of the character line formed by metal 1 and metal 5 (M1+M5) doubles to "2R" due to process variations, the RC delay associated with the M1+M5 character line becomes 2R*C. The RC delay associated with the M1+M3 character line is equal to R*C. To mitigate the impact of this variation, the present disclosure provides a tracking plan that combines the coefficients associated with the M1+M3 and M1+M5 character lines in the delay tracking process. By considering both coefficients, the tracking plan aims to minimize the difference and achieve more accurate delay tracking, thereby improving the performance and reliability in advanced SRAM designs.

[0106]

[0107] Table 2

[0108] In a tracking plan that considers only one combination of metallization layers (M1+M3 or M1+M5) for the entire tracking character line, there may be a significant difference between the actual M1+M5 RC delay (e.g., 2RC) and the tracking plan delay (e.g., RC). This difference may be even greater (e.g., 2RC - RC = 1RC) compared to a proposed tracking plan that considers different combinations (M1+M3 and M1+M5). In the proposed plan, the difference between the actual M1+M5 RC delay and the tracking plan delay is reduced (e.g., 2RC - 1.5RC = 0.5RC). By considering multiple combinations of metallization layers, the proposed plan aims to improve accuracy and minimize differences in the delay tracking process, thereby achieving more reliable and efficient performance in advanced SRAM designs.

[0109] Multiple inverters 120 can amplify and reproduce the stored data during read and write operations. In certain embodiments, multiple inverters 120 can also provide a fixed base delay. Multiple inverters 120 can insert delays to shift forward the measurement window for distinguishing tracking delays.

[0110] Figure 2 Illustrated in accordance with some embodiments Figure 1 is a cross-sectional view of an example tracking plan circuit 110 shown in Figure 2 Illustrated is the path of a tracking plan circuit 110 in a multi-layer interconnect structure (e.g., M0, M1, M2, M3, M4, and M5 layers).

[0111] The first tracking character line 110 may have a first portion 112 and a second portion 114. The first portion 112 of the first tracking character line 110 may include at least two first conductors disposed respectively across a first combination of multiple metallization layers (e.g., M1+M3). The first combination may include a first metallization layer and a second metallization layer in the multiple metallization layers. The first metallization layer is the first closest to the memory array 102 among the multiple metallization layers (e.g., 112a in M1), and the second metallization layer is the third closest to the memory array 102 among the multiple metallization layers (e.g., 112b in M3). The second portion 114 of the first tracking character line 110 may include at least two second conductors disposed respectively across a second combination of multiple metallization layers (e.g., M1+M5). The second combination includes the first metallization layer (e.g., 114a in M1) and a third metallization layer in the multiple metallization layers. The third metallization layer is the fifth closest to the memory array 102 among the multiple metallization layers (e.g., 114b in M5).

[0112] The first part 112 and the second part 114 can be coupled / interconnected to each other via a plurality of via structures (VIA). For example, the trace word line 110a in M1 can include a first half 112a and a second half 114a. The first half 112a can be coupled to the second half 114a via the via structure 1 (VIA1) (between M1 and metal 2 (M2)) and a section of the wire disposed in M2. Thus, the path of the trace word line 110a can be described as M1 - VIA1 - M2 - VIA1 - M1. In another example, the trace word lines 110b in M3 and M5 can include a first half 112b and a second half 114b. The first half 112b can be coupled to the second half 114b via the via structure 3 (VIA3) (between M3 and metal 4 (M4)) and the via structure 4 (VIA4) (between M4 and M5). Thus, the path of the trace word line 110b can be described as M3 - VIA3 - VIA4 - M5. In some embodiments, at least two first wires 110a and 110b can be coupled to each other via a plurality of via structures (e.g., VIA1, via structure 2 (VIA2), VIA3, or VIA4).

[0113] Figure 3 FIG. shows a schematic diagram of a system 300 including a trace scheduling circuit 310 according to some embodiments. The system 300 can include a memory array 102, a plurality of access word lines 106, a plurality of access bit lines 108, a first trace word line 310, and a plurality of inverters 120. Figure 3 The system 300 is substantially similar to Figure 1 the system 100, except for the detailed first trace word line 310 having different trace word line paths / schedules. Thus, the following description of the system 300 will focus on the differences.

[0114] The first trace word line 310 can have a first part 312 extending from the edge of the memory array 102 to the middle of the memory array 102 and a second part 314 extending from the middle of the memory array 102 to the edge of the memory array 102. The first half trace word line 312 can use M1 and M3, and the second half trace word line 314 can use M5. The first part 312 of the first trace word line 310 can include at least two first wires disposed respectively across a first combination of a plurality of metallization layers (e.g., M1 + M3). The second part 314 of the first trace word line 310 can include a second wire disposed across one metallization layer (e.g., M5).

[0115] By using different combinations of metallization layers for the first half (i.e., the first half tracking character line 312) and the second half (i.e., the second half tracking character line 314) of the first tracking character line 310, the first tracking character line 310 can reduce the variation of the macro data output delay (Tcd). The first tracking character line 310 can be compatible / applied to various advanced SRAM processes.

[0116] Figure 4 FIG. shows a schematic diagram of a system 400 including a tracking scheme circuit 410 according to some embodiments. The system 400 may include a memory array 102, a plurality of access character lines 106, a plurality of access bit lines 108, a first tracking character line 410, and a plurality of inverters 120. Figure 4 The system 400 is substantially similar to Figure 1 The system 100, except for the detailed first tracking character line 410 with different tracking character line paths / schemes. Therefore, the following description of the system 400 will focus on the differences.

[0117] The first tracking character line 410 may have a first portion 412 extending from the edge of the memory array 102 to the middle of the memory array 102 and a second portion 414 extending from the middle of the memory array 102 to the edge of the memory array 102. The first half tracking character line 412 may use M3, and the second half tracking character line 414 may use M1 and M5. The first portion 412 of the first tracking character line 410 may include a first wire disposed across one metallization layer (e.g., M3). The second portion 414 of the first tracking character line 410 may include at least two first wires disposed across a first combination of a plurality of metallization layers (e.g., M1 + M5), respectively.

[0118] By using different combinations of metallization layers for the first half (i.e., the first half tracking character line 412) and the second half (i.e., the second half tracking character line 414) of the first tracking character line 410, the first tracking character line 410 can reduce the variation of the macro data output delay (Tcd). The first tracking character line 410 can be compatible / applied to various advanced SRAM processes.

[0119] Figure 5 FIG. shows according to some embodiments Figure 1 A schematic diagram of the tracking scheme circuit 110 shown in. The tracking scheme circuit 110 may include a plurality of address decoders 502, 504, 506, a first tracking character line 510, a second tracking character line 520, and a third tracking character line 530. Figure 5 The tracking scheme circuit 110 is substantially similar to Figure 1tracking scheme circuit 110, in addition to more precisely selecting the detailed first tracking character line 110 of the tracking character line path / scheme. Therefore, the following description of the tracking scheme circuit 110 will focus on the differences.

[0120] To achieve precise selection of the tracking character line path, address decoding in the tracking scheme driver can be combined. Signal A[0] can be used to decode the even / odd character lines, thereby facilitating accurate determination of the appropriate character line path in the tracking scheme.

[0121] As Figure 5 shown, signal VDD, signal TRKSELB, and signal TRKWLEN can be inputs to the first character line decoder 502. Signal A[0], signal TRKSEL, and signal TRKWLEN can be inputs to the second character line decoder 504. Signal AB[0], signal TRKSEL, and signal TRKWLEN can be inputs to the third character line decoder 504. The outputs of the multiple address decoders 502, 504, 506 can drive the character line driver to select the type of tracking character line path to be used for the SRAM.

[0122] In the memory array 102, the first tracking character line 510 can extend along a lateral direction (e.g., the Y direction). The first tracking character line 510 can have a first portion extending from the edge of the memory array to the middle of the memory array and a second portion extending from the middle of the memory array 102 to the edge of the memory array 102. The first portion of the first tracking character line 510 can include at least two first conductors respectively disposed across a first combination of multiple metallization layers (e.g., M1+M3). The second portion of the first tracking character line 510 can include at least two second conductors respectively disposed across a second combination of multiple metallization layers (e.g., M1+M5). The first combination is different from the second combination.

[0123] In the memory array 102, the second tracking character line 520 can extend along a lateral direction (e.g., the Y direction). The second tracking character line 520 can have a first portion extending from the edge of the memory array to the middle of the memory array 102 and a second portion extending from the middle of the memory array to the edge of the memory array 102. The first portion of the second tracking character line 520 can each include at least two third conductors respectively disposed across a first combination of multiple metallization layers (e.g., M1+M5). The second portion of the second tracking character line 520 can include at least two fourth conductors respectively disposed across a first combination of multiple metallization layers (e.g., M1+M5).

[0124] In the memory array 102, the third tracking character line 530 may extend along a lateral direction (e.g., the Y direction). The third tracking character line 530 may have a first portion extending from an edge of the memory array to the middle of the memory array 102 and a second portion extending from the middle of the memory array to an edge of the memory array 102. The first portions of the third tracking character line 530 may each include at least two fifth conductors disposed respectively across a second combination of multiple metallization layers (e.g., M1+M3). The second portion of the third tracking character line 530 includes at least two sixth conductors disposed respectively across a second combination of multiple metallization layers (e.g., M1+M3).

[0125] The first tracking character line 510, the second tracking character line 520, and the third tracking character line 530 are each used to track the propagation time present on the access character line 106. The second tracking character line 520 and the third tracking character line 530 are each selected based on a signal (e.g., signal A[0] or signal AB[0]) that decodes one of the multiple access character lines 106. The first tracking character line 510 may be selected independently of the signal. Signal A[0] may be used to decode even / odd character lines.

[0126] Signal A[0] may be used to decode even / odd character lines among the multiple character lines. The result of the decoding determines the type of tracking character line path used in the SRAM. Options for the tracking character line path include M1+M3 for tracking even character lines (e.g., the third tracking character line 530), M1+M5 for tracking odd character lines (e.g., the second tracking character line 520), or a combination of M1+M3 and M1+M5 for tracking specific portions of both even and odd character lines (e.g., the first tracking character line 510). This flexibility in choosing the tracking character line path allows for customization and optimization of the SRAM design according to specific requirements and performance considerations.

[0127] In Table 3, when the signal TRKWLEN is set to the voltage VDD, the signal TRKSEL is set to the voltage VDD, the signal TRKSELB is set to 0 volts (V), the signal A[0] is set to 0V, and the signal AB[0] is set to the voltage VDD, the tracking word line (TRKWL) formed by the combination of M1 and M3 (e.g., the third tracking word line 530) can be selected. When the signal TRKWLEN is set to the voltage VDD, the signal TRKSEL is set to the voltage VDD, the signal TRKSELB is set to 0V, the signal A[0] is set to the voltage VDD, and the signal AB[0] is set to 0V, the tracking word line (TRKWL) formed by the combination of M1 and M5 (e.g., the second tracking word line 520) can be selected. When the signal TRKWLEN is set to the voltage VDD, the signal TRKSEL is set to 0V, the signal TRKSELB is set to the voltage VDD, the signal A[0] is set to X, and the signal AB[0] is set to X, the tracking word line (TRKWL) formed by the combination of M1, M3, and M5 (e.g., the first tracking word line 510) can be selected.

[0128] TRKWLEN TRKSEL TRKSELB A[0] AB[0] TRKWL M1+M3 VDD VDD 0V 0V VDD TRKWL M1+M5 VDD VDD 0V VDD 0V TRKWL M1+M3+M5 VDD 0V VDD X X

[0129] Table 3

[0130] Figure 6 FIG. 6 illustrates a schematic diagram of a system 600 including a tracking scheme circuit according to some embodiments. Figure 7 Illustrates according to some embodiments Figure 6 A schematic diagram of the tracking scheme circuit 610 shown in. The system 600 may include a memory array 102, a plurality of access word lines 106, a plurality of access bit lines 108, a first tracking bit line 610, and a plurality of inverters 120. Figure 6 The system 600 of is substantially similar to Figure 1 The system 100 of, except for the detailed first tracking bit line 610 having a different tracking word line path / scheme. Therefore, the following description of the system 600 will focus on the differences.

[0131] The first tracking bit line 610 can be used to track the propagation time present on the access bit line 108. The first tracking bit line 610 may have a first portion extending from the bottom of the memory array 102 to the middle of the memory array 102 and a second portion extending from the middle of the memory array 102 to the bottom of the memory array 102. The first portion of the first tracking bit line 610 may include at least two first wires disposed respectively across a combination of a plurality of metallization layers. The second portion of the first tracking bit line 610 may include at least two second wires disposed respectively across another combination of a plurality of metallization layers. These combinations may be different.

[0132] By using different combinations of metallization layers for the first half and the second half of the first tracking bit line 610, the first tracking bit line 610 can reduce the variation of the macro data output delay (Tcd). The first tracking bit line 610 can be compatible / applied to various advanced SRAM processes.

[0133] The address decoding in the tracking program receiver is combined to enable the selection of an exact tracking bit line path. The signal A[5] can be used to decode the bit line as the top (TOP) tracking bit line or the bottom (BOT) tracking bit line. This decoding allows the selection of a specific type of tracking bit line path to be used in the SRAM. To achieve an accurate selection of the tracking bit line path, the address decoding in the tracking program driver can be combined. The signal A[5] can be used to decode the top / bottom bit line, thereby facilitating the accurate determination of the appropriate bit line path in the tracking program.

[0134] As Figure 7 shown, the signal TRKBLEN and the signal A[5] can be inputs to the first bit line decoder 702. The signal TRKBLEN and the signal AB[5] can be inputs to the second bit line decoder 704. The outputs of the multiple address decoders 702, 704 can drive the bit line driver to select the type of tracking bit line path to be used in the SRAM. The options for the tracking bit line path include using M0 to track the bottom tracking bit line (TRKBL) or tracking the top tracking bit line (TRKBL) by combining M0 and M2. This flexibility allows the SRAM design to be customized and optimized according to specific requirements and performance considerations.

[0135] In Table 4, when the signal TRKBLEN is set to the voltage VDD, the signal A[5] is set to 0V, and the signal AB[5] is set to the voltage VDD, the tracking bit line (TRKBL) formed by the combination of M0 (e.g., the second tracking word line 720) can be selected. When the signal TRKBLEN is set to the voltage VDD, the signal A[5] is set to the voltage VDD, and the signal AB[5] is set to 0V, the tracking bit line (TRKBL) formed by the combination of M0 and M2 (e.g., the first tracking word line 710) can be selected.

[0136] TRKBLEN A[5] AB[5] TRKBL M0 VDD 0V VDD TRKBL M0+M2 VDD VDD 0V

[0137] Table 4

[0138] By combining the address decoding and using the signal A[5] to determine the type of the tracking bit line, the designer can accurately select the appropriate tracking bit line path in the SRAM design, thereby ensuring effective and reliable data storage and retrieval operations.

[0139] Figure 8 illustrates according to some embodimentsFigure 1 Cross-sectional view of an example trace schedule circuit 110 shown in Figure 8 Trace character lines (TRKWL) are shown that use different numbers of via structures (VIA) to adjust the capacitance level of the trace schedule.

[0140] For example, in Figure 8 , the trace schedule circuit 802 can utilize three VIAs (e.g., VIA 810a, 810b, 810c), and the trace schedule circuit 804 can utilize four VIAs (e.g., VIA 810a, 810b, 810c, and 810d). The capacitance level of the trace schedule can be adjusted by changing the number of VIAs employed. The capacitance associated with the VIAs can be used to modify the load in the trace schedule. Specifically, increasing the number of VIAs results in a corresponding adjustment of the capacitance level (e.g., from +1*C VIA adjusted to N*C VIA ), thereby allowing for fine-tuning of the characteristics and performance of the trace schedule.

[0141] Figure 9 A cross-sectional view of an example trace schedule circuit 110 shown in Figure 1 is shown in accordance with some embodiments. Figure 9 Trace character lines (TRKWL) are shown that use different numbers of metallization islands to adjust the capacitance level of the trace schedule.

[0142] For example, in Figure 9 , the trace schedule circuit 902 can utilize three M2 / M4 islands (e.g., islands 910a, 910b, 910c), and the trace schedule circuit 904 can utilize four M2 / M4 islands (e.g., islands 910a, 910b, 910c, 910d). The capacitance level of the trace schedule can be adjusted by changing the number of M2 / M4 islands employed. The number of M2 / M4 islands can be used to modify the load characteristics in the trace schedule. By increasing the number of M2 / M4 islands, the capacitance level can be effectively adjusted (e.g., from +1*(C M2 +C M4 ) adjusted to N*(C M2 +C M4 ), thereby allowing for fine-tuning of the characteristics and performance of the trace schedule.

[0143] Figure 10 A schematic diagram of the trace schedule circuit 110 shown in Figure 1 is shown in accordance with some embodiments. Figure 10 Trace character lines (TRKWL) are shown that use a floating metal layer to adjust the capacitance level of the trace schedule.

[0144] To adjust the capacitance value in a tracking scheme, a floating metal nearby method can be used. By using a floating metal layer (which may not contribute to the capacitance value), the contributed capacitance value can be adjusted, thereby allowing different load levels in the tracking scheme. Using a floating metal (which does not significantly contribute to the capacitance value) enables flexible adjustment of the overall capacitance value and optimization of the performance of the tracking scheme.

[0145] For example, in Figure 10 and Table 5, when the first tracking character line 1002 is implemented with the M1+M3 combination, it can be positioned adjacent to two metal layers carrying the voltages VDD / VSS. This proximity property can generate a combined capacitance value of 2*Cc + Cg, where Cc represents the capacitance value contributed by the metal layer and Cg represents any other relevant capacitance value.

[0146] Continuing Figure 10 and Table 5, when the first tracking character line 1004 is implemented with the M1+M3 combination, it can be positioned adjacent to the metal layer carrying the voltages VDD / VSS and a high-Z (impedance) metal layer. This configuration can generate a combined capacitance value of Cc + Cg, where Cc represents the capacitance value contributed by the metal layer and Cg represents any other relevant capacitance value.

[0147] Continuing Figure 10 and Table 5, when the first tracking character line 1006 is implemented with the M1+M3 combination, it can be positioned adjacent to the high-Z (high impedance) metal layer and the metal layer carrying the voltages VDD / VSS. This configuration can generate a combined capacitance value of Cc + Cg, where Cc represents the capacitance value contributed by the metal layer and Cg represents any other relevant capacitance value.

[0148] Continuing Figure 10 and Table 5, when the first tracking character line 1008 is implemented with the M1+M3 combination, it can be positioned adjacent to two high-Z (high impedance) metal layers. This configuration can generate a combined capacitance value of Cg, where Cg represents any other relevant capacitance value.

[0149] Voltage on metal other than tracking signal VDD / VSS High Z VDD / VSS 2*Cc + Cg Cc + Cg High Z Cc + Cg Cg

[0150] Table 5

[0151] Figure 11 illustrates a flowchart of an example method for manufacturing Figure 1 the tracking scheme circuit 110 shown in. The method 1100 can be used to manufacture the first tracking character line 110. It should be noted that the method 1100 is only an example and is not intended to limit this disclosure. Therefore, it should be understood that additional operations can be provided before, during, or after Figure 11 the method 1100, and other operations may only be briefly described herein.

[0152] Method 1100 starts with operation 1102, in which a memory array 102 is formed along a main surface of a substrate. The memory array 102 includes a plurality of bit cells 104 disposed on a plurality of rows 106 and a plurality of columns 108. For example, in Figure 1 this case, the plurality of rows may be respectively operatively coupled to a plurality of access word lines 106. The plurality of columns may be respectively operatively coupled to a plurality of access bit lines 108.

[0153] Method 1100 then performs operation 1104, in which a plurality of access word lines 106 extending along a lateral direction and operatively coupled to the plurality of rows 106 are respectively formed. Continuing Figure 1 with the above example, the even access word lines (e.g., access word lines WL[0], WL[2], WL[4], etc.) among the plurality of access word lines 106 may each be composed of two first wires respectively disposed by crossing a first combination (e.g., M1+M3) of a plurality of metallization layers, and this first combination is disposed above the main surface. The odd access word lines (e.g., access word lines WL[1], WL[3], WL[5]...) among the plurality of access word lines 106 may each be composed of two second wires respectively disposed by crossing a second combination (e.g., M1+M5) of a plurality of metallization layers. Conventionally, the use of even / odd word lines may pose challenges to accurately tracking the resistance-capacitance (RC) delay of each word line. For example, the delay tracking scheme for word lines using the first combination (e.g., M1 and M3) cannot accurately track the RC delay of word lines of the second combination (e.g., M1 and M5).

[0154] Method 1100 then performs operation 1106, in which a first tracking word line 110 extending along a lateral direction is formed. The first tracking word line 110 may have a first portion 112 and a second portion 114. Continuing Figure 1In the above example, the first part 112 of the first trace character line 110 may be composed of two third wires respectively disposed by crossing a first combination of a plurality of metallization layers (e.g., M1 + M3). The second part 114 of the first trace character line 110 may be composed of two fourth wires respectively disposed by crossing a second combination of a plurality of metallization layers (e.g., M1 + M5). The present disclosure provides a trace plan that introduces changes to a trace plan (e.g., the first trace character line 110) in an SRAM design. The first trace character line 110 uses M1 + M3 in the first half (e.g., the first part 112) and M1 + M5 in the second half (e.g., the second part 114) for the trace character line path. The first combination may be different from the second combination. In some embodiments, the first trace character line 110 is used to trace the propagation time present on the access character line 106. The first part 112 of the first trace character line 110 extends from the edge of the memory array 102 to the middle of the memory array 102, and the second part 114 of the first trace character line 110 extends from the middle of the memory array 102 to the edge of the memory array 102. This trace plan method is versatile and can be applied to various advanced SRAM processes, providing improved performance and resilience.

[0155] The trace plan proposed in the present disclosure improves the performance of SRAM design by changing the trace path and combining address decoding. Specifically, the trace character line path utilizes M1 + M3 in the first half and M1 + M5 in the second half. This combination allows for more accurate tracking of the actual character line RC delay. The trace plan method proposed in the present disclosure is applicable to all advanced SRAM processes, with compatibility and versatility. The advantages of the present disclosure include reducing the variation of the macro data output delay (Tcd) and compatibility with all advanced SRAM processes. By minimizing the variation of the macro data output delay (Tcd), the trace plan proposed in the present disclosure improves the consistency and reliability of SRAM operation. The trace plan proposed in the present disclosure can be compatible with various advanced SRAM processes.

[0156] As used herein, the terms "about" and "approximately" generally indicate a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may indicate a value of a given quantity that varies within, for example, 10% to 30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0157] The present disclosure provides a memory device of an aspect, including a memory array, a plurality of access word lines, and a first tracking word line. The memory array includes a plurality of bit cells arranged on a plurality of rows and a plurality of columns. The plurality of access word lines extend along a lateral direction. The plurality of rows respectively correspond to the plurality of access word lines. The first tracking word line extends along the lateral direction and has a first portion and a second portion. The first portion extends from an edge of the memory array to a middle of the memory array, and the second portion extends from the middle of the memory array to the edge of the memory array. The first portion of the first tracking word line includes at least two first conductors, and the at least two first conductors are respectively disposed across a first combination of a plurality of metallization layers. The second portion of the first tracking word line includes at least two second conductors, and the at least two second conductors are respectively disposed across a second combination of the plurality of metallization layers. The first combination is different from the second combination.

[0158] In some embodiments of the memory device of this aspect, the first combination includes a first metallization layer among the plurality of metallization layers and a second metallization layer among the plurality of metallization layers. The first metallization layer is the first closest to the memory array among the plurality of metallization layers, and the second metallization layer is the fifth closest to the memory array among the plurality of metallization layers. The second combination includes the first metallization layer and a third metallization layer among the plurality of metallization layers. The third metallization layer is the third closest to the memory array among the plurality of metallization layers.

[0159] In some embodiments of the memory device of this aspect, the first combination includes a first metallization layer among the plurality of metallization layers. The first metallization layer is the fifth closest to the memory array among the plurality of metallization layers. The second combination includes a second metallization layer among the plurality of metallization layers and a third metallization layer among the plurality of metallization layers. The second metallization layer is the first closest to the memory array among the plurality of metallization layers, and the third metallization layer is the third closest to the memory array among the plurality of metallization layers.

[0160] In some embodiments of the memory device of this aspect, the first combination includes a first metallization layer among the plurality of metallization layers and a second metallization layer among the plurality of metallization layers. The first metallization layer is the first closest to the memory array among the plurality of metallization layers, and the second metallization layer is the fifth closest to the memory array among the plurality of metallization layers. The second combination includes a third metallization layer among the plurality of metallization layers. The third metallization layer is the third closest to the memory array among the plurality of metallization layers.

[0161] In some embodiments of the memory device of this aspect, the at least two first conductors are coupled to each other via a plurality of first via structures, and the at least two second conductors are coupled to each other via a plurality of second via structures.

[0162] In some embodiments of the memory device in this aspect, at least one of the at least two first wires is further coupled to a plurality of third via structures, and at least one of the at least two second wires is further coupled to a plurality of fourth via structures.

[0163] In some embodiments of the memory device in this aspect, the memory device further includes a second trace character line and a third trace character line. The second trace character line extends along a lateral direction and has a first portion and a second portion. The first portion of the second trace character line extends from an edge of the memory array to a middle of the memory array, and the second portion of the second trace character line extends from the middle of the memory array to the edge of the memory array. The third trace character line extends along the lateral direction and has a first portion and a second portion. The first portion of the third trace character line extends from the edge of the memory array to the middle of the memory array, and the second portion of the third trace character line extends from the middle of the memory array to the edge of the memory array.

[0164] In some embodiments of the memory device in this aspect, the first trace character line, the second trace character line, and the third trace character line are each used to trace the propagation time existing on a plurality of access character lines.

[0165] In some embodiments of the memory device in this aspect, the first portion of the second trace character line includes at least two third wires, and the at least two third wires are respectively disposed across a first combination of a plurality of metallization layers. The second portion of the second trace character line includes at least two fourth wires, and the at least two fourth wires are respectively disposed across the first combination of the plurality of metallization layers.

[0166] In some embodiments of the memory device in this aspect, the first portion of the third trace character line includes at least two fifth wires, and the at least two fifth wires are respectively disposed across a second combination of a plurality of metallization layers. The second portion of the third trace character line includes at least two sixth wires, and the at least two sixth wires are respectively disposed across the second combination of the plurality of metallization layers.

[0167] In some embodiments of the memory device in this aspect, the second trace character line and the third trace character line are each selected based on a signal for decoding one of the plurality of access character lines, and the first trace character line is selected independently of the signal.

[0168] This disclosure provides another aspect of a memory device, including a plurality of access word lines and a first tracking word line. The plurality of access word lines extend along a lateral direction and respectively correspond to a plurality of rows of a memory array. The first tracking word line extends along the lateral direction and has a first portion and a second portion. A plurality of even access word lines among the plurality of access word lines each include two first conductors, and the two first conductors are respectively disposed across a first combination of a plurality of metallization layers. A plurality of odd access word lines among the plurality of access word lines each include two second conductors, and the two second conductors are respectively disposed across a second combination of a plurality of metallization layers. The first portion of the first tracking word line includes two third conductors, and the two third conductors are respectively disposed across the first combination of a plurality of metallization layers. The second portion of the first tracking word line includes two fourth conductors, and the two fourth conductors are respectively disposed across the second combination of a plurality of metallization layers. The first combination is different from the second combination.

[0169] In some embodiments of another aspect of the memory device, the first combination includes a first metallization layer among the plurality of metallization layers and a second metallization layer among the plurality of metallization layers. The first metallization layer is the first closest to the memory array among the plurality of metallization layers, and the second metallization layer is the fifth closest to the memory array among the plurality of metallization layers. And the second combination includes the first metallization layer and a third metallization layer among the plurality of metallization layers. The third metallization layer is the third closest to the memory array among the plurality of metallization layers.

[0170] In some embodiments of another aspect of the memory device, the two third conductors are coupled to each other via a plurality of first via structures, and the two fourth conductors are coupled to each other via a plurality of second via structures.

[0171] In some embodiments of another aspect of the memory device, one of the two third conductors is further coupled to a plurality of third via structures, and one of the two fourth conductors is further coupled to a plurality of fourth via structures.

[0172] In some embodiments of another aspect of the memory device, the memory device further includes a second tracking word line and a third tracking word line. The second tracking word line extends along the lateral direction and has a first portion and a second portion. The third tracking word line extends along the lateral direction and has a first portion and a second portion. The first portion of the second tracking word line includes two fifth conductors, and the two fifth conductors are respectively disposed across the first combination of a plurality of metallization layers. And the second portion of the second tracking word line includes at least two sixth conductors, and the at least two sixth conductors are respectively disposed across the first combination of a plurality of metallization layers. The first portion of the third tracking word line includes at least two seventh conductors, and the at least two seventh conductors are respectively disposed across the second combination of a plurality of metallization layers. And the second portion of the second tracking word line includes at least two eighth conductors, and the at least two eighth conductors are respectively disposed across the second combination of a plurality of metallization layers.

[0173] In some embodiments of another aspect of the memory device, the second tracking word line and the third tracking word line are each selected based on a signal that decodes one of the plurality of access word lines, while the first tracking word line is selected independently of the signal.

[0174] The present disclosure provides a manufacturing method for manufacturing a plurality of memory devices. The manufacturing method includes the steps of: forming a memory array along a main surface of a substrate, the memory array including a plurality of bit cells arranged in a plurality of rows and a plurality of columns; forming a plurality of access word lines that extend along a lateral direction and are operatively coupled to the plurality of rows respectively, wherein a plurality of even access word lines among the plurality of access word lines each include two first conductors that are respectively disposed across a first combination of a plurality of metallization layers disposed above the main surface, and a plurality of odd access word lines among the plurality of access word lines each include two second conductors that are respectively disposed across a second combination of a plurality of metallization layers; and forming a tracking word line that extends along the lateral direction and has a first portion and a second portion. The first portion of the tracking word line includes two third conductors that are respectively disposed across the first combination of the plurality of metallization layers. The second portion of the tracking word line includes two fourth conductors that are respectively disposed across the second combination of the plurality of metallization layers. The first combination is different from the second combination.

[0175] In some embodiments of the manufacturing method, the tracking word line is used to track the propagation time present on the plurality of access word lines.

[0176] In some embodiments of the manufacturing method, the first portion of the tracking word line extends from an edge of the memory array to a middle of the memory array, and the second portion of the tracking word line extends from the middle of the memory array to an edge of the memory array.

[0177] The present disclosure provides a memory device, comprising: a memory array disposed along a main surface of a substrate and including a plurality of bit cells configured on a plurality of rows and a plurality of columns; a plurality of access word lines extending along a lateral direction and operatively coupled to the plurality of rows respectively, wherein a plurality of even access word lines among the plurality of access word lines each include two first conductors respectively disposed across a first combination of a plurality of metallization layers disposed above the main surface, and a plurality of odd access word lines among the plurality of access word lines each include two second conductors respectively disposed across a second combination of the plurality of metallization layers; and a trace word line extending along the lateral direction and having a first portion and a second portion. The first portion of the trace word line includes two third conductors respectively disposed across the first combination of the plurality of metallization layers. The second portion of the trace word line includes two fourth conductors respectively disposed across the second combination of the plurality of metallization layers. The first combination is different from the second combination.

[0178] The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for the same purposes and / or achieving the same advantages as those introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that such equivalent constructions may be made herein without departing from the spirit and scope of the present disclosure by various changes, substitutions, and alterations.

Claims

1. A memory device, characterized in that, Comprising: A memory array including a plurality of bit cells disposed on a plurality of rows and a plurality of columns; A plurality of access word lines extending along a lateral direction, with each of the plurality of rows corresponding to one of the plurality of access word lines; And A first tracking word line extending along the lateral direction and having a first portion and a second portion, the first portion extending from an edge of the memory array to a middle of the memory array, and the second portion extending from the middle of the memory array to the edge of the memory array, wherein the first portion of the first tracking word line includes at least two first conductors respectively disposed across a first combination of a plurality of metallization layers, and the second portion of the first tracking word line includes at least two second conductors respectively disposed across a second combination of the plurality of metallization layers, and wherein the first combination is different from the second combination.

2. The memory device according to claim 1, wherein Wherein the first combination includes a first metallization layer among the plurality of metallization layers and a second metallization layer among the plurality of metallization layers, the first metallization layer is the first closest to the memory array among the plurality of metallization layers, the second metallization layer is the fifth closest to the memory array among the plurality of metallization layers, and the second combination includes the first metallization layer and a third metallization layer among the plurality of metallization layers, the third metallization layer is the third closest to the memory array among the plurality of metallization layers.

3. The memory device according to claim 1, wherein, Wherein the first combination includes a first metallization layer among the plurality of metallization layers, the first metallization layer is the fifth closest to the memory array among the plurality of metallization layers, and the second combination includes a second metallization layer among the plurality of metallization layers and a third metallization layer among the plurality of metallization layers, the second metallization layer is the first closest to the memory array among the plurality of metallization layers, the third metallization layer is the third closest to the memory array among the plurality of metallization layers.

4. The memory device according to claim 1, wherein Wherein the first combination includes a first metallization layer among the plurality of metallization layers and a second metallization layer among the plurality of metallization layers, the first metallization layer is the first closest to the memory array among the plurality of metallization layers, the second metallization layer is the fifth closest to the memory array among the plurality of metallization layers, and the second combination includes a third metallization layer among the plurality of metallization layers, the third metallization layer is the third closest to the memory array among the plurality of metallization layers.

5. The memory device according to claim 1, characterized in that, Wherein the at least two first conductors are coupled to each other via a plurality of first via structures, and the at least two second conductors are coupled to each other via a plurality of second via structures.

6. The memory device according to claim 1, wherein, Further comprising: A second tracking word line extending along the lateral direction and having a first portion and a second portion, the first portion of the second tracking word line extending from the edge of the memory array to the middle of the memory array, and the second portion of the second tracking word line extending from the middle of the memory array to the edge of the memory array; and A third tracking character line extends along the lateral direction and has a first part and a second part. The first part of the third tracking character line extends from the edge of the memory array to the middle of the memory array, and the second part of the third tracking character line extends from the middle of the memory array to the edge of the memory array.

7. The memory device according to claim 6, wherein, Wherein the first part of the second tracking character line includes at least two third conductors, the at least two third conductors are respectively disposed across the first combination of the plurality of metallization layers, and the second part of the second tracking character line includes at least two fourth conductors, the at least two fourth conductors are respectively disposed across the first combination of the plurality of metallization layers.

8. The memory device according to claim 7, characterized in that, Wherein the first part of the third tracking character line includes at least two fifth conductors, the at least two fifth conductors are respectively disposed across the second combination of the plurality of metallization layers, and the second part of the third tracking character line includes at least two sixth conductors, the at least two sixth conductors are respectively disposed across the second combination of the plurality of metallization layers.

9. A memory device, characterized in that, Comprising: A plurality of access character lines extending along a lateral direction and respectively corresponding to a plurality of rows of a memory array; and A first tracking character line extending along the lateral direction and having a first part and a second part, Wherein a plurality of even access character lines among the plurality of access character lines each include two first conductors, the two first conductors are respectively disposed across a first combination of a plurality of metallization layers, Wherein a plurality of odd access character lines among the plurality of access character lines each include two second conductors, the two second conductors are respectively disposed across a second combination of the plurality of metallization layers, Wherein the first part of the first tracking character line includes two third conductors, the two third conductors are respectively disposed across the first combination of the plurality of metallization layers, and the second part of the first tracking character line includes two fourth conductors, the two fourth conductors are respectively disposed across the second combination of the plurality of metallization layers, and Wherein the first combination is different from the second combination.

10. A memory device, characterized in that, Comprising: A memory array along a main surface of a substrate and including a plurality of bit cells arranged in a plurality of rows and a plurality of columns; A plurality of access character lines extending along a lateral direction and respectively coupled to the plurality of rows. Among the plurality of access character lines, a plurality of even access character lines each include two first conductors, the two first conductors are respectively disposed across a first combination of a plurality of metallization layers disposed above the main surface, and a plurality of odd access character lines among the plurality of access character lines each include two second conductors, the two second conductors are respectively disposed across a second combination of the plurality of metallization layers; and A tracking character line extending along the lateral direction and having a first part and a second part, Wherein the first part of the tracking character line includes two third conductors, the two third conductors are respectively disposed across the first combination of the plurality of metallization layers, and the second part of the tracking character line includes two fourth conductors, the two fourth conductors are respectively disposed across the second combination of the plurality of metallization layers, and Wherein the first combination is different from the second combination.

Images